Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2136	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2207	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2149	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	1950	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2242	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2138	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2287	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2161	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2169	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2212	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2101	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2125	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2084	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2030	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2062	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2198	0	0
adc_en_ctl_rd_A	2147483647	1568	0	0
adc_fsm_rst_rd_A	2147483647	1568	0	0
adc_intr_ctl_rd_A	2147483647	2085	0	0
adc_lp_sample_ctl_rd_A	2147483647	1406	0	0
adc_pd_ctl_rd_A	2147483647	1954	0	0
adc_sample_ctl_rd_A	2147483647	1436	0	0
adc_wakeup_ctl_rd_A	2147483647	1671	0	0
intr_enable_rd_A	2147483647	2238	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2136	0	0
T12	318010	36	0	0
T13	598417	29	0	0
T14	0	21	0	0
T15	0	32	0	0
T16	0	26	0	0
T17	0	1	0	0
T18	0	39	0	0
T19	0	18	0	0
T20	0	38	0	0
T21	0	32	0	0
T22	159078	0	0	0
T23	189794	0	0	0
T24	479769	0	0	0
T25	280214	0	0	0
T26	290862	0	0	0
T27	358243	0	0	0
T28	414594	0	0	0
T29	473218	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2207	0	0
T12	318010	40	0	0
T13	598417	21	0	0
T14	0	21	0	0
T15	0	27	0	0
T16	0	15	0	0
T17	0	9	0	0
T18	0	26	0	0
T19	0	15	0	0
T20	0	26	0	0
T21	0	22	0	0
T22	159078	0	0	0
T23	189794	0	0	0
T24	479769	0	0	0
T25	280214	0	0	0
T26	290862	0	0	0
T27	358243	0	0	0
T28	414594	0	0	0
T29	473218	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2149	0	0
T12	318010	34	0	0
T13	598417	16	0	0
T14	0	21	0	0
T15	0	35	0	0
T16	0	17	0	0
T17	0	8	0	0
T18	0	16	0	0
T19	0	10	0	0
T20	0	47	0	0
T21	0	29	0	0
T22	159078	0	0	0
T23	189794	0	0	0
T24	479769	0	0	0
T25	280214	0	0	0
T26	290862	0	0	0
T27	358243	0	0	0
T28	414594	0	0	0
T29	473218	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1950	0	0
T12	318010	27	0	0
T13	598417	23	0	0
T14	0	22	0	0
T15	0	42	0	0
T16	0	15	0	0
T17	0	1	0	0
T18	0	17	0	0
T19	0	6	0	0
T20	0	25	0	0
T21	0	26	0	0
T22	159078	0	0	0
T23	189794	0	0	0
T24	479769	0	0	0
T25	280214	0	0	0
T26	290862	0	0	0
T27	358243	0	0	0
T28	414594	0	0	0
T29	473218	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2242	0	0
T12	318010	39	0	0
T13	598417	19	0	0
T14	0	15	0	0
T15	0	38	0	0
T16	0	18	0	0
T17	0	4	0	0
T18	0	19	0	0
T19	0	17	0	0
T20	0	39	0	0
T21	0	22	0	0
T22	159078	0	0	0
T23	189794	0	0	0
T24	479769	0	0	0
T25	280214	0	0	0
T26	290862	0	0	0
T27	358243	0	0	0
T28	414594	0	0	0
T29	473218	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2138	0	0
T12	318010	42	0	0
T13	598417	19	0	0
T14	0	18	0	0
T15	0	44	0	0
T16	0	15	0	0
T17	0	10	0	0
T18	0	16	0	0
T19	0	30	0	0
T20	0	32	0	0
T21	0	32	0	0
T22	159078	0	0	0
T23	189794	0	0	0
T24	479769	0	0	0
T25	280214	0	0	0
T26	290862	0	0	0
T27	358243	0	0	0
T28	414594	0	0	0
T29	473218	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2287	0	0
T12	318010	32	0	0
T13	598417	12	0	0
T14	0	13	0	0
T15	0	19	0	0
T16	0	16	0	0
T17	0	5	0	0
T18	0	19	0	0
T19	0	23	0	0
T20	0	49	0	0
T21	0	18	0	0
T22	159078	0	0	0
T23	189794	0	0	0
T24	479769	0	0	0
T25	280214	0	0	0
T26	290862	0	0	0
T27	358243	0	0	0
T28	414594	0	0	0
T29	473218	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2161	0	0
T12	318010	40	0	0
T13	598417	14	0	0
T14	0	16	0	0
T15	0	28	0	0
T16	0	19	0	0
T17	0	6	0	0
T18	0	18	0	0
T19	0	18	0	0
T20	0	29	0	0
T21	0	27	0	0
T22	159078	0	0	0
T23	189794	0	0	0
T24	479769	0	0	0
T25	280214	0	0	0
T26	290862	0	0	0
T27	358243	0	0	0
T28	414594	0	0	0
T29	473218	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2169	0	0
T12	318010	43	0	0
T13	598417	22	0	0
T14	0	10	0	0
T15	0	31	0	0
T16	0	23	0	0
T18	0	36	0	0
T19	0	22	0	0
T20	0	42	0	0
T21	0	36	0	0
T22	159078	0	0	0
T23	189794	0	0	0
T24	479769	0	0	0
T25	280214	0	0	0
T26	290862	0	0	0
T27	358243	0	0	0
T28	414594	0	0	0
T29	473218	0	0	0
T30	0	21	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2212	0	0
T12	318010	42	0	0
T13	598417	22	0	0
T14	0	25	0	0
T15	0	48	0	0
T16	0	19	0	0
T17	0	5	0	0
T18	0	8	0	0
T19	0	20	0	0
T20	0	31	0	0
T21	0	28	0	0
T22	159078	0	0	0
T23	189794	0	0	0
T24	479769	0	0	0
T25	280214	0	0	0
T26	290862	0	0	0
T27	358243	0	0	0
T28	414594	0	0	0
T29	473218	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2101	0	0
T12	318010	36	0	0
T13	598417	29	0	0
T14	0	20	0	0
T15	0	40	0	0
T16	0	27	0	0
T17	0	10	0	0
T18	0	14	0	0
T19	0	22	0	0
T20	0	37	0	0
T21	0	34	0	0
T22	159078	0	0	0
T23	189794	0	0	0
T24	479769	0	0	0
T25	280214	0	0	0
T26	290862	0	0	0
T27	358243	0	0	0
T28	414594	0	0	0
T29	473218	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2125	0	0
T12	318010	45	0	0
T13	598417	23	0	0
T14	0	14	0	0
T15	0	44	0	0
T16	0	10	0	0
T17	0	9	0	0
T18	0	25	0	0
T19	0	25	0	0
T20	0	35	0	0
T21	0	19	0	0
T22	159078	0	0	0
T23	189794	0	0	0
T24	479769	0	0	0
T25	280214	0	0	0
T26	290862	0	0	0
T27	358243	0	0	0
T28	414594	0	0	0
T29	473218	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2084	0	0
T12	318010	31	0	0
T13	598417	15	0	0
T14	0	19	0	0
T15	0	31	0	0
T16	0	31	0	0
T17	0	2	0	0
T18	0	16	0	0
T19	0	26	0	0
T20	0	33	0	0
T21	0	32	0	0
T22	159078	0	0	0
T23	189794	0	0	0
T24	479769	0	0	0
T25	280214	0	0	0
T26	290862	0	0	0
T27	358243	0	0	0
T28	414594	0	0	0
T29	473218	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2030	0	0
T12	318010	32	0	0
T13	598417	24	0	0
T14	0	17	0	0
T15	0	24	0	0
T16	0	2	0	0
T17	0	1	0	0
T18	0	20	0	0
T19	0	15	0	0
T20	0	43	0	0
T21	0	45	0	0
T22	159078	0	0	0
T23	189794	0	0	0
T24	479769	0	0	0
T25	280214	0	0	0
T26	290862	0	0	0
T27	358243	0	0	0
T28	414594	0	0	0
T29	473218	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2062	0	0
T12	318010	24	0	0
T13	598417	11	0	0
T14	0	36	0	0
T15	0	21	0	0
T16	0	25	0	0
T17	0	2	0	0
T18	0	27	0	0
T19	0	26	0	0
T20	0	30	0	0
T21	0	23	0	0
T22	159078	0	0	0
T23	189794	0	0	0
T24	479769	0	0	0
T25	280214	0	0	0
T26	290862	0	0	0
T27	358243	0	0	0
T28	414594	0	0	0
T29	473218	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2198	0	0
T12	318010	32	0	0
T13	598417	36	0	0
T14	0	22	0	0
T15	0	24	0	0
T16	0	11	0	0
T17	0	1	0	0
T18	0	31	0	0
T19	0	26	0	0
T20	0	40	0	0
T21	0	24	0	0
T22	159078	0	0	0
T23	189794	0	0	0
T24	479769	0	0	0
T25	280214	0	0	0
T26	290862	0	0	0
T27	358243	0	0	0
T28	414594	0	0	0
T29	473218	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1568	0	0
T12	318010	39	0	0
T13	598417	14	0	0
T14	0	21	0	0
T15	0	36	0	0
T16	0	9	0	0
T17	0	9	0	0
T18	0	11	0	0
T19	0	14	0	0
T20	0	44	0	0
T21	0	27	0	0
T22	159078	0	0	0
T23	189794	0	0	0
T24	479769	0	0	0
T25	280214	0	0	0
T26	290862	0	0	0
T27	358243	0	0	0
T28	414594	0	0	0
T29	473218	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1568	0	0
T12	318010	32	0	0
T13	598417	26	0	0
T14	0	3	0	0
T15	0	42	0	0
T16	0	20	0	0
T17	0	20	0	0
T18	0	35	0	0
T19	0	9	0	0
T20	0	30	0	0
T21	0	30	0	0
T22	159078	0	0	0
T23	189794	0	0	0
T24	479769	0	0	0
T25	280214	0	0	0
T26	290862	0	0	0
T27	358243	0	0	0
T28	414594	0	0	0
T29	473218	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2085	0	0
T12	318010	40	0	0
T13	598417	12	0	0
T14	0	14	0	0
T15	0	17	0	0
T16	0	14	0	0
T17	0	9	0	0
T18	0	29	0	0
T19	0	21	0	0
T20	0	57	0	0
T21	0	25	0	0
T22	159078	0	0	0
T23	189794	0	0	0
T24	479769	0	0	0
T25	280214	0	0	0
T26	290862	0	0	0
T27	358243	0	0	0
T28	414594	0	0	0
T29	473218	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1406	0	0
T12	318010	35	0	0
T13	598417	15	0	0
T14	0	20	0	0
T15	0	32	0	0
T16	0	4	0	0
T17	0	9	0	0
T18	0	13	0	0
T19	0	14	0	0
T20	0	26	0	0
T21	0	14	0	0
T22	159078	0	0	0
T23	189794	0	0	0
T24	479769	0	0	0
T25	280214	0	0	0
T26	290862	0	0	0
T27	358243	0	0	0
T28	414594	0	0	0
T29	473218	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1954	0	0
T12	318010	39	0	0
T13	598417	29	0	0
T14	0	16	0	0
T15	0	25	0	0
T16	0	10	0	0
T17	0	3	0	0
T18	0	29	0	0
T19	0	40	0	0
T20	0	32	0	0
T21	0	19	0	0
T22	159078	0	0	0
T23	189794	0	0	0
T24	479769	0	0	0
T25	280214	0	0	0
T26	290862	0	0	0
T27	358243	0	0	0
T28	414594	0	0	0
T29	473218	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1436	0	0
T12	318010	35	0	0
T13	598417	19	0	0
T14	0	18	0	0
T15	0	14	0	0
T16	0	13	0	0
T17	0	3	0	0
T18	0	40	0	0
T19	0	6	0	0
T20	0	28	0	0
T21	0	26	0	0
T22	159078	0	0	0
T23	189794	0	0	0
T24	479769	0	0	0
T25	280214	0	0	0
T26	290862	0	0	0
T27	358243	0	0	0
T28	414594	0	0	0
T29	473218	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1671	0	0
T12	318010	24	0	0
T13	598417	14	0	0
T14	0	13	0	0
T15	0	32	0	0
T16	0	29	0	0
T17	0	7	0	0
T18	0	36	0	0
T19	0	30	0	0
T20	0	37	0	0
T21	0	23	0	0
T22	159078	0	0	0
T23	189794	0	0	0
T24	479769	0	0	0
T25	280214	0	0	0
T26	290862	0	0	0
T27	358243	0	0	0
T28	414594	0	0	0
T29	473218	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2238	0	0
T12	318010	73	0	0
T13	598417	61	0	0
T14	0	7	0	0
T15	0	31	0	0
T16	0	11	0	0
T17	0	17	0	0
T18	0	36	0	0
T19	0	65	0	0
T22	159078	0	0	0
T23	189794	0	0	0
T24	479769	0	0	0
T25	280214	0	0	0
T26	290862	0	0	0
T27	358243	0	0	0
T28	414594	0	0	0
T29	473218	0	0	0
T31	0	38	0	0
T32	0	26	0	0