Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1185972	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1164049

1

T1

2111

T2

1404

T3

1151

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2057021	1			T1	3998		T2	2506		T3	1797
values[0x0]	146182	1			T1	117		T2	166		T3	223
values[0x1]	146818	1			T1	142		T2	151		T3	219

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	950450	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1399571

1

T1

2525

T2

1699

T3

1362

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	16434	1			T3	10		T6	27		T8	14
valid_sources[0x01]	6435	1			T1	22		T3	11		T6	38
valid_sources[0x02]	11132	1			T1	29		T3	4		T5	1
valid_sources[0x03]	6287	1			T1	1		T3	2		T6	29
valid_sources[0x04]	11005	1			T1	27		T3	1		T6	27
valid_sources[0x05]	10867	1			T1	11		T3	10		T5	1
valid_sources[0x06]	6565	1			T1	15		T3	10		T6	44
valid_sources[0x07]	11632	1			T1	31		T3	4		T6	38
valid_sources[0x08]	7031	1			T1	20		T3	10		T5	1
valid_sources[0x09]	15468	1			T1	13		T3	6		T6	25
valid_sources[0x0a]	8242	1			T1	8		T3	5		T6	51
valid_sources[0x0b]	6921	1			T1	46		T3	7		T6	30
valid_sources[0x0c]	9413	1			T1	12		T3	2		T6	51
valid_sources[0x0d]	6930	1			T3	1		T5	1		T6	34
valid_sources[0x0e]	11893	1			T1	14		T3	7		T6	26
valid_sources[0x0f]	9613	1			T1	17		T3	2		T6	44
valid_sources[0x10]	11033	1			T1	2		T3	7		T6	51
valid_sources[0x11]	12573	1			T1	44		T3	11		T4	1710
valid_sources[0x12]	7275	1			T1	10		T3	6		T6	32
valid_sources[0x13]	9181	1			T1	5		T3	11		T6	29
valid_sources[0x14]	7111	1			T3	6		T6	27		T8	24
valid_sources[0x15]	13698	1			T1	56		T3	8		T5	1
valid_sources[0x16]	6768	1			T1	72		T3	4		T5	1
valid_sources[0x17]	7644	1			T1	5		T3	8		T6	35
valid_sources[0x18]	10944	1			T1	11		T3	10		T6	30
valid_sources[0x19]	8787	1			T1	15		T3	4		T6	28
valid_sources[0x1a]	10933	1			T1	31		T3	5		T6	46
valid_sources[0x1b]	8495	1			T1	11		T3	4		T5	1
valid_sources[0x1c]	11681	1			T1	22		T3	12		T6	46
valid_sources[0x1d]	6912	1			T1	23		T3	8		T6	39
valid_sources[0x1e]	6285	1			T1	7		T3	2		T6	40
valid_sources[0x1f]	8830	1			T1	33		T3	2		T6	46
valid_sources[0x20]	6703	1			T1	10		T3	6		T6	44
valid_sources[0x21]	6236	1			T1	29		T3	2		T6	33
valid_sources[0x22]	11323	1			T1	50		T3	5		T6	37
valid_sources[0x23]	11248	1			T1	12		T3	9		T6	23
valid_sources[0x24]	6851	1			T3	8		T6	28		T8	6
valid_sources[0x25]	15266	1			T1	12		T3	10		T4	1
valid_sources[0x26]	7901	1			T1	15		T3	4		T4	15
valid_sources[0x27]	11867	1			T1	14		T3	10		T6	37
valid_sources[0x28]	9996	1			T1	1		T3	6		T6	30
valid_sources[0x29]	11424	1			T1	28		T3	6		T6	23
valid_sources[0x2a]	6586	1			T1	12		T3	5		T6	36
valid_sources[0x2b]	11243	1			T1	51		T3	10		T6	33
valid_sources[0x2c]	6422	1			T1	11		T3	6		T6	36
valid_sources[0x2d]	11261	1			T1	13		T3	5		T6	47
valid_sources[0x2e]	6076	1			T1	35		T3	3		T6	26
valid_sources[0x2f]	10727	1			T1	13		T3	10		T6	31
valid_sources[0x30]	11038	1			T1	3		T3	5		T5	1
valid_sources[0x31]	12949	1			T1	8		T3	4		T6	39
valid_sources[0x32]	9470	1			T1	24		T3	5		T6	38
valid_sources[0x33]	11532	1			T1	28		T3	5		T6	25
valid_sources[0x34]	8391	1			T1	14		T3	9		T6	25
valid_sources[0x35]	6333	1			T1	1		T3	3		T6	24
valid_sources[0x36]	8302	1			T1	22		T3	4		T5	2
valid_sources[0x37]	6689	1			T1	52		T3	5		T6	13
valid_sources[0x38]	11039	1			T1	5		T3	8		T6	22
valid_sources[0x39]	9523	1			T1	42		T3	5		T5	1
valid_sources[0x3a]	10504	1			T1	25		T3	4		T6	30
valid_sources[0x3b]	7696	1			T1	28		T3	10		T6	34
valid_sources[0x3c]	9410	1			T1	17		T3	10		T5	2
valid_sources[0x3d]	6533	1			T1	13		T3	6		T6	42
valid_sources[0x3e]	10937	1			T1	9		T3	6		T6	32
valid_sources[0x3f]	7232	1			T1	3		T3	5		T6	33
valid_sources[0x40]	6497	1			T1	2		T3	11		T6	45
valid_sources[0x41]	6617	1			T1	21		T3	5		T6	46
valid_sources[0x42]	6343	1			T3	14		T6	34		T8	6
valid_sources[0x43]	10948	1			T1	2		T3	2		T5	1
valid_sources[0x44]	6526	1			T1	12		T3	5		T6	43
valid_sources[0x45]	14673	1			T1	4		T3	3		T6	31
valid_sources[0x46]	8731	1			T1	36		T3	5		T6	44
valid_sources[0x47]	7770	1			T1	25		T3	7		T6	36
valid_sources[0x48]	8285	1			T1	5		T3	5		T6	41
valid_sources[0x49]	6573	1			T1	9		T3	6		T6	52
valid_sources[0x4a]	13447	1			T1	52		T3	7		T6	36
valid_sources[0x4b]	6700	1			T1	15		T3	6		T6	34
valid_sources[0x4c]	10758	1			T1	8		T3	3		T6	51
valid_sources[0x4d]	9096	1			T1	28		T3	2		T6	27
valid_sources[0x4e]	11065	1			T1	3		T3	14		T6	37
valid_sources[0x4f]	6727	1			T3	10		T6	44		T8	11
valid_sources[0x50]	11976	1			T1	49		T3	9		T6	20
valid_sources[0x51]	26216	1			T1	19		T3	3		T6	33
valid_sources[0x52]	6406	1			T1	27		T3	5		T6	40
valid_sources[0x53]	9419	1			T1	13		T3	9		T6	48
valid_sources[0x54]	10700	1			T1	25		T3	6		T6	38
valid_sources[0x55]	12275	1			T1	31		T2	2823		T3	10
valid_sources[0x56]	10827	1			T1	16		T3	8		T6	35
valid_sources[0x57]	10307	1			T1	9		T3	6		T4	3
valid_sources[0x58]	6337	1			T3	6		T6	30		T8	14
valid_sources[0x59]	6694	1			T1	22		T3	2		T6	42
valid_sources[0x5a]	10240	1			T1	7		T3	2		T6	30
valid_sources[0x5b]	8816	1			T1	3		T3	5		T6	54
valid_sources[0x5c]	6060	1			T1	10		T3	3		T6	27
valid_sources[0x5d]	11078	1			T1	19		T3	6		T6	29
valid_sources[0x5e]	6880	1			T1	19		T3	2		T6	39
valid_sources[0x5f]	10852	1			T1	3		T3	8		T4	15
valid_sources[0x60]	6986	1			T1	10		T3	6		T6	63
valid_sources[0x61]	21494	1			T1	53		T3	6		T6	52
valid_sources[0x62]	7216	1			T1	15		T3	6		T6	34
valid_sources[0x63]	7529	1			T1	2		T3	7		T5	1
valid_sources[0x64]	6467	1			T1	35		T3	5		T6	39
valid_sources[0x65]	6581	1			T1	10		T3	6		T6	38
valid_sources[0x66]	26108	1			T1	25		T3	5		T4	1030
valid_sources[0x67]	6397	1			T1	23		T3	6		T6	33
valid_sources[0x68]	11843	1			T1	21		T3	11		T5	1
valid_sources[0x69]	15644	1			T1	10		T3	2		T6	49
valid_sources[0x6a]	6753	1			T1	15		T3	6		T6	19
valid_sources[0x6b]	10455	1			T1	21		T3	7		T6	46
valid_sources[0x6c]	6921	1			T1	25		T3	9		T6	42
valid_sources[0x6d]	10378	1			T1	5		T3	6		T6	32
valid_sources[0x6e]	11917	1			T1	3		T3	7		T6	35
valid_sources[0x6f]	6815	1			T1	13		T3	9		T6	37
valid_sources[0x70]	10850	1			T1	6		T3	3		T6	37
valid_sources[0x71]	6368	1			T1	6		T3	11		T6	38
valid_sources[0x72]	6184	1			T1	11		T3	3		T6	46
valid_sources[0x73]	7252	1			T1	11		T3	9		T6	44
valid_sources[0x74]	6447	1			T1	27		T3	10		T5	1
valid_sources[0x75]	11603	1			T1	12		T3	6		T6	28
valid_sources[0x76]	13593	1			T1	10		T3	4		T4	15
valid_sources[0x77]	8729	1			T1	2		T3	4		T6	45
valid_sources[0x78]	6412	1			T1	30		T3	3		T6	37
valid_sources[0x79]	10581	1			T1	18		T3	4		T6	38
valid_sources[0x7a]	8569	1			T3	3		T4	993		T6	31
valid_sources[0x7b]	7850	1			T1	5		T3	5		T6	38
valid_sources[0x7c]	5931	1			T1	4		T3	7		T6	41
valid_sources[0x7d]	7785	1			T1	37		T3	10		T4	212
valid_sources[0x7e]	6431	1			T1	21		T3	7		T6	38
valid_sources[0x7f]	7661	1			T1	4		T3	7		T6	42
valid_sources[0x80]	8383	1			T1	20		T3	8		T6	50

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1026782

1

T1

2023

T2

1249

T3

877

values[0x0]

all_enables

biggest_size

79746

1

T1

53

T2

93

T3

142

values[0x1]

all_enables

biggest_size

57521

1

T1

35

T2

62

T3

132