Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.11	91.11	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	91.11	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.11	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	4	41	91.11

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	3	13	81.25	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	26877	1			T1	8		T2	25		T4	301
auto[PWRUP]	109	1			T4	2		T6	1		T10	1
auto[ONEST_0]	66	1			T4	2		T24	1		T163	1
auto[ONEST_021]	14	1			T40	1		T43	1		T200	2
auto[ONEST_1]	66	1			T4	1		T10	2		T40	2
auto[ONEST_DONE]	9	1			T40	1		T24	1		T201	1
auto[LP_0]	130	1			T4	2		T10	2		T40	1
auto[LP_021]	35	1			T6	1		T24	1		T32	1
auto[LP_1]	114	1			T4	2		T10	2		T202	1
auto[LP_EVAL]	66	1			T6	1		T10	1		T40	1
auto[LP_SLP]	471	1			T4	5		T6	5		T10	5
auto[LP_PWRUP]	27	1			T10	1		T40	1		T157	1
auto[NP_0]	169	1			T4	1		T6	2		T10	2
auto[NP_021]	37	1			T4	1		T40	1		T202	2
auto[NP_1]	159	1			T4	5		T6	1		T10	2
auto[NP_EVAL]	40	1			T6	1		T10	1		T202	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

7

1

T203

1

T36

1

T204

1

min

26361

1

T1

8

T2

25

T4

283

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	26369	1			T1	8		T2	25		T4	283
pow[0x1]	9	1			T10	1		T205	1		T206	1
pow[0x2]	21	1			T202	3		T163	1		T201	1
pow[0x3]	27	1			T4	1		T187	1		T163	1
pow[0x4]	55	1			T4	1		T10	1		T40	1
pow[0x5]	125	1			T4	4		T6	2		T10	2
pow[0x6]	284	1			T4	7		T6	3		T10	1
pow[0x7]	489	1			T4	8		T6	4		T10	6

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

191

1

T4

5

T6

3

T10

3

min

25930

1

T1

8

T2

25

T4

282

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	3	13	81.25

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	25930	1			T1	8		T2	25		T4	282
pow[0x1]	1	1			T207	1		-	-		-	-
pow[0x4]	1	1			T208	1		-	-		-	-
pow[0x5]	2	1			T105	1		T209	1		-	-
pow[0x7]	2	1			T210	1		T211	1		-	-
pow[0x8]	7	1			T212	1		T203	1		T200	1
pow[0x9]	11	1			T25	1		T213	1		T214	1
pow[0xa]	27	1			T6	1		T24	1		T163	1
pow[0xb]	31	1			T4	1		T6	1		T202	1
pow[0xc]	62	1			T4	1		T40	1		T202	1
pow[0xd]	124	1			T4	2		T6	1		T10	2
pow[0xe]	281	1			T4	7		T6	4		T10	6
pow[0xf]	604	1			T4	13		T6	4		T10	8