Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2279	1			T3	12		T4	36		T6	11
auto[PWRUP]	158	1			T4	4		T30	1		T40	1
auto[ONEST_0]	66	1			T4	1		T40	2		T202	1
auto[ONEST_021]	19	1			T4	1		T40	1		T43	1
auto[ONEST_1]	87	1			T10	2		T40	2		T24	1
auto[ONEST_DONE]	5	1			T157	1		T336	1		T337	1
auto[LP_0]	116	1			T4	3		T6	1		T10	1
auto[LP_021]	27	1			T4	1		T6	1		T40	1
auto[LP_1]	152	1			T3	1		T4	3		T40	1
auto[LP_EVAL]	54	1			T10	1		T202	2		T24	1
auto[LP_SLP]	529	1			T4	7		T6	6		T10	5
auto[LP_PWRUP]	30	1			T4	1		T187	1		T33	1
auto[NP_0]	205	1			T3	3		T4	4		T6	2
auto[NP_021]	50	1			T3	1		T4	1		T40	1
auto[NP_1]	223	1			T3	2		T4	7		T6	2
auto[NP_EVAL]	29	1			T3	1		T6	1		T10	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

8

1

T214

1

T338

1

T210

1

min

1879

1

T3

19

T4

30

T6

10

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1895	1			T3	19		T4	30		T6	10
pow[0x1]	9	1			T4	1		T34	1		T14	1
pow[0x2]	20	1			T4	1		T40	1		T31	1
pow[0x3]	35	1			T3	1		T4	1		T40	2
pow[0x4]	67	1			T4	2		T202	1		T24	1
pow[0x5]	132	1			T4	2		T40	1		T202	1
pow[0x6]	291	1			T4	5		T6	1		T10	3
pow[0x7]	520	1			T4	7		T6	4		T10	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

183

1

T4

6

T6

1

T10

3

min

1321

1

T3

13

T4

16

T6

7

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1324	1			T3	13		T4	16		T6	7
pow[0x1]	7	1			T3	1		T281	1		T19	1
pow[0x2]	22	1			T3	4		T4	1		T28	2
pow[0x3]	28	1			T3	2		T28	1		T30	1
pow[0x4]	72	1			T4	4		T28	2		T30	2
pow[0x5]	2	1			T339	1		T340	1		-	-
pow[0x6]	1	1			T341	1		-	-		-	-
pow[0x7]	5	1			T205	1		T41	1		T342	1
pow[0x8]	5	1			T96	1		T213	1		T343	1
pow[0x9]	10	1			T187	2		T212	1		T96	1
pow[0xa]	18	1			T202	1		T24	1		T32	1
pow[0xb]	51	1			T4	4		T10	1		T40	1
pow[0xc]	106	1			T6	1		T10	1		T40	1
pow[0xd]	154	1			T4	1		T10	3		T40	2
pow[0xe]	275	1			T4	5		T6	2		T10	2
pow[0xf]	612	1			T4	16		T6	5		T10	3