Module Definition
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Module : adc_ctrl_fsm_sva
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_sva_0.1/adc_ctrl_fsm_sva.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva 100.00 100.00



Module Instance : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.75 100.00 100.00 100.00 98.73 100.00 u_adc_ctrl_fsm


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Assert Coverage for Module : adc_ctrl_fsm_sva
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 11 11 100.00 11 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 11 11 100.00 11 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
FsmDebugOut_A 31536670 31456964 0 0
FsmStateHwReset_A 1143 1143 0 0
FsmStateSwReset_A 31536670 6485 0 0
LpSampleCntHwReset_A 1143 1143 0 0
LpSampleCntSwReset_A 31536670 6485 0 0
NpSampleCntHwReset_A 1143 1143 0 0
NpSampleCntSwReset_A 31536670 6485 0 0
PwrupTimerCntHwReset_A 1143 1143 0 0
PwrupTimerCntSwReset_A 31536670 6485 0 0
WakeupTimerCntHwReset_A 1143 1143 0 0
WakeupTimerCntSwReset_A 31536670 6485 0 0


FsmDebugOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 31536670 31456964 0 0
T1 32568 32504 0 0
T2 97855 97798 0 0
T3 85 1 0 0
T4 63 1 0 0
T5 32145 32060 0 0
T6 65995 65699 0 0
T7 563 497 0 0
T8 97480 97403 0 0
T9 98500 98429 0 0
T10 69 1 0 0

FsmStateHwReset_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1143 1143 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 4 4 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

FsmStateSwReset_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 31536670 6485 0 0
T1 32568 8 0 0
T2 97855 25 0 0
T3 85 0 0 0
T4 63 0 0 0
T5 32145 11 0 0
T6 65995 10 0 0
T7 563 0 0 0
T8 97480 24 0 0
T9 98500 25 0 0
T10 69 0 0 0
T11 0 23 0 0
T12 0 10 0 0
T29 0 16 0 0
T76 0 8 0 0

LpSampleCntHwReset_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1143 1143 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 4 4 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

LpSampleCntSwReset_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 31536670 6485 0 0
T1 32568 8 0 0
T2 97855 25 0 0
T3 85 0 0 0
T4 63 0 0 0
T5 32145 11 0 0
T6 65995 10 0 0
T7 563 0 0 0
T8 97480 24 0 0
T9 98500 25 0 0
T10 69 0 0 0
T11 0 23 0 0
T12 0 10 0 0
T29 0 16 0 0
T76 0 8 0 0

NpSampleCntHwReset_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1143 1143 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 4 4 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

NpSampleCntSwReset_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 31536670 6485 0 0
T1 32568 8 0 0
T2 97855 25 0 0
T3 85 0 0 0
T4 63 0 0 0
T5 32145 11 0 0
T6 65995 10 0 0
T7 563 0 0 0
T8 97480 24 0 0
T9 98500 25 0 0
T10 69 0 0 0
T11 0 23 0 0
T12 0 10 0 0
T29 0 16 0 0
T76 0 8 0 0

PwrupTimerCntHwReset_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1143 1143 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 4 4 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

PwrupTimerCntSwReset_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 31536670 6485 0 0
T1 32568 8 0 0
T2 97855 25 0 0
T3 85 0 0 0
T4 63 0 0 0
T5 32145 11 0 0
T6 65995 10 0 0
T7 563 0 0 0
T8 97480 24 0 0
T9 98500 25 0 0
T10 69 0 0 0
T11 0 23 0 0
T12 0 10 0 0
T29 0 16 0 0
T76 0 8 0 0

WakeupTimerCntHwReset_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1143 1143 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 4 4 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

WakeupTimerCntSwReset_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 31536670 6485 0 0
T1 32568 8 0 0
T2 97855 25 0 0
T3 85 0 0 0
T4 63 0 0 0
T5 32145 11 0 0
T6 65995 10 0 0
T7 563 0 0 0
T8 97480 24 0 0
T9 98500 25 0 0
T10 69 0 0 0
T11 0 23 0 0
T12 0 10 0 0
T29 0 16 0 0
T76 0 8 0 0

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