Line Coverage for Module :
prim_reg_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Module :
prim_reg_cdc ( parameter DataWidth=2,ResetVal=0,BitMask=3,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal,BitMask,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal=4,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=16,ResetVal=155,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=28,ResetVal=0,BitMask=268374015,DstWrReq=1,TxnWidth=3 + DataWidth=9,ResetVal=0,BitMask=511,DstWrReq=0,TxnWidth=3 + DataWidth=9,ResetVal=0,BitMask=511,DstWrReq=1,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 15 | 13 | 86.67 |
Logical | 15 | 13 | 86.67 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T3,T4,T28 |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 13 | 12 | 92.31 |
Logical | 13 | 12 | 92.31 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T4 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 123
EXPRESSION (src_wd_i & BitMask)
----1--- ---2---
-1- | -2- | Status | Tests |
0 | - | Covered | T1,T2,T4 |
1 | - | Covered | T1,T2,T4 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T4 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Module :
prim_reg_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_reg_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
182722012 |
0 |
0 |
T1 |
8598194 |
8100 |
0 |
0 |
T2 |
2691018 |
31224 |
0 |
0 |
T3 |
12161592 |
206221 |
0 |
0 |
T4 |
14214504 |
626372 |
0 |
0 |
T5 |
2459280 |
35210 |
0 |
0 |
T6 |
9324792 |
1348015 |
0 |
0 |
T7 |
6646680 |
51739 |
0 |
0 |
T8 |
2807448 |
31404 |
0 |
0 |
T9 |
3073176 |
28869 |
0 |
0 |
T10 |
8608440 |
665093 |
0 |
0 |
T11 |
1027802 |
124416 |
0 |
0 |
T12 |
713814 |
4548 |
0 |
0 |
T28 |
0 |
1552 |
0 |
0 |
T29 |
0 |
570 |
0 |
0 |
T30 |
0 |
368 |
0 |
0 |
T31 |
0 |
500 |
0 |
0 |
T32 |
0 |
759 |
0 |
0 |
T33 |
0 |
1156 |
0 |
0 |
T34 |
0 |
1516 |
0 |
0 |
T35 |
0 |
1505 |
0 |
0 |
T36 |
0 |
1480 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
888585360 |
879577582 |
0 |
0 |
T1 |
846768 |
845104 |
0 |
0 |
T2 |
2544230 |
2542748 |
0 |
0 |
T3 |
572338 |
547560 |
0 |
0 |
T4 |
1231880 |
1112540 |
0 |
0 |
T5 |
835770 |
833560 |
0 |
0 |
T6 |
2126592 |
2079662 |
0 |
0 |
T7 |
14638 |
12922 |
0 |
0 |
T8 |
2534480 |
2532478 |
0 |
0 |
T9 |
2561000 |
2559154 |
0 |
0 |
T10 |
380588 |
339742 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
202425 |
0 |
0 |
T1 |
8598194 |
25 |
0 |
0 |
T2 |
2691018 |
75 |
0 |
0 |
T3 |
12161592 |
269 |
0 |
0 |
T4 |
14214504 |
1492 |
0 |
0 |
T5 |
2459280 |
26 |
0 |
0 |
T6 |
9324792 |
807 |
0 |
0 |
T7 |
6646680 |
31 |
0 |
0 |
T8 |
2807448 |
75 |
0 |
0 |
T9 |
3073176 |
75 |
0 |
0 |
T10 |
8608440 |
787 |
0 |
0 |
T11 |
1027802 |
63 |
0 |
0 |
T12 |
713814 |
16 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T29 |
0 |
2 |
0 |
0 |
T30 |
0 |
1 |
0 |
0 |
T31 |
0 |
1 |
0 |
0 |
T32 |
0 |
1 |
0 |
0 |
T33 |
0 |
1 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T35 |
0 |
1 |
0 |
0 |
T36 |
0 |
1 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
10161502 |
10161268 |
0 |
0 |
T2 |
3180294 |
3180294 |
0 |
0 |
T3 |
13175058 |
13132756 |
0 |
0 |
T4 |
15399046 |
15369302 |
0 |
0 |
T5 |
2664220 |
2662894 |
0 |
0 |
T6 |
10101858 |
10101390 |
0 |
0 |
T7 |
7200570 |
7197970 |
0 |
0 |
T8 |
3041402 |
3041376 |
0 |
0 |
T9 |
3329274 |
3329274 |
0 |
0 |
T10 |
9325810 |
9322014 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 17 | 16 | 94.12 |
CONT_ASSIGN | 65 | 0 | 0 | |
ALWAYS | 71 | 5 | 4 | 80.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 7 | 7 | 100.00 |
CONT_ASSIGN | 150 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
|
unreachable |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
|
unreachable |
75 |
1 |
1 |
76 |
0 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
|
unreachable |
124 |
|
unreachable |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
|
unreachable |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc
| Total | Covered | Percent |
Conditions | 7 | 6 | 85.71 |
Logical | 7 | 6 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Excluded | |
VC_COV_UNR |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Excluded | |
VC_COV_UNR |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Not Covered | |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Excluded | |
VC_COV_UNR |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
5 |
83.33 |
IF |
71 |
3 |
2 |
66.67 |
IF |
115 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Unreachable |
|
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Unreachable |
|
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_0_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34176360 |
33829907 |
0 |
0 |
T1 |
32568 |
32504 |
0 |
0 |
T2 |
97855 |
97798 |
0 |
0 |
T3 |
22013 |
21060 |
0 |
0 |
T4 |
47380 |
42790 |
0 |
0 |
T5 |
32145 |
32060 |
0 |
0 |
T6 |
81792 |
79987 |
0 |
0 |
T7 |
563 |
497 |
0 |
0 |
T8 |
97480 |
97403 |
0 |
0 |
T9 |
98500 |
98429 |
0 |
0 |
T10 |
14638 |
13067 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
390827 |
390818 |
0 |
0 |
T2 |
122319 |
122319 |
0 |
0 |
T3 |
506733 |
505106 |
0 |
0 |
T4 |
592271 |
591127 |
0 |
0 |
T5 |
102470 |
102419 |
0 |
0 |
T6 |
388533 |
388515 |
0 |
0 |
T7 |
276945 |
276845 |
0 |
0 |
T8 |
116977 |
116976 |
0 |
0 |
T9 |
128049 |
128049 |
0 |
0 |
T10 |
358685 |
358539 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 17 | 16 | 94.12 |
CONT_ASSIGN | 65 | 0 | 0 | |
ALWAYS | 71 | 5 | 4 | 80.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 7 | 7 | 100.00 |
CONT_ASSIGN | 150 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
|
unreachable |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
|
unreachable |
75 |
1 |
1 |
76 |
0 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
|
unreachable |
124 |
|
unreachable |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
|
unreachable |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc
| Total | Covered | Percent |
Conditions | 7 | 6 | 85.71 |
Logical | 7 | 6 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Unreachable | |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Excluded | |
VC_COV_UNR |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Excluded | |
VC_COV_UNR |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Not Covered | |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Excluded | |
VC_COV_UNR |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests | Exclude Annotation |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Excluded | |
VC_COV_UNR |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
6 |
5 |
83.33 |
IF |
71 |
3 |
2 |
66.67 |
IF |
115 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Unreachable |
|
0 |
0 |
1 |
Not Covered |
|
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Unreachable |
|
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn_val_1_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
0 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34176360 |
33829907 |
0 |
0 |
T1 |
32568 |
32504 |
0 |
0 |
T2 |
97855 |
97798 |
0 |
0 |
T3 |
22013 |
21060 |
0 |
0 |
T4 |
47380 |
42790 |
0 |
0 |
T5 |
32145 |
32060 |
0 |
0 |
T6 |
81792 |
79987 |
0 |
0 |
T7 |
563 |
497 |
0 |
0 |
T8 |
97480 |
97403 |
0 |
0 |
T9 |
98500 |
98429 |
0 |
0 |
T10 |
14638 |
13067 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
0 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
390827 |
390818 |
0 |
0 |
T2 |
122319 |
122319 |
0 |
0 |
T3 |
506733 |
505106 |
0 |
0 |
T4 |
592271 |
591127 |
0 |
0 |
T5 |
102470 |
102419 |
0 |
0 |
T6 |
388533 |
388515 |
0 |
0 |
T7 |
276945 |
276845 |
0 |
0 |
T8 |
116977 |
116976 |
0 |
0 |
T9 |
128049 |
128049 |
0 |
0 |
T10 |
358685 |
358539 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_filter_status_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
62669025 |
0 |
0 |
T1 |
390827 |
30549 |
0 |
0 |
T2 |
122319 |
100426 |
0 |
0 |
T3 |
506733 |
41051 |
0 |
0 |
T4 |
592271 |
16656 |
0 |
0 |
T5 |
102470 |
0 |
0 |
0 |
T6 |
388533 |
229278 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
96029 |
0 |
0 |
T9 |
128049 |
97113 |
0 |
0 |
T10 |
358685 |
0 |
0 |
0 |
T11 |
0 |
395319 |
0 |
0 |
T12 |
0 |
28982 |
0 |
0 |
T29 |
0 |
64327 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34176360 |
33829907 |
0 |
0 |
T1 |
32568 |
32504 |
0 |
0 |
T2 |
97855 |
97798 |
0 |
0 |
T3 |
22013 |
21060 |
0 |
0 |
T4 |
47380 |
42790 |
0 |
0 |
T5 |
32145 |
32060 |
0 |
0 |
T6 |
81792 |
79987 |
0 |
0 |
T7 |
563 |
497 |
0 |
0 |
T8 |
97480 |
97403 |
0 |
0 |
T9 |
98500 |
98429 |
0 |
0 |
T10 |
14638 |
13067 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
67223 |
0 |
0 |
T1 |
390827 |
77 |
0 |
0 |
T2 |
122319 |
239 |
0 |
0 |
T3 |
506733 |
50 |
0 |
0 |
T4 |
592271 |
41 |
0 |
0 |
T5 |
102470 |
0 |
0 |
0 |
T6 |
388533 |
140 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
227 |
0 |
0 |
T9 |
128049 |
225 |
0 |
0 |
T10 |
358685 |
0 |
0 |
0 |
T11 |
0 |
225 |
0 |
0 |
T12 |
0 |
84 |
0 |
0 |
T29 |
0 |
166 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
390827 |
390818 |
0 |
0 |
T2 |
122319 |
122319 |
0 |
0 |
T3 |
506733 |
505106 |
0 |
0 |
T4 |
592271 |
591127 |
0 |
0 |
T5 |
102470 |
102419 |
0 |
0 |
T6 |
388533 |
388515 |
0 |
0 |
T7 |
276945 |
276845 |
0 |
0 |
T8 |
116977 |
116976 |
0 |
0 |
T9 |
128049 |
128049 |
0 |
0 |
T10 |
358685 |
358539 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 21 | 21 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
|
unreachable |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc
| Total | Covered | Percent |
Conditions | 14 | 12 | 85.71 |
Logical | 14 | 12 | 85.71 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T3,T4,T28 |
1 | 0 | Unreachable | |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T30 |
1 | 1 | Covered | T3,T4,T28 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T30 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T3,T4,T28 |
1 | 1 | Covered | T3,T4,T30 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T3,T4,T28 |
0 |
0 |
1 |
Covered |
T3,T4,T30 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T3,T4,T28 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_state_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
80872 |
0 |
0 |
T3 |
506733 |
1790 |
0 |
0 |
T4 |
592271 |
1595 |
0 |
0 |
T5 |
102470 |
0 |
0 |
0 |
T6 |
388533 |
0 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
0 |
0 |
0 |
T9 |
128049 |
0 |
0 |
0 |
T10 |
358685 |
0 |
0 |
0 |
T11 |
513901 |
0 |
0 |
0 |
T12 |
356907 |
0 |
0 |
0 |
T28 |
0 |
228 |
0 |
0 |
T30 |
0 |
368 |
0 |
0 |
T31 |
0 |
500 |
0 |
0 |
T32 |
0 |
759 |
0 |
0 |
T33 |
0 |
1156 |
0 |
0 |
T34 |
0 |
1516 |
0 |
0 |
T35 |
0 |
1505 |
0 |
0 |
T36 |
0 |
1480 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34176360 |
33829907 |
0 |
0 |
T1 |
32568 |
32504 |
0 |
0 |
T2 |
97855 |
97798 |
0 |
0 |
T3 |
22013 |
21060 |
0 |
0 |
T4 |
47380 |
42790 |
0 |
0 |
T5 |
32145 |
32060 |
0 |
0 |
T6 |
81792 |
79987 |
0 |
0 |
T7 |
563 |
497 |
0 |
0 |
T8 |
97480 |
97403 |
0 |
0 |
T9 |
98500 |
98429 |
0 |
0 |
T10 |
14638 |
13067 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
87 |
0 |
0 |
T3 |
506733 |
1 |
0 |
0 |
T4 |
592271 |
1 |
0 |
0 |
T5 |
102470 |
0 |
0 |
0 |
T6 |
388533 |
0 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
0 |
0 |
0 |
T9 |
128049 |
0 |
0 |
0 |
T10 |
358685 |
0 |
0 |
0 |
T11 |
513901 |
0 |
0 |
0 |
T12 |
356907 |
0 |
0 |
0 |
T13 |
0 |
1 |
0 |
0 |
T30 |
0 |
1 |
0 |
0 |
T31 |
0 |
1 |
0 |
0 |
T32 |
0 |
1 |
0 |
0 |
T33 |
0 |
1 |
0 |
0 |
T34 |
0 |
1 |
0 |
0 |
T35 |
0 |
1 |
0 |
0 |
T36 |
0 |
1 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
390827 |
390818 |
0 |
0 |
T2 |
122319 |
122319 |
0 |
0 |
T3 |
506733 |
505106 |
0 |
0 |
T4 |
592271 |
591127 |
0 |
0 |
T5 |
102470 |
102419 |
0 |
0 |
T6 |
388533 |
388515 |
0 |
0 |
T7 |
276945 |
276845 |
0 |
0 |
T8 |
116977 |
116976 |
0 |
0 |
T9 |
128049 |
128049 |
0 |
0 |
T10 |
358685 |
358539 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_en_ctl_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
33930020 |
0 |
0 |
T1 |
390827 |
1183 |
0 |
0 |
T2 |
122319 |
4181 |
0 |
0 |
T3 |
506733 |
71571 |
0 |
0 |
T4 |
592271 |
210505 |
0 |
0 |
T5 |
102470 |
3499 |
0 |
0 |
T6 |
388533 |
400787 |
0 |
0 |
T7 |
276945 |
35209 |
0 |
0 |
T8 |
116977 |
3710 |
0 |
0 |
T9 |
128049 |
3697 |
0 |
0 |
T10 |
358685 |
204295 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34176360 |
33829907 |
0 |
0 |
T1 |
32568 |
32504 |
0 |
0 |
T2 |
97855 |
97798 |
0 |
0 |
T3 |
22013 |
21060 |
0 |
0 |
T4 |
47380 |
42790 |
0 |
0 |
T5 |
32145 |
32060 |
0 |
0 |
T6 |
81792 |
79987 |
0 |
0 |
T7 |
563 |
497 |
0 |
0 |
T8 |
97480 |
97403 |
0 |
0 |
T9 |
98500 |
98429 |
0 |
0 |
T10 |
14638 |
13067 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
37961 |
0 |
0 |
T1 |
390827 |
3 |
0 |
0 |
T2 |
122319 |
9 |
0 |
0 |
T3 |
506733 |
86 |
0 |
0 |
T4 |
592271 |
490 |
0 |
0 |
T5 |
102470 |
3 |
0 |
0 |
T6 |
388533 |
241 |
0 |
0 |
T7 |
276945 |
21 |
0 |
0 |
T8 |
116977 |
9 |
0 |
0 |
T9 |
128049 |
9 |
0 |
0 |
T10 |
358685 |
241 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
390827 |
390818 |
0 |
0 |
T2 |
122319 |
122319 |
0 |
0 |
T3 |
506733 |
505106 |
0 |
0 |
T4 |
592271 |
591127 |
0 |
0 |
T5 |
102470 |
102419 |
0 |
0 |
T6 |
388533 |
388515 |
0 |
0 |
T7 |
276945 |
276845 |
0 |
0 |
T8 |
116977 |
116976 |
0 |
0 |
T9 |
128049 |
128049 |
0 |
0 |
T10 |
358685 |
358539 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_pd_ctl_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
15355633 |
0 |
0 |
T1 |
390827 |
672 |
0 |
0 |
T2 |
122319 |
2508 |
0 |
0 |
T3 |
506733 |
23266 |
0 |
0 |
T4 |
592271 |
87724 |
0 |
0 |
T5 |
102470 |
1357 |
0 |
0 |
T6 |
388533 |
200206 |
0 |
0 |
T7 |
276945 |
16530 |
0 |
0 |
T8 |
116977 |
2401 |
0 |
0 |
T9 |
128049 |
2264 |
0 |
0 |
T10 |
358685 |
100439 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34176360 |
33829907 |
0 |
0 |
T1 |
32568 |
32504 |
0 |
0 |
T2 |
97855 |
97798 |
0 |
0 |
T3 |
22013 |
21060 |
0 |
0 |
T4 |
47380 |
42790 |
0 |
0 |
T5 |
32145 |
32060 |
0 |
0 |
T6 |
81792 |
79987 |
0 |
0 |
T7 |
563 |
497 |
0 |
0 |
T8 |
97480 |
97403 |
0 |
0 |
T9 |
98500 |
98429 |
0 |
0 |
T10 |
14638 |
13067 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
17627 |
0 |
0 |
T1 |
390827 |
2 |
0 |
0 |
T2 |
122319 |
6 |
0 |
0 |
T3 |
506733 |
31 |
0 |
0 |
T4 |
592271 |
220 |
0 |
0 |
T5 |
102470 |
2 |
0 |
0 |
T6 |
388533 |
121 |
0 |
0 |
T7 |
276945 |
10 |
0 |
0 |
T8 |
116977 |
6 |
0 |
0 |
T9 |
128049 |
6 |
0 |
0 |
T10 |
358685 |
120 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
390827 |
390818 |
0 |
0 |
T2 |
122319 |
122319 |
0 |
0 |
T3 |
506733 |
505106 |
0 |
0 |
T4 |
592271 |
591127 |
0 |
0 |
T5 |
102470 |
102419 |
0 |
0 |
T6 |
388533 |
388515 |
0 |
0 |
T7 |
276945 |
276845 |
0 |
0 |
T8 |
116977 |
116976 |
0 |
0 |
T9 |
128049 |
128049 |
0 |
0 |
T10 |
358685 |
358539 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_lp_sample_ctl_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
12215419 |
0 |
0 |
T1 |
390827 |
326 |
0 |
0 |
T2 |
122319 |
1168 |
0 |
0 |
T3 |
506733 |
6016 |
0 |
0 |
T4 |
592271 |
83053 |
0 |
0 |
T5 |
102470 |
1346 |
0 |
0 |
T6 |
388533 |
197713 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
1214 |
0 |
0 |
T9 |
128049 |
1130 |
0 |
0 |
T10 |
358685 |
100679 |
0 |
0 |
T11 |
0 |
5895 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34176360 |
33829907 |
0 |
0 |
T1 |
32568 |
32504 |
0 |
0 |
T2 |
97855 |
97798 |
0 |
0 |
T3 |
22013 |
21060 |
0 |
0 |
T4 |
47380 |
42790 |
0 |
0 |
T5 |
32145 |
32060 |
0 |
0 |
T6 |
81792 |
79987 |
0 |
0 |
T7 |
563 |
497 |
0 |
0 |
T8 |
97480 |
97403 |
0 |
0 |
T9 |
98500 |
98429 |
0 |
0 |
T10 |
14638 |
13067 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
13891 |
0 |
0 |
T1 |
390827 |
1 |
0 |
0 |
T2 |
122319 |
3 |
0 |
0 |
T3 |
506733 |
9 |
0 |
0 |
T4 |
592271 |
205 |
0 |
0 |
T5 |
102470 |
1 |
0 |
0 |
T6 |
388533 |
119 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
3 |
0 |
0 |
T9 |
128049 |
3 |
0 |
0 |
T10 |
358685 |
120 |
0 |
0 |
T11 |
0 |
3 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
390827 |
390818 |
0 |
0 |
T2 |
122319 |
122319 |
0 |
0 |
T3 |
506733 |
505106 |
0 |
0 |
T4 |
592271 |
591127 |
0 |
0 |
T5 |
102470 |
102419 |
0 |
0 |
T6 |
388533 |
388515 |
0 |
0 |
T7 |
276945 |
276845 |
0 |
0 |
T8 |
116977 |
116976 |
0 |
0 |
T9 |
128049 |
128049 |
0 |
0 |
T10 |
358685 |
358539 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_sample_ctl_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
12234357 |
0 |
0 |
T1 |
390827 |
338 |
0 |
0 |
T2 |
122319 |
1211 |
0 |
0 |
T3 |
506733 |
6073 |
0 |
0 |
T4 |
592271 |
85327 |
0 |
0 |
T5 |
102470 |
1357 |
0 |
0 |
T6 |
388533 |
198564 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
1220 |
0 |
0 |
T9 |
128049 |
1153 |
0 |
0 |
T10 |
358685 |
100919 |
0 |
0 |
T11 |
0 |
5901 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34176360 |
33829907 |
0 |
0 |
T1 |
32568 |
32504 |
0 |
0 |
T2 |
97855 |
97798 |
0 |
0 |
T3 |
22013 |
21060 |
0 |
0 |
T4 |
47380 |
42790 |
0 |
0 |
T5 |
32145 |
32060 |
0 |
0 |
T6 |
81792 |
79987 |
0 |
0 |
T7 |
563 |
497 |
0 |
0 |
T8 |
97480 |
97403 |
0 |
0 |
T9 |
98500 |
98429 |
0 |
0 |
T10 |
14638 |
13067 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
13840 |
0 |
0 |
T1 |
390827 |
1 |
0 |
0 |
T2 |
122319 |
3 |
0 |
0 |
T3 |
506733 |
9 |
0 |
0 |
T4 |
592271 |
205 |
0 |
0 |
T5 |
102470 |
1 |
0 |
0 |
T6 |
388533 |
119 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
3 |
0 |
0 |
T9 |
128049 |
3 |
0 |
0 |
T10 |
358685 |
120 |
0 |
0 |
T11 |
0 |
3 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
390827 |
390818 |
0 |
0 |
T2 |
122319 |
122319 |
0 |
0 |
T3 |
506733 |
505106 |
0 |
0 |
T4 |
592271 |
591127 |
0 |
0 |
T5 |
102470 |
102419 |
0 |
0 |
T6 |
388533 |
388515 |
0 |
0 |
T7 |
276945 |
276845 |
0 |
0 |
T8 |
116977 |
116976 |
0 |
0 |
T9 |
128049 |
128049 |
0 |
0 |
T10 |
358685 |
358539 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1855327 |
0 |
0 |
T1 |
390827 |
349 |
0 |
0 |
T2 |
122319 |
1333 |
0 |
0 |
T3 |
506733 |
6293 |
0 |
0 |
T4 |
592271 |
3481 |
0 |
0 |
T5 |
102470 |
1489 |
0 |
0 |
T6 |
388533 |
5189 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
1316 |
0 |
0 |
T9 |
128049 |
1259 |
0 |
0 |
T10 |
358685 |
733 |
0 |
0 |
T11 |
0 |
5997 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34176360 |
33829907 |
0 |
0 |
T1 |
32568 |
32504 |
0 |
0 |
T2 |
97855 |
97798 |
0 |
0 |
T3 |
22013 |
21060 |
0 |
0 |
T4 |
47380 |
42790 |
0 |
0 |
T5 |
32145 |
32060 |
0 |
0 |
T6 |
81792 |
79987 |
0 |
0 |
T7 |
563 |
497 |
0 |
0 |
T8 |
97480 |
97403 |
0 |
0 |
T9 |
98500 |
98429 |
0 |
0 |
T10 |
14638 |
13067 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2060 |
0 |
0 |
T1 |
390827 |
1 |
0 |
0 |
T2 |
122319 |
3 |
0 |
0 |
T3 |
506733 |
8 |
0 |
0 |
T4 |
592271 |
8 |
0 |
0 |
T5 |
102470 |
1 |
0 |
0 |
T6 |
388533 |
3 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
3 |
0 |
0 |
T9 |
128049 |
3 |
0 |
0 |
T10 |
358685 |
1 |
0 |
0 |
T11 |
0 |
3 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
390827 |
390818 |
0 |
0 |
T2 |
122319 |
122319 |
0 |
0 |
T3 |
506733 |
505106 |
0 |
0 |
T4 |
592271 |
591127 |
0 |
0 |
T5 |
102470 |
102419 |
0 |
0 |
T6 |
388533 |
388515 |
0 |
0 |
T7 |
276945 |
276845 |
0 |
0 |
T8 |
116977 |
116976 |
0 |
0 |
T9 |
128049 |
128049 |
0 |
0 |
T10 |
358685 |
358539 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1739561 |
0 |
0 |
T1 |
390827 |
345 |
0 |
0 |
T2 |
122319 |
1309 |
0 |
0 |
T3 |
506733 |
6232 |
0 |
0 |
T4 |
592271 |
2077 |
0 |
0 |
T5 |
102470 |
1477 |
0 |
0 |
T6 |
388533 |
3761 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
1310 |
0 |
0 |
T9 |
128049 |
1230 |
0 |
0 |
T10 |
358685 |
0 |
0 |
0 |
T11 |
0 |
5991 |
0 |
0 |
T12 |
0 |
317 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34176360 |
33829907 |
0 |
0 |
T1 |
32568 |
32504 |
0 |
0 |
T2 |
97855 |
97798 |
0 |
0 |
T3 |
22013 |
21060 |
0 |
0 |
T4 |
47380 |
42790 |
0 |
0 |
T5 |
32145 |
32060 |
0 |
0 |
T6 |
81792 |
79987 |
0 |
0 |
T7 |
563 |
497 |
0 |
0 |
T8 |
97480 |
97403 |
0 |
0 |
T9 |
98500 |
98429 |
0 |
0 |
T10 |
14638 |
13067 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1929 |
0 |
0 |
T1 |
390827 |
1 |
0 |
0 |
T2 |
122319 |
3 |
0 |
0 |
T3 |
506733 |
8 |
0 |
0 |
T4 |
592271 |
5 |
0 |
0 |
T5 |
102470 |
1 |
0 |
0 |
T6 |
388533 |
2 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
3 |
0 |
0 |
T9 |
128049 |
3 |
0 |
0 |
T10 |
358685 |
0 |
0 |
0 |
T11 |
0 |
3 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
390827 |
390818 |
0 |
0 |
T2 |
122319 |
122319 |
0 |
0 |
T3 |
506733 |
505106 |
0 |
0 |
T4 |
592271 |
591127 |
0 |
0 |
T5 |
102470 |
102419 |
0 |
0 |
T6 |
388533 |
388515 |
0 |
0 |
T7 |
276945 |
276845 |
0 |
0 |
T8 |
116977 |
116976 |
0 |
0 |
T9 |
128049 |
128049 |
0 |
0 |
T10 |
358685 |
358539 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1682384 |
0 |
0 |
T1 |
390827 |
340 |
0 |
0 |
T2 |
122319 |
1272 |
0 |
0 |
T3 |
506733 |
6179 |
0 |
0 |
T4 |
592271 |
2035 |
0 |
0 |
T5 |
102470 |
1473 |
0 |
0 |
T6 |
388533 |
3748 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
1304 |
0 |
0 |
T9 |
128049 |
1198 |
0 |
0 |
T10 |
358685 |
0 |
0 |
0 |
T11 |
0 |
5985 |
0 |
0 |
T12 |
0 |
311 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34176360 |
33829907 |
0 |
0 |
T1 |
32568 |
32504 |
0 |
0 |
T2 |
97855 |
97798 |
0 |
0 |
T3 |
22013 |
21060 |
0 |
0 |
T4 |
47380 |
42790 |
0 |
0 |
T5 |
32145 |
32060 |
0 |
0 |
T6 |
81792 |
79987 |
0 |
0 |
T7 |
563 |
497 |
0 |
0 |
T8 |
97480 |
97403 |
0 |
0 |
T9 |
98500 |
98429 |
0 |
0 |
T10 |
14638 |
13067 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1885 |
0 |
0 |
T1 |
390827 |
1 |
0 |
0 |
T2 |
122319 |
3 |
0 |
0 |
T3 |
506733 |
8 |
0 |
0 |
T4 |
592271 |
5 |
0 |
0 |
T5 |
102470 |
1 |
0 |
0 |
T6 |
388533 |
2 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
3 |
0 |
0 |
T9 |
128049 |
3 |
0 |
0 |
T10 |
358685 |
0 |
0 |
0 |
T11 |
0 |
3 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
390827 |
390818 |
0 |
0 |
T2 |
122319 |
122319 |
0 |
0 |
T3 |
506733 |
505106 |
0 |
0 |
T4 |
592271 |
591127 |
0 |
0 |
T5 |
102470 |
102419 |
0 |
0 |
T6 |
388533 |
388515 |
0 |
0 |
T7 |
276945 |
276845 |
0 |
0 |
T8 |
116977 |
116976 |
0 |
0 |
T9 |
128049 |
128049 |
0 |
0 |
T10 |
358685 |
358539 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1672072 |
0 |
0 |
T1 |
390827 |
330 |
0 |
0 |
T2 |
122319 |
1241 |
0 |
0 |
T3 |
506733 |
6130 |
0 |
0 |
T4 |
592271 |
1982 |
0 |
0 |
T5 |
102470 |
1464 |
0 |
0 |
T6 |
388533 |
3733 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
1298 |
0 |
0 |
T9 |
128049 |
1165 |
0 |
0 |
T10 |
358685 |
0 |
0 |
0 |
T11 |
0 |
5979 |
0 |
0 |
T12 |
0 |
309 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34176360 |
33829907 |
0 |
0 |
T1 |
32568 |
32504 |
0 |
0 |
T2 |
97855 |
97798 |
0 |
0 |
T3 |
22013 |
21060 |
0 |
0 |
T4 |
47380 |
42790 |
0 |
0 |
T5 |
32145 |
32060 |
0 |
0 |
T6 |
81792 |
79987 |
0 |
0 |
T7 |
563 |
497 |
0 |
0 |
T8 |
97480 |
97403 |
0 |
0 |
T9 |
98500 |
98429 |
0 |
0 |
T10 |
14638 |
13067 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1885 |
0 |
0 |
T1 |
390827 |
1 |
0 |
0 |
T2 |
122319 |
3 |
0 |
0 |
T3 |
506733 |
8 |
0 |
0 |
T4 |
592271 |
5 |
0 |
0 |
T5 |
102470 |
1 |
0 |
0 |
T6 |
388533 |
2 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
3 |
0 |
0 |
T9 |
128049 |
3 |
0 |
0 |
T10 |
358685 |
0 |
0 |
0 |
T11 |
0 |
3 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
390827 |
390818 |
0 |
0 |
T2 |
122319 |
122319 |
0 |
0 |
T3 |
506733 |
505106 |
0 |
0 |
T4 |
592271 |
591127 |
0 |
0 |
T5 |
102470 |
102419 |
0 |
0 |
T6 |
388533 |
388515 |
0 |
0 |
T7 |
276945 |
276845 |
0 |
0 |
T8 |
116977 |
116976 |
0 |
0 |
T9 |
128049 |
128049 |
0 |
0 |
T10 |
358685 |
358539 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1726983 |
0 |
0 |
T1 |
390827 |
320 |
0 |
0 |
T2 |
122319 |
1202 |
0 |
0 |
T3 |
506733 |
6086 |
0 |
0 |
T4 |
592271 |
1930 |
0 |
0 |
T5 |
102470 |
1452 |
0 |
0 |
T6 |
388533 |
3715 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
1292 |
0 |
0 |
T9 |
128049 |
1140 |
0 |
0 |
T10 |
358685 |
0 |
0 |
0 |
T11 |
0 |
5973 |
0 |
0 |
T12 |
0 |
302 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34176360 |
33829907 |
0 |
0 |
T1 |
32568 |
32504 |
0 |
0 |
T2 |
97855 |
97798 |
0 |
0 |
T3 |
22013 |
21060 |
0 |
0 |
T4 |
47380 |
42790 |
0 |
0 |
T5 |
32145 |
32060 |
0 |
0 |
T6 |
81792 |
79987 |
0 |
0 |
T7 |
563 |
497 |
0 |
0 |
T8 |
97480 |
97403 |
0 |
0 |
T9 |
98500 |
98429 |
0 |
0 |
T10 |
14638 |
13067 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1914 |
0 |
0 |
T1 |
390827 |
1 |
0 |
0 |
T2 |
122319 |
3 |
0 |
0 |
T3 |
506733 |
8 |
0 |
0 |
T4 |
592271 |
5 |
0 |
0 |
T5 |
102470 |
1 |
0 |
0 |
T6 |
388533 |
2 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
3 |
0 |
0 |
T9 |
128049 |
3 |
0 |
0 |
T10 |
358685 |
0 |
0 |
0 |
T11 |
0 |
3 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
390827 |
390818 |
0 |
0 |
T2 |
122319 |
122319 |
0 |
0 |
T3 |
506733 |
505106 |
0 |
0 |
T4 |
592271 |
591127 |
0 |
0 |
T5 |
102470 |
102419 |
0 |
0 |
T6 |
388533 |
388515 |
0 |
0 |
T7 |
276945 |
276845 |
0 |
0 |
T8 |
116977 |
116976 |
0 |
0 |
T9 |
128049 |
128049 |
0 |
0 |
T10 |
358685 |
358539 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1700892 |
0 |
0 |
T1 |
390827 |
313 |
0 |
0 |
T2 |
122319 |
1174 |
0 |
0 |
T3 |
506733 |
6041 |
0 |
0 |
T4 |
592271 |
1870 |
0 |
0 |
T5 |
102470 |
1440 |
0 |
0 |
T6 |
388533 |
3702 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
1286 |
0 |
0 |
T9 |
128049 |
1112 |
0 |
0 |
T10 |
358685 |
0 |
0 |
0 |
T11 |
0 |
5967 |
0 |
0 |
T12 |
0 |
300 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34176360 |
33829907 |
0 |
0 |
T1 |
32568 |
32504 |
0 |
0 |
T2 |
97855 |
97798 |
0 |
0 |
T3 |
22013 |
21060 |
0 |
0 |
T4 |
47380 |
42790 |
0 |
0 |
T5 |
32145 |
32060 |
0 |
0 |
T6 |
81792 |
79987 |
0 |
0 |
T7 |
563 |
497 |
0 |
0 |
T8 |
97480 |
97403 |
0 |
0 |
T9 |
98500 |
98429 |
0 |
0 |
T10 |
14638 |
13067 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1911 |
0 |
0 |
T1 |
390827 |
1 |
0 |
0 |
T2 |
122319 |
3 |
0 |
0 |
T3 |
506733 |
8 |
0 |
0 |
T4 |
592271 |
5 |
0 |
0 |
T5 |
102470 |
1 |
0 |
0 |
T6 |
388533 |
2 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
3 |
0 |
0 |
T9 |
128049 |
3 |
0 |
0 |
T10 |
358685 |
0 |
0 |
0 |
T11 |
0 |
3 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
390827 |
390818 |
0 |
0 |
T2 |
122319 |
122319 |
0 |
0 |
T3 |
506733 |
505106 |
0 |
0 |
T4 |
592271 |
591127 |
0 |
0 |
T5 |
102470 |
102419 |
0 |
0 |
T6 |
388533 |
388515 |
0 |
0 |
T7 |
276945 |
276845 |
0 |
0 |
T8 |
116977 |
116976 |
0 |
0 |
T9 |
128049 |
128049 |
0 |
0 |
T10 |
358685 |
358539 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1726458 |
0 |
0 |
T1 |
390827 |
305 |
0 |
0 |
T2 |
122319 |
1149 |
0 |
0 |
T3 |
506733 |
5993 |
0 |
0 |
T4 |
592271 |
1817 |
0 |
0 |
T5 |
102470 |
1437 |
0 |
0 |
T6 |
388533 |
3679 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
1280 |
0 |
0 |
T9 |
128049 |
1075 |
0 |
0 |
T10 |
358685 |
0 |
0 |
0 |
T11 |
0 |
5961 |
0 |
0 |
T12 |
0 |
291 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34176360 |
33829907 |
0 |
0 |
T1 |
32568 |
32504 |
0 |
0 |
T2 |
97855 |
97798 |
0 |
0 |
T3 |
22013 |
21060 |
0 |
0 |
T4 |
47380 |
42790 |
0 |
0 |
T5 |
32145 |
32060 |
0 |
0 |
T6 |
81792 |
79987 |
0 |
0 |
T7 |
563 |
497 |
0 |
0 |
T8 |
97480 |
97403 |
0 |
0 |
T9 |
98500 |
98429 |
0 |
0 |
T10 |
14638 |
13067 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1953 |
0 |
0 |
T1 |
390827 |
1 |
0 |
0 |
T2 |
122319 |
3 |
0 |
0 |
T3 |
506733 |
8 |
0 |
0 |
T4 |
592271 |
5 |
0 |
0 |
T5 |
102470 |
1 |
0 |
0 |
T6 |
388533 |
2 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
3 |
0 |
0 |
T9 |
128049 |
3 |
0 |
0 |
T10 |
358685 |
0 |
0 |
0 |
T11 |
0 |
3 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
390827 |
390818 |
0 |
0 |
T2 |
122319 |
122319 |
0 |
0 |
T3 |
506733 |
505106 |
0 |
0 |
T4 |
592271 |
591127 |
0 |
0 |
T5 |
102470 |
102419 |
0 |
0 |
T6 |
388533 |
388515 |
0 |
0 |
T7 |
276945 |
276845 |
0 |
0 |
T8 |
116977 |
116976 |
0 |
0 |
T9 |
128049 |
128049 |
0 |
0 |
T10 |
358685 |
358539 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1723710 |
0 |
0 |
T1 |
390827 |
293 |
0 |
0 |
T2 |
122319 |
1110 |
0 |
0 |
T3 |
506733 |
5946 |
0 |
0 |
T4 |
592271 |
1768 |
0 |
0 |
T5 |
102470 |
1431 |
0 |
0 |
T6 |
388533 |
3660 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
1274 |
0 |
0 |
T9 |
128049 |
1041 |
0 |
0 |
T10 |
358685 |
0 |
0 |
0 |
T11 |
0 |
5955 |
0 |
0 |
T12 |
0 |
287 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34176360 |
33829907 |
0 |
0 |
T1 |
32568 |
32504 |
0 |
0 |
T2 |
97855 |
97798 |
0 |
0 |
T3 |
22013 |
21060 |
0 |
0 |
T4 |
47380 |
42790 |
0 |
0 |
T5 |
32145 |
32060 |
0 |
0 |
T6 |
81792 |
79987 |
0 |
0 |
T7 |
563 |
497 |
0 |
0 |
T8 |
97480 |
97403 |
0 |
0 |
T9 |
98500 |
98429 |
0 |
0 |
T10 |
14638 |
13067 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1953 |
0 |
0 |
T1 |
390827 |
1 |
0 |
0 |
T2 |
122319 |
3 |
0 |
0 |
T3 |
506733 |
8 |
0 |
0 |
T4 |
592271 |
5 |
0 |
0 |
T5 |
102470 |
1 |
0 |
0 |
T6 |
388533 |
2 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
3 |
0 |
0 |
T9 |
128049 |
3 |
0 |
0 |
T10 |
358685 |
0 |
0 |
0 |
T11 |
0 |
3 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
390827 |
390818 |
0 |
0 |
T2 |
122319 |
122319 |
0 |
0 |
T3 |
506733 |
505106 |
0 |
0 |
T4 |
592271 |
591127 |
0 |
0 |
T5 |
102470 |
102419 |
0 |
0 |
T6 |
388533 |
388515 |
0 |
0 |
T7 |
276945 |
276845 |
0 |
0 |
T8 |
116977 |
116976 |
0 |
0 |
T9 |
128049 |
128049 |
0 |
0 |
T10 |
358685 |
358539 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1762033 |
0 |
0 |
T1 |
390827 |
283 |
0 |
0 |
T2 |
122319 |
1080 |
0 |
0 |
T3 |
506733 |
5876 |
0 |
0 |
T4 |
592271 |
3034 |
0 |
0 |
T5 |
102470 |
1421 |
0 |
0 |
T6 |
388533 |
5042 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
1268 |
0 |
0 |
T9 |
128049 |
1008 |
0 |
0 |
T10 |
358685 |
731 |
0 |
0 |
T11 |
0 |
5949 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34176360 |
33829907 |
0 |
0 |
T1 |
32568 |
32504 |
0 |
0 |
T2 |
97855 |
97798 |
0 |
0 |
T3 |
22013 |
21060 |
0 |
0 |
T4 |
47380 |
42790 |
0 |
0 |
T5 |
32145 |
32060 |
0 |
0 |
T6 |
81792 |
79987 |
0 |
0 |
T7 |
563 |
497 |
0 |
0 |
T8 |
97480 |
97403 |
0 |
0 |
T9 |
98500 |
98429 |
0 |
0 |
T10 |
14638 |
13067 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2013 |
0 |
0 |
T1 |
390827 |
1 |
0 |
0 |
T2 |
122319 |
3 |
0 |
0 |
T3 |
506733 |
8 |
0 |
0 |
T4 |
592271 |
8 |
0 |
0 |
T5 |
102470 |
1 |
0 |
0 |
T6 |
388533 |
3 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
3 |
0 |
0 |
T9 |
128049 |
3 |
0 |
0 |
T10 |
358685 |
1 |
0 |
0 |
T11 |
0 |
3 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
390827 |
390818 |
0 |
0 |
T2 |
122319 |
122319 |
0 |
0 |
T3 |
506733 |
505106 |
0 |
0 |
T4 |
592271 |
591127 |
0 |
0 |
T5 |
102470 |
102419 |
0 |
0 |
T6 |
388533 |
388515 |
0 |
0 |
T7 |
276945 |
276845 |
0 |
0 |
T8 |
116977 |
116976 |
0 |
0 |
T9 |
128049 |
128049 |
0 |
0 |
T10 |
358685 |
358539 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1682259 |
0 |
0 |
T1 |
390827 |
275 |
0 |
0 |
T2 |
122319 |
1051 |
0 |
0 |
T3 |
506733 |
5812 |
0 |
0 |
T4 |
592271 |
1803 |
0 |
0 |
T5 |
102470 |
1417 |
0 |
0 |
T6 |
388533 |
3628 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
1262 |
0 |
0 |
T9 |
128049 |
992 |
0 |
0 |
T10 |
358685 |
0 |
0 |
0 |
T11 |
0 |
5943 |
0 |
0 |
T12 |
0 |
267 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34176360 |
33829907 |
0 |
0 |
T1 |
32568 |
32504 |
0 |
0 |
T2 |
97855 |
97798 |
0 |
0 |
T3 |
22013 |
21060 |
0 |
0 |
T4 |
47380 |
42790 |
0 |
0 |
T5 |
32145 |
32060 |
0 |
0 |
T6 |
81792 |
79987 |
0 |
0 |
T7 |
563 |
497 |
0 |
0 |
T8 |
97480 |
97403 |
0 |
0 |
T9 |
98500 |
98429 |
0 |
0 |
T10 |
14638 |
13067 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1918 |
0 |
0 |
T1 |
390827 |
1 |
0 |
0 |
T2 |
122319 |
3 |
0 |
0 |
T3 |
506733 |
8 |
0 |
0 |
T4 |
592271 |
5 |
0 |
0 |
T5 |
102470 |
1 |
0 |
0 |
T6 |
388533 |
2 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
3 |
0 |
0 |
T9 |
128049 |
3 |
0 |
0 |
T10 |
358685 |
0 |
0 |
0 |
T11 |
0 |
3 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
390827 |
390818 |
0 |
0 |
T2 |
122319 |
122319 |
0 |
0 |
T3 |
506733 |
505106 |
0 |
0 |
T4 |
592271 |
591127 |
0 |
0 |
T5 |
102470 |
102419 |
0 |
0 |
T6 |
388533 |
388515 |
0 |
0 |
T7 |
276945 |
276845 |
0 |
0 |
T8 |
116977 |
116976 |
0 |
0 |
T9 |
128049 |
128049 |
0 |
0 |
T10 |
358685 |
358539 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1698467 |
0 |
0 |
T1 |
390827 |
265 |
0 |
0 |
T2 |
122319 |
1144 |
0 |
0 |
T3 |
506733 |
5740 |
0 |
0 |
T4 |
592271 |
2014 |
0 |
0 |
T5 |
102470 |
1406 |
0 |
0 |
T6 |
388533 |
3618 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
1256 |
0 |
0 |
T9 |
128049 |
964 |
0 |
0 |
T10 |
358685 |
0 |
0 |
0 |
T11 |
0 |
5937 |
0 |
0 |
T12 |
0 |
257 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34176360 |
33829907 |
0 |
0 |
T1 |
32568 |
32504 |
0 |
0 |
T2 |
97855 |
97798 |
0 |
0 |
T3 |
22013 |
21060 |
0 |
0 |
T4 |
47380 |
42790 |
0 |
0 |
T5 |
32145 |
32060 |
0 |
0 |
T6 |
81792 |
79987 |
0 |
0 |
T7 |
563 |
497 |
0 |
0 |
T8 |
97480 |
97403 |
0 |
0 |
T9 |
98500 |
98429 |
0 |
0 |
T10 |
14638 |
13067 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1942 |
0 |
0 |
T1 |
390827 |
1 |
0 |
0 |
T2 |
122319 |
3 |
0 |
0 |
T3 |
506733 |
8 |
0 |
0 |
T4 |
592271 |
5 |
0 |
0 |
T5 |
102470 |
1 |
0 |
0 |
T6 |
388533 |
2 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
3 |
0 |
0 |
T9 |
128049 |
3 |
0 |
0 |
T10 |
358685 |
0 |
0 |
0 |
T11 |
0 |
3 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
390827 |
390818 |
0 |
0 |
T2 |
122319 |
122319 |
0 |
0 |
T3 |
506733 |
505106 |
0 |
0 |
T4 |
592271 |
591127 |
0 |
0 |
T5 |
102470 |
102419 |
0 |
0 |
T6 |
388533 |
388515 |
0 |
0 |
T7 |
276945 |
276845 |
0 |
0 |
T8 |
116977 |
116976 |
0 |
0 |
T9 |
128049 |
128049 |
0 |
0 |
T10 |
358685 |
358539 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1666813 |
0 |
0 |
T1 |
390827 |
253 |
0 |
0 |
T2 |
122319 |
1234 |
0 |
0 |
T3 |
506733 |
5695 |
0 |
0 |
T4 |
592271 |
1968 |
0 |
0 |
T5 |
102470 |
1396 |
0 |
0 |
T6 |
388533 |
3609 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
1250 |
0 |
0 |
T9 |
128049 |
1057 |
0 |
0 |
T10 |
358685 |
0 |
0 |
0 |
T11 |
0 |
5931 |
0 |
0 |
T12 |
0 |
246 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34176360 |
33829907 |
0 |
0 |
T1 |
32568 |
32504 |
0 |
0 |
T2 |
97855 |
97798 |
0 |
0 |
T3 |
22013 |
21060 |
0 |
0 |
T4 |
47380 |
42790 |
0 |
0 |
T5 |
32145 |
32060 |
0 |
0 |
T6 |
81792 |
79987 |
0 |
0 |
T7 |
563 |
497 |
0 |
0 |
T8 |
97480 |
97403 |
0 |
0 |
T9 |
98500 |
98429 |
0 |
0 |
T10 |
14638 |
13067 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1927 |
0 |
0 |
T1 |
390827 |
1 |
0 |
0 |
T2 |
122319 |
3 |
0 |
0 |
T3 |
506733 |
8 |
0 |
0 |
T4 |
592271 |
5 |
0 |
0 |
T5 |
102470 |
1 |
0 |
0 |
T6 |
388533 |
2 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
3 |
0 |
0 |
T9 |
128049 |
3 |
0 |
0 |
T10 |
358685 |
0 |
0 |
0 |
T11 |
0 |
3 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
390827 |
390818 |
0 |
0 |
T2 |
122319 |
122319 |
0 |
0 |
T3 |
506733 |
505106 |
0 |
0 |
T4 |
592271 |
591127 |
0 |
0 |
T5 |
102470 |
102419 |
0 |
0 |
T6 |
388533 |
388515 |
0 |
0 |
T7 |
276945 |
276845 |
0 |
0 |
T8 |
116977 |
116976 |
0 |
0 |
T9 |
128049 |
128049 |
0 |
0 |
T10 |
358685 |
358539 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1662306 |
0 |
0 |
T1 |
390827 |
248 |
0 |
0 |
T2 |
122319 |
1331 |
0 |
0 |
T3 |
506733 |
5651 |
0 |
0 |
T4 |
592271 |
2158 |
0 |
0 |
T5 |
102470 |
1391 |
0 |
0 |
T6 |
388533 |
3600 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
1244 |
0 |
0 |
T9 |
128049 |
1278 |
0 |
0 |
T10 |
358685 |
0 |
0 |
0 |
T11 |
0 |
5925 |
0 |
0 |
T12 |
0 |
236 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34176360 |
33829907 |
0 |
0 |
T1 |
32568 |
32504 |
0 |
0 |
T2 |
97855 |
97798 |
0 |
0 |
T3 |
22013 |
21060 |
0 |
0 |
T4 |
47380 |
42790 |
0 |
0 |
T5 |
32145 |
32060 |
0 |
0 |
T6 |
81792 |
79987 |
0 |
0 |
T7 |
563 |
497 |
0 |
0 |
T8 |
97480 |
97403 |
0 |
0 |
T9 |
98500 |
98429 |
0 |
0 |
T10 |
14638 |
13067 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1915 |
0 |
0 |
T1 |
390827 |
1 |
0 |
0 |
T2 |
122319 |
3 |
0 |
0 |
T3 |
506733 |
8 |
0 |
0 |
T4 |
592271 |
5 |
0 |
0 |
T5 |
102470 |
1 |
0 |
0 |
T6 |
388533 |
2 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
3 |
0 |
0 |
T9 |
128049 |
3 |
0 |
0 |
T10 |
358685 |
0 |
0 |
0 |
T11 |
0 |
3 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
390827 |
390818 |
0 |
0 |
T2 |
122319 |
122319 |
0 |
0 |
T3 |
506733 |
505106 |
0 |
0 |
T4 |
592271 |
591127 |
0 |
0 |
T5 |
102470 |
102419 |
0 |
0 |
T6 |
388533 |
388515 |
0 |
0 |
T7 |
276945 |
276845 |
0 |
0 |
T8 |
116977 |
116976 |
0 |
0 |
T9 |
128049 |
128049 |
0 |
0 |
T10 |
358685 |
358539 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1652540 |
0 |
0 |
T1 |
390827 |
246 |
0 |
0 |
T2 |
122319 |
1294 |
0 |
0 |
T3 |
506733 |
5605 |
0 |
0 |
T4 |
592271 |
2106 |
0 |
0 |
T5 |
102470 |
1387 |
0 |
0 |
T6 |
388533 |
3581 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
1238 |
0 |
0 |
T9 |
128049 |
1252 |
0 |
0 |
T10 |
358685 |
0 |
0 |
0 |
T11 |
0 |
5919 |
0 |
0 |
T12 |
0 |
229 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34176360 |
33829907 |
0 |
0 |
T1 |
32568 |
32504 |
0 |
0 |
T2 |
97855 |
97798 |
0 |
0 |
T3 |
22013 |
21060 |
0 |
0 |
T4 |
47380 |
42790 |
0 |
0 |
T5 |
32145 |
32060 |
0 |
0 |
T6 |
81792 |
79987 |
0 |
0 |
T7 |
563 |
497 |
0 |
0 |
T8 |
97480 |
97403 |
0 |
0 |
T9 |
98500 |
98429 |
0 |
0 |
T10 |
14638 |
13067 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1905 |
0 |
0 |
T1 |
390827 |
1 |
0 |
0 |
T2 |
122319 |
3 |
0 |
0 |
T3 |
506733 |
8 |
0 |
0 |
T4 |
592271 |
5 |
0 |
0 |
T5 |
102470 |
1 |
0 |
0 |
T6 |
388533 |
2 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
3 |
0 |
0 |
T9 |
128049 |
3 |
0 |
0 |
T10 |
358685 |
0 |
0 |
0 |
T11 |
0 |
3 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
390827 |
390818 |
0 |
0 |
T2 |
122319 |
122319 |
0 |
0 |
T3 |
506733 |
505106 |
0 |
0 |
T4 |
592271 |
591127 |
0 |
0 |
T5 |
102470 |
102419 |
0 |
0 |
T6 |
388533 |
388515 |
0 |
0 |
T7 |
276945 |
276845 |
0 |
0 |
T8 |
116977 |
116976 |
0 |
0 |
T9 |
128049 |
128049 |
0 |
0 |
T10 |
358685 |
358539 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1671708 |
0 |
0 |
T1 |
390827 |
358 |
0 |
0 |
T2 |
122319 |
1260 |
0 |
0 |
T3 |
506733 |
5537 |
0 |
0 |
T4 |
592271 |
2068 |
0 |
0 |
T5 |
102470 |
1376 |
0 |
0 |
T6 |
388533 |
3566 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
1232 |
0 |
0 |
T9 |
128049 |
1219 |
0 |
0 |
T10 |
358685 |
0 |
0 |
0 |
T11 |
0 |
5913 |
0 |
0 |
T12 |
0 |
223 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34176360 |
33829907 |
0 |
0 |
T1 |
32568 |
32504 |
0 |
0 |
T2 |
97855 |
97798 |
0 |
0 |
T3 |
22013 |
21060 |
0 |
0 |
T4 |
47380 |
42790 |
0 |
0 |
T5 |
32145 |
32060 |
0 |
0 |
T6 |
81792 |
79987 |
0 |
0 |
T7 |
563 |
497 |
0 |
0 |
T8 |
97480 |
97403 |
0 |
0 |
T9 |
98500 |
98429 |
0 |
0 |
T10 |
14638 |
13067 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1912 |
0 |
0 |
T1 |
390827 |
1 |
0 |
0 |
T2 |
122319 |
3 |
0 |
0 |
T3 |
506733 |
8 |
0 |
0 |
T4 |
592271 |
5 |
0 |
0 |
T5 |
102470 |
1 |
0 |
0 |
T6 |
388533 |
2 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
3 |
0 |
0 |
T9 |
128049 |
3 |
0 |
0 |
T10 |
358685 |
0 |
0 |
0 |
T11 |
0 |
3 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
390827 |
390818 |
0 |
0 |
T2 |
122319 |
122319 |
0 |
0 |
T3 |
506733 |
505106 |
0 |
0 |
T4 |
592271 |
591127 |
0 |
0 |
T5 |
102470 |
102419 |
0 |
0 |
T6 |
388533 |
388515 |
0 |
0 |
T7 |
276945 |
276845 |
0 |
0 |
T8 |
116977 |
116976 |
0 |
0 |
T9 |
128049 |
128049 |
0 |
0 |
T10 |
358685 |
358539 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T3 |
0 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1672949 |
0 |
0 |
T1 |
390827 |
346 |
0 |
0 |
T2 |
122319 |
1231 |
0 |
0 |
T3 |
506733 |
5479 |
0 |
0 |
T4 |
592271 |
2011 |
0 |
0 |
T5 |
102470 |
1366 |
0 |
0 |
T6 |
388533 |
3554 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
1226 |
0 |
0 |
T9 |
128049 |
1184 |
0 |
0 |
T10 |
358685 |
0 |
0 |
0 |
T11 |
0 |
5907 |
0 |
0 |
T12 |
0 |
322 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34176360 |
33829907 |
0 |
0 |
T1 |
32568 |
32504 |
0 |
0 |
T2 |
97855 |
97798 |
0 |
0 |
T3 |
22013 |
21060 |
0 |
0 |
T4 |
47380 |
42790 |
0 |
0 |
T5 |
32145 |
32060 |
0 |
0 |
T6 |
81792 |
79987 |
0 |
0 |
T7 |
563 |
497 |
0 |
0 |
T8 |
97480 |
97403 |
0 |
0 |
T9 |
98500 |
98429 |
0 |
0 |
T10 |
14638 |
13067 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1916 |
0 |
0 |
T1 |
390827 |
1 |
0 |
0 |
T2 |
122319 |
3 |
0 |
0 |
T3 |
506733 |
8 |
0 |
0 |
T4 |
592271 |
5 |
0 |
0 |
T5 |
102470 |
1 |
0 |
0 |
T6 |
388533 |
2 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
3 |
0 |
0 |
T9 |
128049 |
3 |
0 |
0 |
T10 |
358685 |
0 |
0 |
0 |
T11 |
0 |
3 |
0 |
0 |
T12 |
0 |
1 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
390827 |
390818 |
0 |
0 |
T2 |
122319 |
122319 |
0 |
0 |
T3 |
506733 |
505106 |
0 |
0 |
T4 |
592271 |
591127 |
0 |
0 |
T5 |
102470 |
102419 |
0 |
0 |
T6 |
388533 |
388515 |
0 |
0 |
T7 |
276945 |
276845 |
0 |
0 |
T8 |
116977 |
116976 |
0 |
0 |
T9 |
128049 |
128049 |
0 |
0 |
T10 |
358685 |
358539 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc
| Total | Covered | Percent |
Conditions | 11 | 10 | 90.91 |
Logical | 11 | 10 | 90.91 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T3,T4,T5 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T3,T4,T5 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T3,T4,T5 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T3,T4,T5 |
1 | 1 | Covered | T3,T4,T5 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T3,T4,T5 |
0 |
0 |
1 |
Covered |
T3,T4,T5 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T3,T4,T5 |
0 |
0 |
1 |
Covered |
T3,T4,T5 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_wakeup_ctl_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1210423 |
0 |
0 |
T3 |
506733 |
3210 |
0 |
0 |
T4 |
592271 |
415 |
0 |
0 |
T5 |
102470 |
1331 |
0 |
0 |
T6 |
388533 |
1749 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
0 |
0 |
0 |
T9 |
128049 |
0 |
0 |
0 |
T10 |
358685 |
0 |
0 |
0 |
T11 |
513901 |
5883 |
0 |
0 |
T12 |
356907 |
0 |
0 |
0 |
T28 |
0 |
1324 |
0 |
0 |
T29 |
0 |
570 |
0 |
0 |
T37 |
0 |
1265 |
0 |
0 |
T38 |
0 |
761 |
0 |
0 |
T39 |
0 |
761 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34176360 |
33829907 |
0 |
0 |
T1 |
32568 |
32504 |
0 |
0 |
T2 |
97855 |
97798 |
0 |
0 |
T3 |
22013 |
21060 |
0 |
0 |
T4 |
47380 |
42790 |
0 |
0 |
T5 |
32145 |
32060 |
0 |
0 |
T6 |
81792 |
79987 |
0 |
0 |
T7 |
563 |
497 |
0 |
0 |
T8 |
97480 |
97403 |
0 |
0 |
T9 |
98500 |
98429 |
0 |
0 |
T10 |
14638 |
13067 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
1381 |
0 |
0 |
T3 |
506733 |
5 |
0 |
0 |
T4 |
592271 |
1 |
0 |
0 |
T5 |
102470 |
1 |
0 |
0 |
T6 |
388533 |
1 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
0 |
0 |
0 |
T9 |
128049 |
0 |
0 |
0 |
T10 |
358685 |
0 |
0 |
0 |
T11 |
513901 |
3 |
0 |
0 |
T12 |
356907 |
0 |
0 |
0 |
T28 |
0 |
5 |
0 |
0 |
T29 |
0 |
2 |
0 |
0 |
T37 |
0 |
1 |
0 |
0 |
T38 |
0 |
2 |
0 |
0 |
T39 |
0 |
2 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
390827 |
390818 |
0 |
0 |
T2 |
122319 |
122319 |
0 |
0 |
T3 |
506733 |
505106 |
0 |
0 |
T4 |
592271 |
591127 |
0 |
0 |
T5 |
102470 |
102419 |
0 |
0 |
T6 |
388533 |
388515 |
0 |
0 |
T7 |
276945 |
276845 |
0 |
0 |
T8 |
116977 |
116976 |
0 |
0 |
T9 |
128049 |
128049 |
0 |
0 |
T10 |
358685 |
358539 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 22 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
ALWAYS | 71 | 6 | 6 | 100.00 |
CONT_ASSIGN | 85 | 1 | 1 | 100.00 |
CONT_ASSIGN | 109 | 1 | 1 | 100.00 |
ALWAYS | 115 | 9 | 9 | 100.00 |
CONT_ASSIGN | 150 | 1 | 1 | 100.00 |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
CONT_ASSIGN | 200 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
65 |
1 |
1 |
71 |
1 |
1 |
72 |
1 |
1 |
73 |
1 |
1 |
74 |
1 |
1 |
75 |
1 |
1 |
76 |
1 |
1 |
|
|
|
MISSING_ELSE |
85 |
1 |
1 |
109 |
1 |
1 |
115 |
1 |
1 |
116 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
123 |
1 |
1 |
124 |
1 |
1 |
125 |
1 |
1 |
134 |
1 |
1 |
135 |
1 |
1 |
|
|
|
MISSING_ELSE |
150 |
1 |
1 |
155 |
1 |
1 |
156 |
1 |
1 |
200 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc
| Total | Covered | Percent |
Conditions | 13 | 12 | 92.31 |
Logical | 13 | 12 | 92.31 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 65
EXPRESSION (src_we_i | src_re_i)
----1--- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T4 |
LINE 109
EXPRESSION (src_busy_q & ((!src_ack)))
-----1---- ------2-----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 123
EXPRESSION (src_wd_i & BitMask)
----1--- ---2---
-1- | -2- | Status | Tests |
0 | - | Covered | T1,T2,T4 |
1 | - | Covered | T1,T2,T4 |
LINE 125
EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
-----------1----------- ------------2------------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Unreachable | |
1 | 0 | Covered | T1,T2,T4 |
LINE 125
SUB-EXPRESSION (src_busy_q && src_ack)
-----1---- ---2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T4 |
1 | 1 | Covered | T1,T2,T4 |
LINE 125
SUB-EXPRESSION (src_update && ((!busy)))
-----1---- ----2----
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Unreachable | |
1 | 1 | Unreachable | |
Branch Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc
| Line No. | Total | Covered | Percent |
Branches |
|
8 |
8 |
100.00 |
IF |
71 |
4 |
4 |
100.00 |
IF |
115 |
4 |
4 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 71 if ((!rst_src_ni))
-2-: 73 if (src_req)
-3-: 75 if (src_ack)
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T4 |
0 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 115 if ((!rst_src_ni))
-2-: 118 if (src_req)
-3-: 125 if (((src_busy_q && src_ack) || (src_update && (!busy))))
Branches:
-1- | -2- | -3- | Status | Tests |
1 |
- |
- |
Covered |
T1,T2,T3 |
0 |
1 |
- |
Covered |
T1,T2,T4 |
0 |
0 |
1 |
Covered |
T1,T2,T4 |
0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg.u_adc_fsm_rst_cdc
Assertion Details
BusySrcReqChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
17729801 |
0 |
0 |
T1 |
390827 |
712 |
0 |
0 |
T2 |
122319 |
2741 |
0 |
0 |
T3 |
506733 |
0 |
0 |
0 |
T4 |
592271 |
123631 |
0 |
0 |
T5 |
102470 |
3497 |
0 |
0 |
T6 |
388533 |
287611 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
2523 |
0 |
0 |
T9 |
128049 |
2451 |
0 |
0 |
T10 |
358685 |
157297 |
0 |
0 |
T11 |
0 |
11505 |
0 |
0 |
T12 |
0 |
651 |
0 |
0 |
DstReqKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
34176360 |
33829907 |
0 |
0 |
T1 |
32568 |
32504 |
0 |
0 |
T2 |
97855 |
97798 |
0 |
0 |
T3 |
22013 |
21060 |
0 |
0 |
T4 |
47380 |
42790 |
0 |
0 |
T5 |
32145 |
32060 |
0 |
0 |
T6 |
81792 |
79987 |
0 |
0 |
T7 |
563 |
497 |
0 |
0 |
T8 |
97480 |
97403 |
0 |
0 |
T9 |
98500 |
98429 |
0 |
0 |
T10 |
14638 |
13067 |
0 |
0 |
SrcAckBusyChk_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
19477 |
0 |
0 |
T1 |
390827 |
2 |
0 |
0 |
T2 |
122319 |
6 |
0 |
0 |
T3 |
506733 |
0 |
0 |
0 |
T4 |
592271 |
284 |
0 |
0 |
T5 |
102470 |
2 |
0 |
0 |
T6 |
388533 |
172 |
0 |
0 |
T7 |
276945 |
0 |
0 |
0 |
T8 |
116977 |
6 |
0 |
0 |
T9 |
128049 |
6 |
0 |
0 |
T10 |
358685 |
184 |
0 |
0 |
T11 |
0 |
6 |
0 |
0 |
T12 |
0 |
2 |
0 |
0 |
SrcBusyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2147483647 |
2147483647 |
0 |
0 |
T1 |
390827 |
390818 |
0 |
0 |
T2 |
122319 |
122319 |
0 |
0 |
T3 |
506733 |
505106 |
0 |
0 |
T4 |
592271 |
591127 |
0 |
0 |
T5 |
102470 |
102419 |
0 |
0 |
T6 |
388533 |
388515 |
0 |
0 |
T7 |
276945 |
276845 |
0 |
0 |
T8 |
116977 |
116976 |
0 |
0 |
T9 |
128049 |
128049 |
0 |
0 |
T10 |
358685 |
358539 |
0 |
0 |