Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2480	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2227	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2491	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2191	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2520	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2297	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2194	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2312	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2101	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2347	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2519	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2497	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2250	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2320	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2369	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2419	0	0
adc_en_ctl_rd_A	2147483647	1962	0	0
adc_fsm_rst_rd_A	2147483647	1963	0	0
adc_intr_ctl_rd_A	2147483647	2629	0	0
adc_lp_sample_ctl_rd_A	2147483647	1804	0	0
adc_pd_ctl_rd_A	2147483647	2227	0	0
adc_sample_ctl_rd_A	2147483647	1690	0	0
adc_wakeup_ctl_rd_A	2147483647	2055	0	0
intr_enable_rd_A	2147483647	2695	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2480	0	0
T4	592271	34	0	0
T5	102470	0	0	0
T6	388533	0	0	0
T7	276945	0	0	0
T8	116977	0	0	0
T9	128049	0	0	0
T10	358685	0	0	0
T11	513901	0	0	0
T12	356907	0	0	0
T13	0	34	0	0
T14	0	40	0	0
T15	0	11	0	0
T16	0	7	0	0
T17	0	13	0	0
T18	0	19	0	0
T19	0	31	0	0
T20	0	11	0	0
T21	0	43	0	0
T22	24531	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2227	0	0
T4	592271	20	0	0
T5	102470	0	0	0
T6	388533	0	0	0
T7	276945	0	0	0
T8	116977	0	0	0
T9	128049	0	0	0
T10	358685	0	0	0
T11	513901	0	0	0
T12	356907	0	0	0
T13	0	41	0	0
T14	0	30	0	0
T15	0	15	0	0
T16	0	12	0	0
T17	0	13	0	0
T18	0	21	0	0
T19	0	36	0	0
T20	0	12	0	0
T21	0	39	0	0
T22	24531	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2491	0	0
T4	592271	30	0	0
T5	102470	0	0	0
T6	388533	0	0	0
T7	276945	0	0	0
T8	116977	0	0	0
T9	128049	0	0	0
T10	358685	0	0	0
T11	513901	0	0	0
T12	356907	0	0	0
T13	0	31	0	0
T14	0	48	0	0
T15	0	9	0	0
T16	0	10	0	0
T17	0	13	0	0
T18	0	9	0	0
T19	0	30	0	0
T20	0	18	0	0
T21	0	24	0	0
T22	24531	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2191	0	0
T4	592271	40	0	0
T5	102470	0	0	0
T6	388533	0	0	0
T7	276945	0	0	0
T8	116977	0	0	0
T9	128049	0	0	0
T10	358685	0	0	0
T11	513901	0	0	0
T12	356907	0	0	0
T13	0	37	0	0
T14	0	33	0	0
T15	0	12	0	0
T16	0	14	0	0
T17	0	12	0	0
T18	0	14	0	0
T19	0	47	0	0
T20	0	9	0	0
T21	0	32	0	0
T22	24531	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2520	0	0
T4	592271	51	0	0
T5	102470	0	0	0
T6	388533	0	0	0
T7	276945	0	0	0
T8	116977	0	0	0
T9	128049	0	0	0
T10	358685	0	0	0
T11	513901	0	0	0
T12	356907	0	0	0
T13	0	32	0	0
T14	0	38	0	0
T15	0	15	0	0
T16	0	18	0	0
T17	0	20	0	0
T18	0	14	0	0
T19	0	32	0	0
T20	0	25	0	0
T21	0	27	0	0
T22	24531	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2297	0	0
T4	592271	33	0	0
T5	102470	0	0	0
T6	388533	0	0	0
T7	276945	0	0	0
T8	116977	0	0	0
T9	128049	0	0	0
T10	358685	0	0	0
T11	513901	0	0	0
T12	356907	0	0	0
T13	0	31	0	0
T14	0	39	0	0
T15	0	29	0	0
T16	0	10	0	0
T17	0	12	0	0
T18	0	21	0	0
T19	0	3	0	0
T20	0	17	0	0
T21	0	21	0	0
T22	24531	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2194	0	0
T4	592271	33	0	0
T5	102470	0	0	0
T6	388533	0	0	0
T7	276945	0	0	0
T8	116977	0	0	0
T9	128049	0	0	0
T10	358685	0	0	0
T11	513901	0	0	0
T12	356907	0	0	0
T13	0	25	0	0
T14	0	32	0	0
T15	0	23	0	0
T16	0	8	0	0
T17	0	3	0	0
T18	0	15	0	0
T19	0	22	0	0
T20	0	12	0	0
T21	0	28	0	0
T22	24531	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2312	0	0
T4	592271	35	0	0
T5	102470	0	0	0
T6	388533	0	0	0
T7	276945	0	0	0
T8	116977	0	0	0
T9	128049	0	0	0
T10	358685	0	0	0
T11	513901	0	0	0
T12	356907	0	0	0
T13	0	35	0	0
T14	0	42	0	0
T15	0	14	0	0
T16	0	2	0	0
T17	0	24	0	0
T18	0	25	0	0
T19	0	33	0	0
T20	0	15	0	0
T21	0	39	0	0
T22	24531	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2101	0	0
T4	592271	27	0	0
T5	102470	0	0	0
T6	388533	0	0	0
T7	276945	0	0	0
T8	116977	0	0	0
T9	128049	0	0	0
T10	358685	0	0	0
T11	513901	0	0	0
T12	356907	0	0	0
T13	0	35	0	0
T14	0	25	0	0
T15	0	10	0	0
T16	0	20	0	0
T17	0	13	0	0
T18	0	27	0	0
T19	0	27	0	0
T20	0	29	0	0
T21	0	16	0	0
T22	24531	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2347	0	0
T4	592271	31	0	0
T5	102470	0	0	0
T6	388533	0	0	0
T7	276945	0	0	0
T8	116977	0	0	0
T9	128049	0	0	0
T10	358685	0	0	0
T11	513901	0	0	0
T12	356907	0	0	0
T13	0	41	0	0
T14	0	40	0	0
T15	0	19	0	0
T16	0	18	0	0
T17	0	14	0	0
T18	0	34	0	0
T19	0	25	0	0
T20	0	23	0	0
T21	0	36	0	0
T22	24531	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2519	0	0
T4	592271	35	0	0
T5	102470	0	0	0
T6	388533	0	0	0
T7	276945	0	0	0
T8	116977	0	0	0
T9	128049	0	0	0
T10	358685	0	0	0
T11	513901	0	0	0
T12	356907	0	0	0
T13	0	45	0	0
T14	0	44	0	0
T15	0	19	0	0
T16	0	10	0	0
T17	0	24	0	0
T18	0	12	0	0
T19	0	30	0	0
T20	0	30	0	0
T21	0	15	0	0
T22	24531	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2497	0	0
T4	592271	37	0	0
T5	102470	0	0	0
T6	388533	0	0	0
T7	276945	0	0	0
T8	116977	0	0	0
T9	128049	0	0	0
T10	358685	0	0	0
T11	513901	0	0	0
T12	356907	0	0	0
T13	0	32	0	0
T14	0	37	0	0
T15	0	22	0	0
T16	0	17	0	0
T17	0	20	0	0
T18	0	7	0	0
T19	0	25	0	0
T20	0	14	0	0
T21	0	16	0	0
T22	24531	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2250	0	0
T4	592271	26	0	0
T5	102470	0	0	0
T6	388533	0	0	0
T7	276945	0	0	0
T8	116977	0	0	0
T9	128049	0	0	0
T10	358685	0	0	0
T11	513901	0	0	0
T12	356907	0	0	0
T13	0	38	0	0
T14	0	36	0	0
T15	0	20	0	0
T16	0	13	0	0
T17	0	13	0	0
T18	0	37	0	0
T19	0	31	0	0
T20	0	16	0	0
T21	0	23	0	0
T22	24531	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2320	0	0
T4	592271	41	0	0
T5	102470	0	0	0
T6	388533	0	0	0
T7	276945	0	0	0
T8	116977	0	0	0
T9	128049	0	0	0
T10	358685	0	0	0
T11	513901	0	0	0
T12	356907	0	0	0
T13	0	34	0	0
T14	0	36	0	0
T15	0	9	0	0
T16	0	14	0	0
T17	0	17	0	0
T18	0	17	0	0
T19	0	14	0	0
T20	0	18	0	0
T21	0	33	0	0
T22	24531	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2369	0	0
T4	592271	35	0	0
T5	102470	0	0	0
T6	388533	0	0	0
T7	276945	0	0	0
T8	116977	0	0	0
T9	128049	0	0	0
T10	358685	0	0	0
T11	513901	0	0	0
T12	356907	0	0	0
T13	0	24	0	0
T14	0	34	0	0
T15	0	22	0	0
T16	0	10	0	0
T17	0	7	0	0
T18	0	14	0	0
T19	0	32	0	0
T20	0	26	0	0
T21	0	28	0	0
T22	24531	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2419	0	0
T4	592271	40	0	0
T5	102470	0	0	0
T6	388533	0	0	0
T7	276945	0	0	0
T8	116977	0	0	0
T9	128049	0	0	0
T10	358685	0	0	0
T11	513901	0	0	0
T12	356907	0	0	0
T13	0	44	0	0
T14	0	28	0	0
T15	0	13	0	0
T16	0	3	0	0
T17	0	17	0	0
T18	0	20	0	0
T19	0	30	0	0
T20	0	20	0	0
T21	0	30	0	0
T22	24531	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1962	0	0
T4	592271	42	0	0
T5	102470	0	0	0
T6	388533	0	0	0
T7	276945	0	0	0
T8	116977	0	0	0
T9	128049	0	0	0
T10	358685	0	0	0
T11	513901	0	0	0
T12	356907	0	0	0
T13	0	39	0	0
T14	0	34	0	0
T15	0	12	0	0
T16	0	15	0	0
T17	0	9	0	0
T18	0	12	0	0
T19	0	24	0	0
T20	0	13	0	0
T21	0	33	0	0
T22	24531	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1963	0	0
T4	592271	28	0	0
T5	102470	0	0	0
T6	388533	0	0	0
T7	276945	0	0	0
T8	116977	0	0	0
T9	128049	0	0	0
T10	358685	0	0	0
T11	513901	0	0	0
T12	356907	0	0	0
T13	0	50	0	0
T14	0	35	0	0
T15	0	18	0	0
T16	0	14	0	0
T17	0	25	0	0
T18	0	11	0	0
T19	0	22	0	0
T20	0	20	0	0
T21	0	17	0	0
T22	24531	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2629	0	0
T4	592271	39	0	0
T5	102470	0	0	0
T6	388533	0	0	0
T7	276945	0	0	0
T8	116977	0	0	0
T9	128049	0	0	0
T10	358685	0	0	0
T11	513901	0	0	0
T12	356907	0	0	0
T13	0	34	0	0
T14	0	51	0	0
T15	0	11	0	0
T16	0	8	0	0
T17	0	19	0	0
T18	0	10	0	0
T19	0	26	0	0
T20	0	31	0	0
T21	0	39	0	0
T22	24531	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1804	0	0
T4	592271	27	0	0
T5	102470	0	0	0
T6	388533	0	0	0
T7	276945	0	0	0
T8	116977	0	0	0
T9	128049	0	0	0
T10	358685	0	0	0
T11	513901	0	0	0
T12	356907	0	0	0
T13	0	37	0	0
T14	0	29	0	0
T15	0	16	0	0
T16	0	6	0	0
T17	0	30	0	0
T18	0	18	0	0
T19	0	31	0	0
T20	0	15	0	0
T21	0	24	0	0
T22	24531	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2227	0	0
T4	592271	45	0	0
T5	102470	0	0	0
T6	388533	0	0	0
T7	276945	0	0	0
T8	116977	0	0	0
T9	128049	0	0	0
T10	358685	0	0	0
T11	513901	0	0	0
T12	356907	0	0	0
T13	0	39	0	0
T14	0	35	0	0
T15	0	16	0	0
T16	0	8	0	0
T17	0	15	0	0
T18	0	15	0	0
T19	0	38	0	0
T20	0	17	0	0
T21	0	28	0	0
T22	24531	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1690	0	0
T4	592271	36	0	0
T5	102470	0	0	0
T6	388533	0	0	0
T7	276945	0	0	0
T8	116977	0	0	0
T9	128049	0	0	0
T10	358685	0	0	0
T11	513901	0	0	0
T12	356907	0	0	0
T13	0	41	0	0
T14	0	29	0	0
T15	0	16	0	0
T17	0	15	0	0
T18	0	26	0	0
T19	0	32	0	0
T20	0	11	0	0
T21	0	12	0	0
T22	24531	0	0	0
T23	0	27	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2055	0	0
T4	592271	47	0	0
T5	102470	0	0	0
T6	388533	0	0	0
T7	276945	0	0	0
T8	116977	0	0	0
T9	128049	0	0	0
T10	358685	0	0	0
T11	513901	0	0	0
T12	356907	0	0	0
T13	0	45	0	0
T14	0	33	0	0
T15	0	11	0	0
T16	0	8	0	0
T17	0	14	0	0
T18	0	15	0	0
T19	0	30	0	0
T20	0	24	0	0
T21	0	28	0	0
T22	24531	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2695	0	0
T4	592271	32	0	0
T5	102470	0	0	0
T6	388533	0	0	0
T7	276945	0	0	0
T8	116977	0	0	0
T9	128049	0	0	0
T10	358685	0	0	0
T11	513901	0	0	0
T12	356907	0	0	0
T13	0	46	0	0
T14	0	60	0	0
T15	0	21	0	0
T16	0	21	0	0
T17	0	13	0	0
T22	24531	0	0	0
T24	0	35	0	0
T25	0	12	0	0
T26	0	5	0	0
T27	0	13	0	0