| | | | | | | |
tb.dut.AdcKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.AlertsKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.FpvSecCmRegWeOnehotCheck_A
| 0 | 0 | 2147483647 | 80 | 0 | 0 |
|
tb.dut.IntrKnown
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.TlOAReadyKnown
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.TlODValidKnown
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.WakeKnown
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_0_rd_A
| 0 | 0 | 2147483647 | 1750 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_1_rd_A
| 0 | 0 | 2147483647 | 1669 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_2_rd_A
| 0 | 0 | 2147483647 | 1687 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_3_rd_A
| 0 | 0 | 2147483647 | 1779 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_4_rd_A
| 0 | 0 | 2147483647 | 1793 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_5_rd_A
| 0 | 0 | 2147483647 | 1705 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_6_rd_A
| 0 | 0 | 2147483647 | 1731 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_7_rd_A
| 0 | 0 | 2147483647 | 1651 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_0_rd_A
| 0 | 0 | 2147483647 | 1787 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_1_rd_A
| 0 | 0 | 2147483647 | 1753 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_2_rd_A
| 0 | 0 | 2147483647 | 1549 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_3_rd_A
| 0 | 0 | 2147483647 | 1656 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_4_rd_A
| 0 | 0 | 2147483647 | 1532 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_5_rd_A
| 0 | 0 | 2147483647 | 1677 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_6_rd_A
| 0 | 0 | 2147483647 | 1714 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_7_rd_A
| 0 | 0 | 2147483647 | 1821 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_en_ctl_rd_A
| 0 | 0 | 2147483647 | 1453 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_fsm_rst_rd_A
| 0 | 0 | 2147483647 | 1236 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_intr_ctl_rd_A
| 0 | 0 | 2147483647 | 1630 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_lp_sample_ctl_rd_A
| 0 | 0 | 2147483647 | 1269 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_pd_ctl_rd_A
| 0 | 0 | 2147483647 | 1461 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_sample_ctl_rd_A
| 0 | 0 | 2147483647 | 1225 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.adc_wakeup_ctl_rd_A
| 0 | 0 | 2147483647 | 1399 | 0 | 0 |
|
tb.dut.adc_ctrl_csr_assert.intr_enable_rd_A
| 0 | 0 | 2147483647 | 1770 | 0 | 0 |
|
tb.dut.tlul_assert_device.aKnown_A
| 0 | 0 | 2147483647 | 27598410 | 0 | 0 |
|
tb.dut.tlul_assert_device.aKnown_AKnownEnable
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.tlul_assert_device.aReadyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.tlul_assert_device.dKnown_A
| 0 | 0 | 2147483647 | 4391178 | 0 | 0 |
|
tb.dut.tlul_assert_device.dKnown_AKnownEnable
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.tlul_assert_device.dReadyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[19].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[201].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[202].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[203].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[204].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[205].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[206].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[207].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[208].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[209].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[20].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[210].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[211].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[212].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[213].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[214].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[215].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[216].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[217].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[218].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[219].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[21].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[220].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[221].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[222].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[223].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[224].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[225].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[226].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[227].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[228].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[229].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[22].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[230].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[231].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[232].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[233].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[234].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[235].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[236].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[237].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[238].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[239].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[23].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[240].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[241].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[242].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[243].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[244].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[245].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[246].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[247].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[248].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[249].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[24].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[250].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[251].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[252].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[253].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[254].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[255].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[25].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[26].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[27].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[28].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[29].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[2].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[30].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[31].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[32].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[33].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[34].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[35].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[36].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[37].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[38].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[39].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[3].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[41].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[42].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[44].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[45].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[53].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[54].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[55].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[56].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[57].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[58].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[5].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.aDataKnown_M
| 0 | 0 | 2147483647 | 17431680 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A
| 0 | 0 | 2147483647 | 2833 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.contigMask_M
| 0 | 0 | 2147483647 | 17081891 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.dDataKnown_A
| 0 | 0 | 2147483647 | 3645920 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A
| 0 | 0 | 2147483647 | 2714 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.legalAParam_M
| 0 | 0 | 2147483647 | 27598518 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.legalDParam_A
| 0 | 0 | 2147483647 | 4391242 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M
| 0 | 0 | 2147483647 | 27598518 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A
| 0 | 0 | 2147483647 | 4391242 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.respOpcode_A
| 0 | 0 | 2147483647 | 4391242 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A
| 0 | 0 | 2147483647 | 4391242 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A
| 0 | 0 | 2147483647 | 2472 | 0 | 0 |
|
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A
| 0 | 0 | 2147483647 | 2851 | 0 | 0 |
|
tb.dut.tlul_assert_device.p_dbw.TlDbw_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.MaxFilters_A
| 0 | 0 | 33062736 | 32761972 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[0].MatchCheck00_A
| 0 | 0 | 33062736 | 10424279 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[0].MatchCheck01_A
| 0 | 0 | 33062736 | 2294539 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[0].MatchCheck10_A
| 0 | 0 | 33062736 | 1936825 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[0].MatchCheck11_A
| 0 | 0 | 33062736 | 18106329 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[1].MatchCheck00_A
| 0 | 0 | 33062736 | 10759670 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[1].MatchCheck01_A
| 0 | 0 | 33062736 | 1049894 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[1].MatchCheck10_A
| 0 | 0 | 33062736 | 1106333 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[1].MatchCheck11_A
| 0 | 0 | 33062736 | 19846075 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[2].MatchCheck00_A
| 0 | 0 | 33062736 | 12178523 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[2].MatchCheck01_A
| 0 | 0 | 33062736 | 457578 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[2].MatchCheck10_A
| 0 | 0 | 33062736 | 852163 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[2].MatchCheck11_A
| 0 | 0 | 33062736 | 19273708 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[3].MatchCheck00_A
| 0 | 0 | 33062736 | 12199887 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[3].MatchCheck01_A
| 0 | 0 | 33062736 | 275566 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[3].MatchCheck10_A
| 0 | 0 | 33062736 | 333111 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[3].MatchCheck11_A
| 0 | 0 | 33062736 | 19953408 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[4].MatchCheck00_A
| 0 | 0 | 33062736 | 12492508 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[4].MatchCheck01_A
| 0 | 0 | 33062736 | 10 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[4].MatchCheck10_A
| 0 | 0 | 33062736 | 34617 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[4].MatchCheck11_A
| 0 | 0 | 33062736 | 20234837 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[5].MatchCheck00_A
| 0 | 0 | 33062736 | 12327471 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[5].MatchCheck01_A
| 0 | 0 | 33062736 | 12 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[5].MatchCheck10_A
| 0 | 0 | 33062736 | 143137 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[5].MatchCheck11_A
| 0 | 0 | 33062736 | 20291352 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[6].MatchCheck00_A
| 0 | 0 | 33062736 | 12830776 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[6].MatchCheck01_A
| 0 | 0 | 33062736 | 33379 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[6].MatchCheck10_A
| 0 | 0 | 33062736 | 5735 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[6].MatchCheck11_A
| 0 | 0 | 33062736 | 19892082 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[7].MatchCheck00_A
| 0 | 0 | 33062736 | 11256461 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[7].MatchCheck01_A
| 0 | 0 | 33062736 | 104005 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[7].MatchCheck10_A
| 0 | 0 | 33062736 | 67624 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.gen_filter_match[7].MatchCheck11_A
| 0 | 0 | 33062736 | 21333882 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.LpSampleCntCfg_M
| 0 | 0 | 30552650 | 30469591 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.NpCntClrMisMatch_A
| 0 | 0 | 30552650 | 166873 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.NpCntClrPwrDn_A
| 0 | 0 | 30552650 | 90463 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.NpSampleCntCfg_M
| 0 | 0 | 30552650 | 30469591 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.FsmDebugOut_A
| 0 | 0 | 30552650 | 30469591 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.FsmStateHwReset_A
| 0 | 0 | 1199 | 1199 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.FsmStateSwReset_A
| 0 | 0 | 30552650 | 6347 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.LpSampleCntHwReset_A
| 0 | 0 | 1199 | 1199 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.LpSampleCntSwReset_A
| 0 | 0 | 30552650 | 6347 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.NpSampleCntHwReset_A
| 0 | 0 | 1199 | 1199 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.NpSampleCntSwReset_A
| 0 | 0 | 30552650 | 6347 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.PwrupTimerCntHwReset_A
| 0 | 0 | 1199 | 1199 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.PwrupTimerCntSwReset_A
| 0 | 0 | 30552650 | 6347 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.WakeupTimerCntHwReset_A
| 0 | 0 | 1199 | 1199 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.WakeupTimerCntSwReset_A
| 0 | 0 | 30552650 | 6347 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.i_adc_ctrl_intr_o.IntrTKind_A
| 0 | 0 | 754 | 754 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.u_match_sync.SyncReqAckAckNeedsReq
| 0 | 0 | 2147483647 | 16264 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.u_match_sync.SyncReqAckHoldReq
| 0 | 0 | 33062736 | 16263 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_oneshot_done_sync.DstPulseCheck_A
| 0 | 0 | 2147483647 | 6015 | 0 | 0 |
|
tb.dut.u_adc_ctrl_core.u_oneshot_done_sync.SrcPulseCheck_M
| 0 | 0 | 33062736 | 6019 | 0 | 0 |
|
tb.dut.u_reg.en2addrHit
| 0 | 0 | 2147483647 | 2248959 | 0 | 0 |
|
tb.dut.u_reg.reAfterRv
| 0 | 0 | 2147483647 | 2248959 | 0 | 0 |
|
tb.dut.u_reg.rePulse
| 0 | 0 | 2147483647 | 1973992 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1965447 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.DstReqKnown_A
| 0 | 0 | 33152477 | 32816069 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 2130 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 2130 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 33152477 | 2130 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 33152477 | 1986 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 2141 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1852671 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.DstReqKnown_A
| 0 | 0 | 33152477 | 32816069 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 2044 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 2044 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 33152477 | 2044 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 33152477 | 1900 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 2052 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1832444 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.DstReqKnown_A
| 0 | 0 | 33152477 | 32816069 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 2035 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 2035 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 33152477 | 2035 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 33152477 | 1895 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 2046 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1867000 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.DstReqKnown_A
| 0 | 0 | 33152477 | 32816069 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 2072 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 2072 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 33152477 | 2072 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 33152477 | 1934 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 2084 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1818693 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.DstReqKnown_A
| 0 | 0 | 33152477 | 32816069 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 2022 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 2022 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 33152477 | 2022 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 33152477 | 1883 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 2031 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1826714 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.DstReqKnown_A
| 0 | 0 | 33152477 | 32816069 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 2047 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 2047 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 33152477 | 2047 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 33152477 | 1910 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 2059 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1817815 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.DstReqKnown_A
| 0 | 0 | 33152477 | 32816069 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 2038 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 2038 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 33152477 | 2038 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 33152477 | 1890 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 2050 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1825703 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.DstReqKnown_A
| 0 | 0 | 33152477 | 32816069 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 2030 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 2030 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 33152477 | 2030 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 33152477 | 1887 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 2040 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1935252 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.DstReqKnown_A
| 0 | 0 | 33152477 | 32816069 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 2158 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 2158 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 33152477 | 2158 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 33152477 | 2014 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 2167 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1808667 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.DstReqKnown_A
| 0 | 0 | 33152477 | 32816069 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 2032 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 2032 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 33152477 | 2032 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 33152477 | 1891 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 2043 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1782064 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.DstReqKnown_A
| 0 | 0 | 33152477 | 32816069 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 2015 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 2015 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 33152477 | 2015 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 33152477 | 1871 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 2024 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1754505 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.DstReqKnown_A
| 0 | 0 | 33152477 | 32816069 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 2015 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 2015 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 33152477 | 2015 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 33152477 | 1875 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 2025 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1777051 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.DstReqKnown_A
| 0 | 0 | 33152477 | 32816069 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 2024 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 2024 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 33152477 | 2024 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 33152477 | 1886 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 2036 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1780536 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.DstReqKnown_A
| 0 | 0 | 33152477 | 32816069 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 2030 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 2030 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 33152477 | 2030 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 33152477 | 1891 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 2040 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1745525 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.DstReqKnown_A
| 0 | 0 | 33152477 | 32816069 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 1997 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 1997 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 33152477 | 1997 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 33152477 | 1857 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 2005 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1823914 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.DstReqKnown_A
| 0 | 0 | 33152477 | 32816069 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 2074 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 2074 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 33152477 | 2074 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 33152477 | 1933 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 2084 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn_val_0_cdc.DstReqKnown_A
| 0 | 0 | 33152477 | 32816069 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn_val_0_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A
| 0 | 0 | 33152477 | 615559 | 0 | 919 |
|
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.HwIdSelCheck_A
| 0 | 0 | 33152477 | 615730 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq
| 0 | 0 | 2147483647 | 615738 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq
| 0 | 0 | 33152477 | 615429 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn_val_1_cdc.DstReqKnown_A
| 0 | 0 | 33152477 | 32816069 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn_val_1_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A
| 0 | 0 | 33152477 | 602621 | 0 | 919 |
|
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.HwIdSelCheck_A
| 0 | 0 | 33152477 | 609935 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq
| 0 | 0 | 2147483647 | 609942 | 0 | 0 |
|
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq
| 0 | 0 | 33152477 | 600122 | 0 | 0 |
|
tb.dut.u_reg.u_adc_en_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 35607210 | 0 | 0 |
|
tb.dut.u_reg.u_adc_en_ctl_cdc.DstReqKnown_A
| 0 | 0 | 33152477 | 32816069 | 0 | 0 |
|
tb.dut.u_reg.u_adc_en_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 36056 | 0 | 0 |
|
tb.dut.u_reg.u_adc_en_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 36056 | 0 | 0 |
|
tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 33152477 | 36071 | 0 | 0 |
|
tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 33152477 | 35907 | 0 | 0 |
|
tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 36108 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_rst_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 18001027 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_rst_cdc.DstReqKnown_A
| 0 | 0 | 33152477 | 32816069 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_rst_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 18443 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_rst_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 18443 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 33152477 | 18443 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 33152477 | 18305 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 18455 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_state_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 102446 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_state_cdc.DstReqKnown_A
| 0 | 0 | 33152477 | 32816069 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_state_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 84 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_state_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.HwIdSelCheck_A
| 0 | 0 | 33152477 | 3119865 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq
| 0 | 0 | 2147483647 | 3119985 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq
| 0 | 0 | 33152477 | 1625373 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 33152477 | 79 | 0 | 0 |
|
tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 404 | 0 | 0 |
|
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 12553238 | 0 | 0 |
|
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.DstReqKnown_A
| 0 | 0 | 33152477 | 32816069 | 0 | 0 |
|
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 13201 | 0 | 0 |
|
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 13201 | 0 | 0 |
|
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 33152477 | 13201 | 0 | 0 |
|
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 33152477 | 13037 | 0 | 0 |
|
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 13246 | 0 | 0 |
|
tb.dut.u_reg.u_adc_pd_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 16125681 | 0 | 0 |
|
tb.dut.u_reg.u_adc_pd_ctl_cdc.DstReqKnown_A
| 0 | 0 | 33152477 | 32816069 | 0 | 0 |
|
tb.dut.u_reg.u_adc_pd_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 17016 | 0 | 0 |
|
tb.dut.u_reg.u_adc_pd_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 17016 | 0 | 0 |
|
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 33152477 | 17016 | 0 | 0 |
|
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 33152477 | 16879 | 0 | 0 |
|
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 17032 | 0 | 0 |
|
tb.dut.u_reg.u_adc_sample_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 12627102 | 0 | 0 |
|
tb.dut.u_reg.u_adc_sample_ctl_cdc.DstReqKnown_A
| 0 | 0 | 33152477 | 32816069 | 0 | 0 |
|
tb.dut.u_reg.u_adc_sample_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 13212 | 0 | 0 |
|
tb.dut.u_reg.u_adc_sample_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 13212 | 0 | 0 |
|
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 33152477 | 13212 | 0 | 0 |
|
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 33152477 | 13045 | 0 | 0 |
|
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 13259 | 0 | 0 |
|
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 1254683 | 0 | 0 |
|
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.DstReqKnown_A
| 0 | 0 | 33152477 | 32816069 | 0 | 0 |
|
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 1472 | 0 | 0 |
|
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A
| 0 | 0 | 2147483647 | 1472 | 0 | 0 |
|
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M
| 0 | 0 | 33152477 | 1472 | 0 | 0 |
|
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 33152477 | 1326 | 0 | 0 |
|
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 1481 | 0 | 0 |
|
tb.dut.u_reg.u_chk.PayLoadWidthCheck
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.u_reg.u_filter_status_cdc.BusySrcReqChk_A
| 0 | 0 | 2147483647 | 62740956 | 0 | 0 |
|
tb.dut.u_reg.u_filter_status_cdc.DstReqKnown_A
| 0 | 0 | 33152477 | 32816069 | 0 | 0 |
|
tb.dut.u_reg.u_filter_status_cdc.SrcAckBusyChk_A
| 0 | 0 | 2147483647 | 64918 | 0 | 0 |
|
tb.dut.u_reg.u_filter_status_cdc.SrcBusyKnown_A
| 0 | 0 | 2147483647 | 2147483647 | 0 | 0 |
|
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A
| 0 | 0 | 33152477 | 14616 | 0 | 919 |
|
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.HwIdSelCheck_A
| 0 | 0 | 33152477 | 14686 | 0 | 0 |
|
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq
| 0 | 0 | 2147483647 | 79604 | 0 | 0 |
|
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq
| 0 | 0 | 33152477 | 78662 | 0 | 0 |
|
tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req.DstPulseCheck_A
| 0 | 0 | 33152477 | 64778 | 0 | 0 |
|
tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req.SrcPulseCheck_M
| 0 | 0 | 2147483647 | 64931 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.AllowedLatency_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.MatchedWidthAssert
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck
| 0 | 0 | 919 | 919 | 0 | 0 |
|
tb.dut.u_reg.wePulse
| 0 | 0 | 2147483647 | 274967 | 0 | 0 |
|