Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6470	1			T34	17		T41	20		T35	108
testmodes[AdcCtrlTestmodeNormal]	5088	1			T2	3		T3	1		T4	3
testmodes[AdcCtrlTestmodeLowpower]	5411	1			T1	1		T3	2		T8	3
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3498	1			T34	10		T41	19		T35	42
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1620	1			T34	5		T35	39		T43	10
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1235	1			T34	2		T35	26		T43	18
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1617	1			T34	5		T35	41		T43	12
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	1859	1			T2	2		T4	2		T7	1
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1274	1			T3	1		T34	1		T35	32
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1243	1			T34	2		T35	25		T43	16
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1279	1			T48	1		T34	1		T35	34
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2645	1			T3	1		T8	2		T10	2