Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24537

1

T1

26

T2

3

T3

54

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21226

1

T2

3

T3

8

T4

2

auto[ADC_CTRL_FILTER_COND_OUT]

3311

1

T1

26

T3

46

T4

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18935

1

T3

31

T4

2

T5

10

auto[1]

5602

1

T1

26

T2

3

T3

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20769

1

T1

11

T2

3

T3

27

auto[1]

3768

1

T1

15

T3

27

T5

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	21	1			T206	21		-	-		-	-
values[0]	12	1			T207	12		-	-		-	-
values[1]	687	1			T3	23		T47	10		T34	4
values[2]	2936	1			T2	3		T4	1		T8	35
values[3]	570	1			T6	21		T37	3		T23	1
values[4]	555	1			T1	26		T4	1		T152	14
values[5]	652	1			T7	6		T35	3		T44	1
values[6]	584	1			T3	31		T7	14		T40	1
values[7]	836	1			T48	16		T35	3		T46	14
values[8]	578	1			T4	1		T36	2		T143	1
values[9]	1048	1			T5	10		T9	2		T48	23
minimum	16058	1			T6	2		T34	45		T41	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	799	1			T3	23		T4	1		T47	10
values[1]	2987	1			T2	3		T6	21		T8	35
values[2]	573	1			T37	3		T152	14		T153	17
values[3]	599	1			T1	26		T4	1		T44	1
values[4]	633	1			T3	8		T40	1		T35	3
values[5]	674	1			T7	20		T111	8		T152	13
values[6]	690	1			T3	23		T48	16		T35	3
values[7]	657	1			T4	1		T48	23		T40	18
values[8]	746	1			T9	2		T34	7		T35	47
values[9]	118	1			T5	10		T38	5		T208	12
minimum	16061	1			T6	2		T34	45		T41	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20737

1

T1

16

T2

3

T3

30

auto[1]

3800

1

T1

10

T3

24

T6

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T34	2		T153	8		T209	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T3	11		T4	1		T47	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1619	1			T2	3		T8	35		T10	41
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T6	6		T111	13		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T152	14		T39	7		T210	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T37	2		T153	1		T28	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T4	1		T152	4		T23	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T1	11		T44	1		T36	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T3	5		T35	2		T190	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T40	1		T143	1		T211	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T7	1		T111	8		T152	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T7	1		T12	5		T212	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T48	8		T137	1		T190	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	11		T35	2		T46	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T4	1		T48	11		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T211	12		T141	1		T84	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T9	1		T34	5		T35	27
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T111	12		T213	14		T28	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T5	1		T38	3		T167	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T208	1		T214	3		T215	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15907	1			T34	44		T41	20		T35	332
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T34	2		T153	8		T209	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T3	12		T155	15		T49	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	976	1			T174	20		T29	14		T154	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T6	15		T111	9		T155	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T39	3		T83	12		T216	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T37	1		T153	16		T28	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T166	13		T217	2		T141	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T1	15		T36	1		T142	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T3	3		T35	1		T15	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T211	6		T27	15		T138	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T7	5		T140	11		T97	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T7	13		T12	3		T212	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T48	8		T137	5		T190	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T3	12		T35	1		T46	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T48	12		T40	17		T142	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T211	12		T84	11		T92	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T9	1		T34	2		T35	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T111	10		T28	14		T49	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T5	9		T38	2		T218	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T208	11		T214	2		T215	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T6	2		T34	1		T35	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T206	12		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T207	12		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T34	2		T153	8		T209	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T3	11		T47	10		T37	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1665	1			T2	3		T8	35		T10	41
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T4	1		T111	13		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T23	1		T29	18		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T6	6		T37	2		T28	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T4	1		T152	14		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T1	11		T211	7		T153	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T7	1		T35	2		T152	4
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T44	1		T36	3		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T3	5		T152	13		T23	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T3	11		T7	1		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T48	8		T111	8		T140	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T35	2		T46	1		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T4	1		T36	2		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T211	12		T140	11		T84	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T5	1		T9	1		T48	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T111	12		T213	14		T28	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15906	1			T34	44		T41	20		T35	332
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T206	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T34	2		T153	8		T209	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	12		T155	15		T49	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	995	1			T174	20		T154	21		T219	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T111	9		T155	1		T27	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T29	14		T39	3		T83	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T6	15		T37	1		T28	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T216	3		T182	12		T220	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T1	15		T153	16		T14	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T7	5		T35	1		T166	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T36	1		T142	1		T27	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T3	3		T190	2		T97	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T3	12		T7	13		T211	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T48	8		T140	11		T221	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T35	1		T46	13		T165	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T137	5		T191	4		T97	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T211	12		T140	8		T84	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T5	9		T9	1		T48	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T111	10		T28	14		T49	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	2		T34	1		T35	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T34	3		T153	9		T209	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T3	13		T4	1		T47	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1304	1			T2	3		T8	3		T10	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T6	16		T111	10		T155	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T152	1		T39	9		T210	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T37	2		T153	17		T28	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T4	1		T152	1		T23	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T1	16		T44	1		T36	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T3	4		T35	2		T190	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T40	1		T143	1		T211	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T7	6		T111	1		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T7	14		T12	7		T212	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T48	9		T137	6		T190	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T3	13		T35	3		T46	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T4	1		T48	13		T40	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T211	13		T141	1		T84	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T9	2		T34	5		T35	24
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T111	11		T213	1		T28	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	62	1			T5	10		T38	5		T167	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T208	12		T214	5		T215	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16061	1			T6	2		T34	45		T41	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T34	1		T153	7		T222	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T3	10		T47	9		T155	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1291	1			T8	32		T10	38		T42	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T6	5		T111	12		T140	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T152	13		T39	1		T210	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T37	1		T28	8		T223	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T152	3		T166	13		T13	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T1	10		T36	1		T211	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T3	4		T35	1		T15	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T145	12		T204	13		T224	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T111	7		T152	12		T140	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T12	1		T225	10		T226	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T48	7		T227	9		T228	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T3	10		T145	21		T28	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T48	10		T142	13		T229	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T211	11		T84	9		T92	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T34	2		T35	23		T230	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T111	11		T213	13		T28	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T167	2		T218	10		T231	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T215	4		T232	1		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum , values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T206	10		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T207	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T34	3		T153	9		T209	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T3	13		T47	1		T37	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1338	1			T2	3		T8	3		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T4	1		T111	10		T155	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T23	1		T29	15		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T6	16		T37	2		T28	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T4	1		T152	1		T139	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T1	16		T211	1		T153	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	6		T35	2		T152	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T44	1		T36	3		T142	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T3	4		T152	1		T23	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T3	13		T7	14		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T48	9		T111	1		T140	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T35	3		T46	14		T165	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T4	1		T36	2		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T211	13		T140	9		T84	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	380	1			T5	10		T9	2		T48	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T111	11		T213	1		T28	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16058	1			T6	2		T34	45		T41	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T206	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T207	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T34	1		T153	7		T222	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T3	10		T47	9		T155	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1322	1			T8	32		T10	38		T42	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T111	12		T140	9		T217	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T29	17		T39	1		T210	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T6	5		T37	1		T28	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T152	13		T13	1		T227	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T1	10		T211	6		T145	21
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T35	1		T152	3		T166	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T36	1		T204	13		T233	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T3	4		T152	12		T223	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T3	10		T145	12		T12	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T48	7		T111	7		T140	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T145	21		T28	16		T234	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T191	9		T97	2		T207	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T211	11		T140	10		T84	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T48	10		T34	2		T35	23
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T111	11		T213	13		T28	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20737

1

T1

16

T2

3

T3

30

auto[1]

auto[0]

3800

1

T1

10

T3

24

T6

5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24537

1

T1

26

T2

3

T3

54

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21225

1

T2

3

T3

31

T4

3

auto[ADC_CTRL_FILTER_COND_OUT]

3312

1

T1

26

T3

23

T5

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18788

1

T3

54

T4

1

T6

2

auto[1]

5749

1

T1

26

T2

3

T4

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20769

1

T1

11

T2

3

T3

27

auto[1]

3768

1

T1

15

T3

27

T5

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	18	1			T235	10		T180	8		-	-
values[0]	62	1			T223	11		T151	11		T236	11
values[1]	702	1			T7	6		T48	16		T37	3
values[2]	552	1			T137	6		T23	1		T27	7
values[3]	700	1			T4	1		T47	10		T34	4
values[4]	659	1			T7	14		T40	18		T36	4
values[5]	2846	1			T2	3		T8	35		T10	41
values[6]	723	1			T3	54		T5	10		T6	21
values[7]	536	1			T1	26		T4	1		T48	23
values[8]	577	1			T9	2		T40	1		T111	8
values[9]	1104	1			T4	1		T35	5		T111	22
minimum	16058	1			T6	2		T34	45		T41	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	933	1			T7	6		T48	16		T37	3
values[1]	545	1			T152	4		T155	2		T137	6
values[2]	675	1			T4	1		T47	10		T34	4
values[3]	2949	1			T2	3		T7	14		T8	35
values[4]	557	1			T3	46		T44	1		T36	2
values[5]	656	1			T3	8		T4	1		T5	10
values[6]	647	1			T1	26		T34	7		T40	1
values[7]	645	1			T9	2		T111	22		T12	8
values[8]	675	1			T4	1		T35	5		T145	22
values[9]	186	1			T213	14		T228	32		T207	12
minimum	16069	1			T6	2		T34	45		T41	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20737

1

T1

16

T2

3

T3

30

auto[1]

3800

1

T1

10

T3

24

T6

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T48	8		T165	1		T223	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T7	1		T37	2		T142	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T27	1		T49	9		T38	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T152	4		T155	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T4	1		T47	10		T34	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T40	1		T23	1		T204	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1633	1			T2	3		T8	35		T10	41
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	1		T211	12		T190	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T3	11		T152	13		T142	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T3	11		T44	1		T36	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T3	5		T4	1		T6	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T5	1		T48	11		T155	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T35	26		T111	8		T211	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T1	11		T34	5		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T9	1		T111	12		T12	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T28	17		T149	4		T237	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T4	1		T35	3		T145	22
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T139	1		T217	12		T14	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T207	12		T238	16		T17	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T213	14		T228	17		T175	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15917	1			T34	44		T41	20		T35	332
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T48	8		T165	7		T223	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T7	5		T37	1		T142	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T27	6		T49	8		T38	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T155	1		T137	5		T29	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T34	2		T216	3		T239	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T40	17		T204	4		T240	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	937	1			T36	1		T153	8		T174	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T7	13		T211	12		T206	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T3	12		T142	8		T27	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T3	12		T46	8		T241	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T3	3		T6	15		T46	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T5	9		T48	12		T155	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T35	19		T211	6		T140	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T1	15		T34	2		T35	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T9	1		T111	10		T12	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T28	10		T149	2		T84	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T35	2		T49	5		T148	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T217	13		T14	2		T242	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T17	1		T187	12		T179	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T228	15		T243	11		T244	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	2		T34	1		T35	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T235	6		T180	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T223	3		T151	7		T245	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T236	6		T246	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T48	8		T165	1		T15	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T7	1		T37	2		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T27	1		T38	3		T247	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T137	1		T23	1		T29	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T4	1		T47	10		T34	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T152	4		T155	1		T204	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T36	3		T152	14		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T7	1		T40	1		T211	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1638	1			T2	3		T8	35		T10	41
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T44	1		T36	2		T46	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T3	16		T6	6		T46	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T3	11		T5	1		T142	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T4	1		T35	26		T140	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T1	11		T48	11		T34	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T9	1		T111	8		T211	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T40	1		T27	1		T28	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	331	1			T4	1		T35	3		T111	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T213	14		T139	1		T217	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15906	1			T34	44		T41	20		T35	332
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T235	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T223	8		T151	4		T245	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T236	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T48	8		T165	7		T15	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T7	5		T37	1		T142	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T27	6		T38	2		T248	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T137	5		T29	14		T233	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T34	2		T49	8		T239	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T155	1		T204	4		T97	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T36	1		T153	8		T49	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T7	13		T40	17		T211	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1008	1			T142	8		T174	20		T27	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T46	8		T242	12		T237	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T3	15		T6	15		T46	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T3	12		T5	9		T142	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T35	19		T140	8		T233	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T1	15		T48	12		T34	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T9	1		T211	6		T12	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T27	6		T28	10		T149	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T35	2		T111	10		T140	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T217	13		T14	2		T242	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	2		T34	1		T35	2