Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24537

1

T1

26

T2

3

T3

54

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21272

1

T1

26

T2

3

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3265

1

T3

54

T4

2

T5

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18867

1

T1

26

T3

31

T4

1

auto[1]

5670

1

T2

3

T3

23

T4

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20769

1

T1

11

T2

3

T3

27

auto[1]

3768

1

T1

15

T3

27

T5

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	26	1			T141	1		T244	14		T331	11
values[0]	61	1			T153	17		T254	15		T269	11
values[1]	502	1			T35	2		T165	8		T143	1
values[2]	594	1			T4	2		T5	10		T35	3
values[3]	520	1			T7	6		T48	16		T44	1
values[4]	2870	1			T2	3		T3	23		T4	1
values[5]	679	1			T40	1		T152	18		T142	2
values[6]	853	1			T1	26		T3	8		T40	18
values[7]	607	1			T3	23		T7	14		T47	10
values[8]	724	1			T48	23		T34	11		T111	8
values[9]	1043	1			T6	21		T9	2		T35	45
minimum	16058	1			T6	2		T34	45		T41	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	670	1			T4	1		T35	2		T111	22
values[1]	503	1			T4	1		T5	10		T35	3
values[2]	618	1			T4	1		T7	6		T48	16
values[3]	2853	1			T2	3		T3	23		T8	35
values[4]	810	1			T1	26		T3	8		T40	1
values[5]	632	1			T3	23		T35	3		T37	1
values[6]	677	1			T7	14		T47	10		T34	11
values[7]	800	1			T111	22		T155	32		T12	8
values[8]	762	1			T6	21		T9	2		T48	23
values[9]	104	1			T141	1		T242	13		T237	15
minimum	16108	1			T6	2		T34	45		T41	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20737

1

T1

16

T2

3

T3

30

auto[1]

3800

1

T1

10

T3

24

T6

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T143	1		T38	3		T257	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T4	1		T35	1		T111	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T4	1		T35	2		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T5	1		T166	14		T141	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T48	8		T36	2		T152	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T4	1		T7	1		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1630	1			T2	3		T8	35		T10	41
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T3	11		T152	14		T23	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T1	11		T152	4		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T3	5		T40	1		T49	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T35	2		T145	22		T137	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T3	11		T37	1		T28	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T7	1		T34	5		T40	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T47	10		T34	2		T140	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T111	13		T155	17		T12	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T27	1		T209	1		T189	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T6	6		T36	3		T37	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T9	1		T48	11		T35	26
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T141	1		T242	1		T325	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T237	5		T92	7		T98	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15908	1			T34	44		T41	20		T35	332
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T323	13		T245	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T38	2		T216	2		T289	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T35	1		T111	10		T165	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T35	1		T155	1		T14	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T5	9		T166	13		T267	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T48	8		T211	6		T27	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T7	5		T142	8		T211	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	948	1			T142	3		T174	20		T29	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T3	12		T136	5		T225	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T1	15		T182	12		T332	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T3	3		T49	5		T140	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T35	1		T137	5		T223	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T3	12		T28	9		T217	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T7	13		T34	2		T40	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T34	2		T140	8		T148	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T111	9		T155	15		T12	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T27	9		T209	2		T189	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T6	15		T36	1		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T9	1		T48	12		T35	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T242	12		-	-		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T237	10		T92	9		T274	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T6	2		T34	1		T35	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T323	14		T245	2		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T141	1		T244	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T331	9		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T153	1		T318	7		T333	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T254	15		T269	11		T334	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T143	1		T38	3		T257	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T35	1		T165	1		T287	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T4	1		T35	2		T36	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T4	1		T5	1		T111	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T48	8		T152	13		T155	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T7	1		T44	1		T142	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1643	1			T2	3		T8	35		T10	41
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T3	11		T4	1		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T152	4		T142	1		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T40	1		T152	14		T23	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T1	11		T40	1		T211	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T3	5		T37	1		T28	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T7	1		T35	2		T46	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T3	11		T47	10		T140	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T34	5		T111	8		T155	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T48	11		T34	2		T209	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T6	6		T36	3		T111	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T9	1		T35	26		T46	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15906	1			T34	44		T41	20		T35	332
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T244	13		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T331	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T153	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T334	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T38	2		T216	2		T289	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T35	1		T165	7		T306	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T35	1		T14	2		T221	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T5	9		T111	10		T229	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T48	8		T155	1		T211	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T7	5		T142	8		T211	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	911	1			T142	2		T174	20		T154	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T3	12		T226	12		T304	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T142	1		T137	5		T29	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T49	5		T190	2		T136	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T1	15		T40	17		T223	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T3	3		T28	9		T140	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T7	13		T35	1		T46	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T3	12		T140	8		T272	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T34	2		T155	15		T153	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T48	12		T34	2		T209	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T6	15		T36	1		T111	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T9	1		T35	19		T46	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	2		T34	1		T35	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T143	1		T38	5		T257	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T4	1		T35	2		T111	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T4	1		T35	2		T155	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T5	10		T166	14		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T48	9		T36	2		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T4	1		T7	6		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1289	1			T2	3		T8	3		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T3	13		T152	1		T23	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T1	16		T152	1		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T3	4		T40	1		T49	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T35	3		T145	1		T137	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T3	13		T37	1		T28	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T7	14		T34	5		T40	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T47	1		T34	3		T140	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T111	10		T155	16		T12	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T27	10		T209	3		T189	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T6	16		T36	3		T37	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T9	2		T48	13		T35	22
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T141	1		T242	13		T325	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T237	11		T92	10		T98	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16076	1			T6	2		T34	45		T41	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T323	15		T245	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T158	10		T326	2		T269	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T111	11		T229	13		T250	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T35	1		T145	21		T14	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T166	13		T141	4		T267	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T48	7		T152	12		T83	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T142	11		T211	11		T191	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1289	1			T8	32		T10	38		T42	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T3	10		T152	13		T136	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T1	10		T152	3		T213	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T3	4		T140	9		T206	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T145	21		T223	2		T210	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T3	10		T28	8		T217	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T34	2		T111	7		T153	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T47	9		T34	1		T140	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T111	12		T155	16		T12	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T15	1		T240	13		T156	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T6	5		T36	1		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T48	10		T35	23		T39	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T325	2		T329	1		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T237	4		T92	6		T274	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T323	12		T245	2		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T141	1		T244	14		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T331	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T153	17		T318	1		T333	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T254	1		T269	1		T334	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T143	1		T38	5		T257	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T35	2		T165	8		T287	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T4	1		T35	2		T36	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T4	1		T5	10		T111	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T48	9		T152	1		T155	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T7	6		T44	1		T142	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1244	1			T2	3		T8	3		T10	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T3	13		T4	1		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T152	1		T142	2		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T40	1		T152	1		T23	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T1	16		T40	18		T211	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T3	4		T37	1		T28	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T7	14		T35	3		T46	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T3	13		T47	1		T140	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T34	5		T111	1		T155	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T48	13		T34	3		T209	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T6	16		T36	3		T111	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T9	2		T35	22		T46	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16058	1			T6	2		T34	45		T41	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T331	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T318	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T254	14		T269	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T158	10		T270	4		T232	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T250	13		T330	13		T151	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T35	1		T145	21		T14	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T111	11		T141	4		T229	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T48	7		T152	12		T97	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T142	11		T211	11		T166	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1310	1			T8	32		T10	38		T42	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T3	10		T226	13		T279	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T152	3		T213	13		T145	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T152	13		T136	4		T206	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	10		T211	6		T145	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T3	4		T28	8		T140	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T28	12		T49	8		T93	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T3	10		T47	9		T140	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T34	2		T111	7		T155	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T48	10		T34	1		T15	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T6	5		T36	1		T111	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T35	23		T39	1		T140	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20737

1

T1

16

T2

3

T3

30

auto[1]

auto[0]

3800

1

T1

10

T3

24

T6

5