Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24537

1

T1

26

T2

3

T3

54

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19301

1

T3

8

T4

2

T5

10

auto[ADC_CTRL_FILTER_COND_OUT]

5236

1

T1

26

T2

3

T3

46

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18637

1

T1

26

T3

46

T4

3

auto[1]

5900

1

T2

3

T3

8

T5

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20769

1

T1

11

T2

3

T3

27

auto[1]

3768

1

T1

15

T3

27

T5

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	25	1			T16	7		T297	17		T333	1
values[0]	29	1			T273	5		T101	15		T278	6
values[1]	517	1			T1	26		T4	1		T9	2
values[2]	757	1			T5	10		T152	14		T211	24
values[3]	522	1			T23	1		T28	18		T29	32
values[4]	525	1			T36	4		T142	7		T143	2
values[5]	587	1			T35	3		T23	1		T49	6
values[6]	475	1			T4	1		T34	4		T46	9
values[7]	896	1			T3	23		T4	1		T48	23
values[8]	740	1			T3	8		T48	16		T37	4
values[9]	3406	1			T2	3		T3	23		T6	21
minimum	16058	1			T6	2		T34	45		T41	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	742	1			T1	26		T4	1		T5	10
values[1]	2961	1			T2	3		T8	35		T10	41
values[2]	487	1			T142	2		T143	2		T28	18
values[3]	630	1			T36	4		T142	5		T12	8
values[4]	461	1			T213	14		T145	13		T23	1
values[5]	633	1			T4	1		T34	4		T35	3
values[6]	799	1			T3	23		T4	1		T34	7
values[7]	792	1			T3	31		T6	21		T48	39
values[8]	745	1			T7	20		T40	1		T35	2
values[9]	214	1			T111	8		T152	4		T147	1
minimum	16073	1			T6	2		T34	45		T41	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20737

1

T1

16

T2

3

T3

30

auto[1]

3800

1

T1

10

T3

24

T6

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T4	1		T5	1		T47	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T1	11		T9	1		T40	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T152	14		T211	12		T23	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1673	1			T2	3		T8	35		T10	41
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T83	12		T250	3		T93	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T142	1		T143	2		T28	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T142	3		T12	5		T136	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T36	3		T28	13		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T213	14		T23	1		T49	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T145	13		T13	4		T247	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T4	1		T34	2		T35	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T165	1		T143	1		T145	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T34	5		T35	26		T44	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T3	11		T4	1		T46	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T3	5		T6	6		T48	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T3	11		T138	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	2		T35	1		T36	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T40	1		T142	12		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T111	8		T152	4		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T236	1		T273	7		T17	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15912	1			T34	44		T41	20		T35	332
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T291	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T5	9		T140	9		T15	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T1	15		T9	1		T40	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T211	12		T189	11		T140	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	927	1			T174	20		T154	21		T140	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T83	2		T170	9		T281	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T142	1		T28	9		T29	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T142	2		T12	3		T136	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T36	1		T28	14		T148	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T49	5		T39	3		T15	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T282	12		T264	10		T332	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T34	2		T35	1		T46	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T165	7		T208	11		T168	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T34	2		T35	19		T211	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T3	12		T46	13		T111	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T3	3		T6	15		T48	20
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T3	12		T138	9		T141	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T7	18		T35	1		T155	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T142	8		T153	16		T204	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T283	2		T284	4		T335	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T236	7		T179	10		T268	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T6	2		T34	1		T35	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T291	2		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T333	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T16	4		T297	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T273	5		T101	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T278	6		T336	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T4	1		T47	10		T140	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T1	11		T9	1		T40	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T5	1		T152	14		T211	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T145	22		T140	11		T287	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T23	1		T189	1		T212	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T28	9		T29	18		T217	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T142	3		T12	5		T39	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T36	3		T142	1		T143	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T35	2		T23	1		T49	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T13	4		T247	1		T210	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T4	1		T34	2		T46	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T165	1		T143	1		T145	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T48	11		T34	5		T35	26
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T3	11		T4	1		T46	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T3	5		T48	8		T37	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T155	1		T139	1		T217	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	338	1			T6	6		T7	2		T35	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1740	1			T2	3		T3	11		T8	35
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15906	1			T34	44		T41	20		T35	332
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T16	3		T297	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T101	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T336	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T140	9		T15	1		T206	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T1	15		T9	1		T40	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T5	9		T211	12		T140	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T140	8		T253	11		T87	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T189	11		T212	9		T97	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T28	9		T29	14		T217	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T142	2		T12	3		T39	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T36	1		T142	1		T28	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T35	1		T49	5		T15	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T148	5		T282	12		T264	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T34	2		T46	8		T49	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T165	7		T289	9		T17	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T48	12		T34	2		T35	19
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T3	12		T46	13		T111	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T3	3		T48	8		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T155	1		T217	13		T229	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T6	15		T7	18		T35	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1089	1			T3	12		T142	8		T153	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	2		T34	1		T35	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T4	1		T5	10		T47	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T1	16		T9	2		T40	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T152	1		T211	13		T23	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1270	1			T2	3		T8	3		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T83	3		T250	1		T93	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T142	2		T143	2		T28	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T142	3		T12	7		T136	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T36	3		T28	15		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T213	1		T23	1		T49	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T145	1		T13	3		T247	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T4	1		T34	3		T35	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T165	8		T143	1		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T34	5		T35	22		T44	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T3	13		T4	1		T46	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T3	4		T6	16		T48	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T3	13		T138	10		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T7	20		T35	2		T36	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T40	1		T142	9		T153	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T111	1		T152	1		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T236	8		T273	1		T17	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16063	1			T6	2		T34	45		T41	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T291	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T47	9		T140	9		T15	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T1	10		T35	1		T224	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T152	13		T211	11		T140	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1330	1			T8	32		T10	38		T42	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T83	11		T250	2		T93	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T28	8		T29	17		T217	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T142	2		T12	1		T136	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T36	1		T28	12		T222	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T213	13		T39	1		T223	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T145	12		T13	1		T210	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T34	1		T49	12		T241	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T145	21		T289	9		T292	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T34	2		T35	23		T152	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T3	10		T111	12		T14	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T3	4		T6	5		T48	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T3	10		T230	4		T229	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T155	16		T211	6		T153	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T142	11		T204	13		T217	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T111	7		T152	3		T227	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T273	6		T179	9		T268	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T235	5		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T291	2		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T333	1		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T16	4		T297	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T273	1		T101	9		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T278	1		T336	3		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T4	1		T47	1		T140	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T1	16		T9	2		T40	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T5	10		T152	1		T211	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T145	1		T140	9		T287	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T23	1		T189	12		T212	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T28	10		T29	15		T217	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T142	3		T12	7		T39	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T36	3		T142	2		T143	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T35	3		T23	1		T49	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T13	3		T247	1		T210	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T4	1		T34	3		T46	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T165	8		T143	1		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T48	13		T34	5		T35	22
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T3	13		T4	1		T46	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	275	1			T3	4		T48	9		T37	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T155	2		T139	1		T217	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	308	1			T6	16		T7	20		T35	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1452	1			T2	3		T3	13		T8	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16058	1			T6	2		T34	45		T41	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T16	3		T297	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T273	4		T101	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T278	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T47	9		T140	9		T15	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T1	10		T35	1		T224	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T152	13		T211	11		T140	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T145	21		T140	10		T253	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T250	2		T97	2		T254	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T28	8		T29	17		T217	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T142	2		T12	1		T39	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T36	1		T28	12		T210	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T15	1		T136	4		T330	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T13	1		T210	9		T282	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T34	1		T213	13		T49	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T145	12		T289	9		T248	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T48	10		T34	2		T35	23
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T3	10		T111	12		T145	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	4		T48	7		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T217	11		T230	4		T229	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T6	5		T111	18		T152	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1377	1			T3	10		T8	32		T10	38

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20737

1

T1

16

T2

3

T3

30

auto[1]

auto[0]

3800

1

T1

10

T3

24

T6

5