Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24537

1

T1

26

T2

3

T3

54

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21321

1

T1

26

T2

3

T3

23

auto[ADC_CTRL_FILTER_COND_OUT]

3216

1

T3

31

T4

1

T5

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18873

1

T5

10

T6

23

T7

6

auto[1]

5664

1

T1

26

T2

3

T3

54

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20769

1

T1

11

T2

3

T3

27

auto[1]

3768

1

T1

15

T3

27

T5

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	367	1			T48	23		T37	3		T152	18
values[0]	47	1			T136	15		T296	3		T303	11
values[1]	920	1			T3	23		T4	2		T5	10
values[2]	540	1			T3	23		T48	16		T34	4
values[3]	637	1			T7	20		T46	14		T142	5
values[4]	654	1			T1	26		T6	21		T9	2
values[5]	453	1			T27	10		T189	12		T39	10
values[6]	496	1			T111	22		T143	1		T153	17
values[7]	628	1			T3	8		T35	5		T211	24
values[8]	2972	1			T2	3		T4	1		T8	35
values[9]	765	1			T35	3		T36	4		T46	9
minimum	16058	1			T6	2		T34	45		T41	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	898	1			T3	46		T4	1		T5	10
values[1]	554	1			T48	16		T34	4		T40	1
values[2]	622	1			T7	20		T46	14		T142	5
values[3]	682	1			T1	26		T6	21		T9	2
values[4]	482	1			T111	22		T143	1		T153	17
values[5]	420	1			T35	3		T211	24		T29	32
values[6]	3053	1			T2	3		T3	8		T8	35
values[7]	536	1			T4	1		T34	7		T37	1
values[8]	874	1			T48	23		T35	3		T36	4
values[9]	157	1			T152	4		T143	1		T153	16
minimum	16259	1			T4	1		T6	2		T34	45

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20737

1

T1

16

T2

3

T3

30

auto[1]

3800

1

T1

10

T3

24

T6

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T3	11		T4	1		T142	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T3	11		T5	1		T40	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T23	1		T146	1		T217	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T48	8		T34	2		T40	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T7	1		T46	1		T142	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T7	1		T49	9		T210	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T1	11		T9	1		T142	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T6	6		T189	2		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T111	13		T153	1		T266	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T143	1		T145	13		T27	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T211	12		T253	14		T337	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T35	2		T29	18		T274	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1694	1			T2	3		T8	35		T10	41
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T3	5		T35	1		T44	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T4	1		T34	5		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T155	1		T223	3		T190	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T37	2		T165	1		T211	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T48	11		T35	2		T36	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T152	4		T241	1		T249	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T143	1		T153	8		T12	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15971	1			T34	44		T41	20		T35	332
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T4	1		T140	14		T148	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T3	12		T142	1		T14	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T3	12		T5	9		T40	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T217	13		T233	12		T225	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T48	8		T34	2		T137	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T7	5		T46	13		T142	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T7	13		T49	8		T234	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T1	15		T9	1		T142	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T6	15		T189	11		T140	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T111	9		T153	16		T182	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T27	9		T39	3		T282	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T211	12		T253	11		T151	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T35	1		T29	14		T274	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	974	1			T111	10		T174	20		T28	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T3	3		T35	1		T155	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T34	2		T233	1		T97	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T155	1		T223	8		T221	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T37	1		T165	7		T211	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T48	12		T35	1		T36	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T241	15		T161	4		T293	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T153	8		T12	3		T15	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T6	2		T34	1		T35	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T140	11		T148	5		T305	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T37	2		T152	4		T28	17
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T48	11		T152	14		T143	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T136	10		T296	1		T303	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T298	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T4	1		T142	1		T204	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T3	11		T4	1		T5	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T3	11		T146	1		T217	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T48	8		T34	2		T40	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T7	1		T46	1		T142	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T7	1		T139	1		T210	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T1	11		T9	1		T142	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T6	6		T49	9		T189	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T266	1		T216	1		T93	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T27	1		T189	1		T39	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T111	13		T153	1		T253	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T143	1		T145	13		T282	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T211	12		T145	22		T28	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T3	5		T35	3		T29	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1658	1			T2	3		T4	1		T8	35
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T44	1		T152	13		T155	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T165	1		T211	1		T23	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T35	2		T36	3		T46	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15906	1			T34	44		T41	20		T35	332
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T37	1		T28	10		T241	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T48	12		T12	3		T92	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T136	5		T296	2		T303	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T142	1		T204	4		T14	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T3	12		T5	9		T40	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T3	12		T217	13		T233	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T48	8		T34	2		T137	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T7	5		T46	13		T142	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T7	13		T234	14		T242	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T1	15		T9	1		T142	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T6	15		T49	8		T140	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T216	3		T260	9		T304	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T27	9		T189	11		T39	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T111	9		T153	16		T253	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T282	1		T274	1		T304	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T211	12		T28	9		T209	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T3	3		T35	2		T29	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	966	1			T34	2		T111	10		T174	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T155	15		T221	15		T97	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T165	7		T211	6		T49	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T35	1		T36	1		T46	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	2		T34	1		T35	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T3	13		T4	1		T142	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	313	1			T3	13		T5	10		T40	18
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T23	1		T146	1		T217	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T48	9		T34	3		T40	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T7	6		T46	14		T142	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T7	14		T49	9		T210	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T1	16		T9	2		T142	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T6	16		T189	13		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T111	10		T153	17		T266	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T143	1		T145	1		T27	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T211	13		T253	12		T337	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T35	3		T29	15		T274	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1321	1			T2	3		T8	3		T10	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T3	4		T35	2		T44	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T4	1		T34	5		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T155	2		T223	9		T190	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T37	2		T165	8		T211	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T48	13		T35	2		T36	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T152	1		T241	16		T249	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T143	1		T153	9		T12	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16122	1			T6	2		T34	45		T41	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T4	1		T140	12		T148	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T3	10		T14	1		T233	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	10		T35	23		T229	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T217	11		T233	12		T225	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T48	7		T34	1		T111	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T142	2		T28	12		T230	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T49	8		T210	14		T234	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T1	10		T142	11		T145	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T6	5		T140	9		T223	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T111	12		T182	5		T93	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T145	12		T39	1		T157	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T211	11		T253	13		T151	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T29	17		T274	1		T338	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1347	1			T8	32		T10	38		T47	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T3	4		T152	12		T155	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T34	2		T211	6		T292	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T223	2		T182	11		T267	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T37	1		T28	16		T49	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T48	10		T35	1		T36	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T152	3		T249	12		T275	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T153	7		T12	1		T15	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T204	13		T136	4		T167	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	45	1			T140	13		T305	2		T18	7

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T37	2		T152	1		T28	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T48	13		T152	1		T143	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T136	11		T296	3		T303	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T298	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T4	1		T142	2		T204	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T3	13		T4	1		T5	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T3	13		T146	1		T217	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T48	9		T34	3		T40	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T7	6		T46	14		T142	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T7	14		T139	1		T210	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T1	16		T9	2		T142	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T6	16		T49	9		T189	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T266	1		T216	4		T93	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T27	10		T189	12		T39	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T111	10		T153	17		T253	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T143	1		T145	1		T282	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T211	13		T145	1		T28	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T3	4		T35	5		T29	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1312	1			T2	3		T4	1		T8	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T44	1		T152	1		T155	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T165	8		T211	7		T23	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T35	2		T36	3		T46	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16058	1			T6	2		T34	45		T41	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T37	1		T152	3		T28	16
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T48	10		T152	13		T213	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T136	4		T303	3		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T298	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T204	13		T14	1		T233	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T3	10		T35	23		T140	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T3	10		T217	11		T233	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T48	7		T34	1		T111	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T142	2		T28	12		T250	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T210	14		T234	20		T237	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T1	10		T142	11		T145	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T6	5		T49	8		T140	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T93	10		T207	17		T256	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T39	1		T254	14		T157	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T111	12		T253	13		T182	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T145	12		T274	1		T289	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T211	11		T145	21		T28	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T3	4		T29	17		T15	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1312	1			T8	32		T10	38		T47	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T152	12		T155	16		T267	18
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T49	12		T13	1		T240	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T35	1		T36	1		T153	7

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20737

1

T1

16

T2

3

T3

30

auto[1]

auto[0]

3800

1

T1

10

T3

24

T6

5