Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24537

1

T1

26

T2

3

T3

54

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21242

1

T2

3

T3

8

T4

2

auto[ADC_CTRL_FILTER_COND_OUT]

3295

1

T1

26

T3

46

T4

1

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18937

1

T3

31

T4

2

T5

10

auto[1]

5600

1

T1

26

T2

3

T3

23

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20769

1

T1

11

T2

3

T3

27

auto[1]

3768

1

T1

15

T3

27

T5

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	231	1			T5	10		T35	47		T111	22
values[0]	44	1			T47	10		T242	3		T330	31
values[1]	625	1			T3	23		T34	4		T37	1
values[2]	2980	1			T2	3		T4	1		T8	35
values[3]	535	1			T6	21		T37	3		T23	1
values[4]	584	1			T1	26		T44	1		T36	4
values[5]	641	1			T4	1		T7	6		T35	3
values[6]	623	1			T3	31		T7	14		T40	1
values[7]	829	1			T48	16		T35	3		T46	14
values[8]	549	1			T4	1		T36	2		T142	20
values[9]	838	1			T9	2		T48	23		T34	7
minimum	16058	1			T6	2		T34	45		T41	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	593	1			T4	1		T37	1		T155	32
values[1]	2984	1			T2	3		T6	21		T8	35
values[2]	545	1			T37	3		T152	14		T23	1
values[3]	606	1			T1	26		T44	1		T36	4
values[4]	643	1			T3	8		T4	1		T7	6
values[5]	666	1			T3	23		T7	14		T111	8
values[6]	699	1			T48	16		T35	3		T46	14
values[7]	600	1			T4	1		T48	23		T40	18
values[8]	818	1			T9	2		T34	7		T35	47
values[9]	96	1			T5	10		T38	5		T208	12
minimum	16287	1			T3	23		T6	2		T47	10

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20737

1

T1

16

T2

3

T3

30

auto[1]

3800

1

T1

10

T3

24

T6

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T153	8		T209	1		T257	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T4	1		T37	1		T155	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1626	1			T2	3		T8	35		T10	41
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T6	6		T111	13		T155	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T152	14		T23	1		T210	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T37	2		T28	9		T39	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T152	4		T23	1		T166	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T1	11		T44	1		T36	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T3	5		T4	1		T7	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T40	1		T143	1		T211	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T111	8		T152	13		T23	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T3	11		T7	1		T12	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T48	8		T137	1		T221	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T35	2		T46	1		T165	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T4	1		T48	11		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T211	12		T141	1		T84	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T9	1		T34	5		T35	27
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T111	12		T213	14		T28	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T5	1		T38	3		T287	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T208	1		T341	1		T214	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15964	1			T34	46		T41	20		T35	332
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T3	11		T47	10		T247	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T153	8		T209	2		T83	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T155	15		T49	13		T136	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	982	1			T174	20		T29	14		T154	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T6	15		T111	9		T155	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T83	12		T182	12		T274	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T37	1		T28	9		T39	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T166	13		T141	7		T216	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T1	15		T36	1		T142	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T3	3		T7	5		T35	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T211	6		T27	15		T138	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T140	11		T190	2		T97	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	12		T7	13		T12	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T48	8		T137	5		T221	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T35	1		T46	13		T165	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T48	12		T40	17		T142	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T211	12		T84	11		T236	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T9	1		T34	2		T35	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T111	10		T28	14		T49	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T5	9		T38	2		T342	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T208	11		T214	2		T215	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T6	2		T34	3		T35	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T3	12		T272	7		T330	17

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T5	1		T35	27		T143	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T111	12		T206	12		T87	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T242	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T47	10		T330	14		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T34	2		T153	8		T209	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T3	11		T37	1		T49	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1651	1			T2	3		T8	35		T10	41
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T4	1		T111	13		T155	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T23	1		T29	18		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T6	6		T37	2		T28	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T152	14		T139	1		T13	4
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T1	11		T44	1		T36	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T4	1		T7	1		T35	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T143	1		T145	22		T27	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T3	5		T111	8		T152	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T3	11		T7	1		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T48	8		T140	14		T210	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T35	2		T46	1		T165	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T4	1		T36	2		T142	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T211	12		T140	11		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T9	1		T48	11		T34	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T213	14		T28	13		T49	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15906	1			T34	44		T41	20		T35	332
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T5	9		T35	20		T179	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T111	10		T206	9		T87	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T242	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T330	17		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T34	2		T153	8		T209	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T3	12		T49	13		T136	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	984	1			T174	20		T154	21		T219	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T111	9		T155	16		T27	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T29	14		T83	12		T306	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T6	15		T37	1		T28	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T216	3		T182	12		T220	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T1	15		T36	1		T142	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T7	5		T35	1		T166	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T27	9		T204	4		T217	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T3	3		T190	2		T151	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T3	12		T7	13		T211	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T48	8		T140	11		T221	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T35	1		T46	13		T165	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T142	8		T137	5		T191	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T211	12		T140	8		T84	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T9	1		T48	12		T34	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T28	14		T49	1		T272	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	2		T34	1		T35	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T153	9		T209	3		T257	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T4	1		T37	1		T155	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1313	1			T2	3		T8	3		T10	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T6	16		T111	10		T155	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T152	1		T23	1		T210	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T37	2		T28	10		T39	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T152	1		T23	1		T166	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T1	16		T44	1		T36	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T3	4		T4	1		T7	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T40	1		T143	1		T211	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T111	1		T152	1		T23	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T3	13		T7	14		T12	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T48	9		T137	6		T221	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T35	3		T46	14		T165	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T4	1		T48	13		T40	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T211	13		T141	1		T84	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	289	1			T9	2		T34	5		T35	24
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T111	11		T213	1		T28	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T5	10		T38	5		T287	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T208	12		T341	1		T214	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16097	1			T6	2		T34	48		T41	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T3	13		T47	1		T247	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T153	7		T83	11		T309	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T155	16		T49	8		T136	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1295	1			T8	32		T10	38		T42	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T6	5		T111	12		T140	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T152	13		T210	1		T83	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T37	1		T28	8		T39	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T152	3		T166	13		T13	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T1	10		T36	1		T211	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T3	4		T35	1		T15	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T145	12		T204	13		T225	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T111	7		T152	12		T140	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T3	10		T12	1		T225	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T48	7		T227	9		T228	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T145	21		T28	16		T140	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T48	10		T142	13		T229	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T211	11		T84	9		T93	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T34	2		T35	23		T230	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T111	11		T213	13		T28	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T167	2		T343	3		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T215	4		T232	1		T231	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T34	1		T222	11		T275	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T3	10		T47	9		T272	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T5	10		T35	24		T143	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T111	11		T206	10		T87	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T242	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T47	1		T330	18		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T34	3		T153	9		T209	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T3	13		T37	1		T49	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T2	3		T8	3		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T4	1		T111	10		T155	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T23	1		T29	15		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T6	16		T37	2		T28	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T152	1		T139	1		T13	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T1	16		T44	1		T36	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T4	1		T7	6		T35	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T143	1		T145	1		T27	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T3	4		T111	1		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T3	13		T7	14		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T48	9		T140	12		T210	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T35	3		T46	14		T165	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T4	1		T36	2		T142	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T211	13		T140	9		T141	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T9	2		T48	13		T34	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T213	1		T28	15		T49	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16058	1			T6	2		T34	45		T41	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T35	23		T256	9		T318	7
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T111	11		T206	11		T87	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T47	9		T330	13		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T34	1		T153	7		T222	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T3	10		T49	8		T136	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1311	1			T8	32		T10	38		T42	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T111	12		T155	16		T140	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T29	17		T210	1		T83	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	87	1			T6	5		T37	1		T28	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T152	13		T13	1		T227	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T1	10		T36	1		T211	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T35	1		T152	3		T166	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T145	21		T204	13		T217	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	90	1			T3	4		T111	7		T152	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T3	10		T145	12		T12	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T48	7		T140	13		T210	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T145	21		T28	16		T234	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T142	11		T191	9		T97	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T211	11		T140	10		T84	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T48	10		T34	2		T142	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T213	13		T28	12		T49	12

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20737

1

T1

16

T2

3

T3

30

auto[1]

auto[0]

3800

1

T1

10

T3

24

T6

5