Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24537

1

T1

26

T2

3

T3

54

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21683

1

T1

26

T2

3

T3

31

auto[ADC_CTRL_FILTER_COND_OUT]

2854

1

T3

23

T4

1

T5

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18663

1

T1

26

T3

8

T4

2

auto[1]

5874

1

T2

3

T3

46

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20769

1

T1

11

T2

3

T3

27

auto[1]

3768

1

T1

15

T3

27

T5

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	658	1			T34	1		T35	12		T43	4
values[0]	53	1			T269	9		T270	11		T110	11
values[1]	830	1			T1	26		T3	23		T5	10
values[2]	2972	1			T2	3		T8	35		T10	41
values[3]	523	1			T4	1		T142	5		T211	24
values[4]	438	1			T47	10		T44	1		T213	14
values[5]	683	1			T3	8		T4	1		T35	3
values[6]	448	1			T7	6		T35	3		T46	23
values[7]	620	1			T35	45		T152	31		T142	2
values[8]	507	1			T9	2		T40	1		T36	4
values[9]	1155	1			T3	23		T4	1		T7	14
minimum	15650	1			T6	2		T34	44		T41	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	834	1			T1	26		T3	23		T6	21
values[1]	2908	1			T2	3		T8	35		T10	41
values[2]	506	1			T4	1		T213	14		T211	24
values[3]	588	1			T3	8		T47	10		T35	3
values[4]	514	1			T4	1		T46	14		T165	8
values[5]	559	1			T7	6		T35	48		T46	9
values[6]	561	1			T152	17		T142	2		T143	1
values[7]	523	1			T9	2		T40	1		T36	4
values[8]	1114	1			T3	23		T4	1		T7	14
values[9]	131	1			T190	1		T208	12		T254	15
minimum	16299	1			T5	10		T6	2		T34	52

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20737

1

T1

16

T2

3

T3

30

auto[1]

3800

1

T1

10

T3

24

T6

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T1	11		T34	2		T36	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T3	11		T6	6		T48	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1643	1			T2	3		T8	35		T10	41
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T111	12		T142	3		T257	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T4	1		T213	14		T211	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T14	5		T212	1		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T3	5		T47	10		T211	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T35	2		T44	1		T111	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T4	1		T139	1		T217	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T46	1		T165	1		T145	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T35	28		T23	1		T27	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T7	1		T46	1		T152	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T152	13		T142	1		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T152	4		T155	17		T242	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T9	1		T40	1		T36	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T266	1		T207	18		T260	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T3	11		T35	1		T37	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	348	1			T4	1		T7	1		T48	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T254	15		T160	1		T273	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T190	1		T208	1		T259	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15962	1			T34	49		T41	20		T35	332
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T5	1		T223	3		T282	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T1	15		T34	2		T27	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T3	12		T6	15		T48	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	963	1			T155	1		T153	8		T174	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T111	10		T142	2		T151	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T211	12		T28	14		T138	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T14	2		T212	9		T148	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T3	3		T211	6		T28	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T35	1		T190	2		T272	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T217	2		T221	15		T149	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T46	13		T165	7		T242	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T35	20		T27	9		T217	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T7	5		T46	8		T49	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T142	1		T12	3		T166	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T155	15		T242	8		T240	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T9	1		T36	1		T49	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T260	10		T168	2		T289	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T3	12		T35	1		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T7	13		T48	8		T40	17
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T160	11		T261	2		T231	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T208	11		T259	15		T248	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T6	2		T34	3		T35	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T5	9		T223	8		T282	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	468	1			T34	1		T35	11		T43	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T190	1		T141	1		T208	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T110	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T269	9		T270	8		T335	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T1	11		T34	5		T36	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T3	11		T5	1		T6	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1649	1			T2	3		T8	35		T10	41
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T111	12		T143	1		T140	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T4	1		T211	12		T23	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T142	3		T14	5		T216	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T47	10		T213	14		T28	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T44	1		T212	1		T148	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T3	5		T4	1		T211	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T35	2		T111	8		T145	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T35	2		T23	1		T27	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T7	1		T46	2		T165	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T35	26		T152	13		T142	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T152	18		T155	17		T242	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T9	1		T40	1		T36	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T240	14		T98	1		T249	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T3	11		T37	2		T142	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	342	1			T4	1		T7	1		T48	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15498	1			T34	43		T41	20		T35	322
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T35	1		T289	1		T261	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T208	11		T157	13		T170	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T110	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T270	3		T335	12		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T1	15		T34	2		T137	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T3	12		T5	9		T6	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	966	1			T34	2		T155	1		T153	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T111	10		T140	9		T151	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T211	12		T189	11		T140	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T142	2		T14	2		T216	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T28	14		T29	14		T138	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T212	9		T148	5		T272	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T3	3		T211	6		T28	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T35	1		T190	2		T242	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T35	1		T27	9		T217	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T7	5		T46	21		T165	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T35	19		T142	1		T12	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T155	15		T242	8		T97	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T9	1		T36	1		T166	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T240	14		T168	2		T17	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T3	12		T37	1		T142	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T7	13		T48	8		T40	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	2		T34	1		T35	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T1	16		T34	3		T36	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	299	1			T3	13		T6	16		T48	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1304	1			T2	3		T8	3		T10	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T111	11		T142	3		T257	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T4	1		T213	1		T211	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T14	6		T212	10		T148	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T3	4		T47	1		T211	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T35	2		T44	1		T111	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T4	1		T139	1		T217	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T46	14		T165	8		T145	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T35	25		T23	1		T27	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T7	6		T46	9		T152	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T152	1		T142	2		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T152	1		T155	16		T242	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T9	2		T40	1		T36	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T266	1		T207	1		T260	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T3	13		T35	2		T37	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	361	1			T4	1		T7	14		T48	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T254	1		T160	12		T273	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T190	1		T208	12		T259	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16134	1			T6	2		T34	50		T41	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T5	10		T223	9		T282	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T1	10		T34	1		T28	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T3	10		T6	5		T48	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1302	1			T8	32		T10	38		T42	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T111	11		T142	2		T227	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T213	13		T211	11		T28	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T14	1		T182	5		T267	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T3	4		T47	9		T28	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T35	1		T111	7		T210	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T217	2		T149	1		T229	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T145	21		T223	2		T83	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T35	23		T217	11		T233	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T152	13		T49	12		T136	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T152	12		T12	1		T166	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T152	3		T155	16		T240	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T36	1		T145	12		T204	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T207	17		T256	9		T289	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T3	10		T37	1		T142	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T48	7		T211	6		T140	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T254	14		T273	6		T231	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T248	11		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T34	2		T225	10		T92	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T223	2		T327	8		T270	4

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	466	1			T34	1		T35	12		T43	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	81	1			T190	1		T141	1		T208	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T110	8		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T269	1		T270	7		T335	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T1	16		T34	5		T36	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T3	13		T5	10		T6	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1311	1			T2	3		T8	3		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T111	11		T143	1		T140	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T4	1		T211	13		T23	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T142	3		T14	6		T216	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T47	1		T213	1		T28	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T44	1		T212	10		T148	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	299	1			T3	4		T4	1		T211	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T35	2		T111	1		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T35	3		T23	1		T27	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T7	6		T46	23		T165	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T35	22		T152	1		T142	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T152	2		T155	16		T242	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T9	2		T40	1		T36	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T240	15		T98	1		T249	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T3	13		T37	2		T142	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T4	1		T7	14		T48	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15650	1			T6	2		T34	44		T41	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T254	14		T273	6		T232	13
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	62	1			T157	12		T18	7		T324	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T110	3		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T269	8		T270	4		T335	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T1	10		T34	2		T28	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T3	10		T6	5		T48	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1304	1			T8	32		T10	38		T34	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T111	11		T140	9		T227	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T211	11		T140	10		T230	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T142	2		T14	1		T267	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T47	9		T213	13		T28	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T182	5		T167	11		T251	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T3	4		T28	8		T217	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T35	1		T111	7		T145	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T217	11		T182	1		T275	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T49	12		T136	4		T206	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T35	23		T152	12		T12	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T152	16		T155	16		T156	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T36	1		T145	12		T166	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	63	1			T240	13		T249	12		T344	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T3	10		T37	1		T142	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	282	1			T48	7		T211	6		T140	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20737

1

T1

16

T2

3

T3

30

auto[1]

auto[0]

3800

1

T1

10

T3

24

T6

5