Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24537

1

T1

26

T2

3

T3

54

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21198

1

T1

26

T2

3

T3

31

auto[ADC_CTRL_FILTER_COND_OUT]

3339

1

T3

23

T5

10

T7

20

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18811

1

T3

54

T4

2

T6

2

auto[1]

5726

1

T1

26

T2

3

T4

1

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20769

1

T1

11

T2

3

T3

27

auto[1]

3768

1

T1

15

T3

27

T5

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	233	1			T4	1		T35	2		T146	1
values[0]	51	1			T165	8		T151	11		T345	7
values[1]	711	1			T7	6		T48	16		T37	3
values[2]	558	1			T137	6		T27	7		T29	32
values[3]	703	1			T4	1		T47	10		T34	4
values[4]	631	1			T7	14		T40	18		T36	4
values[5]	2913	1			T2	3		T3	23		T8	35
values[6]	683	1			T3	31		T5	10		T6	21
values[7]	520	1			T1	26		T4	1		T48	23
values[8]	612	1			T9	2		T111	8		T37	1
values[9]	864	1			T35	3		T111	22		T213	14
minimum	16058	1			T6	2		T34	45		T41	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	571	1			T48	16		T37	3		T142	2
values[1]	599	1			T152	4		T155	2		T137	6
values[2]	653	1			T4	1		T47	10		T34	4
values[3]	2938	1			T2	3		T7	14		T8	35
values[4]	572	1			T3	46		T44	1		T36	2
values[5]	696	1			T3	8		T4	1		T5	10
values[6]	627	1			T1	26		T34	7		T40	1
values[7]	572	1			T9	2		T111	8		T12	8
values[8]	812	1			T4	1		T35	5		T111	22
values[9]	109	1			T287	1		T238	16		T169	1
minimum	16388	1			T6	2		T7	6		T34	45

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20737

1

T1

16

T2

3

T3

30

auto[1]

3800

1

T1

10

T3

24

T6

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T48	8		T223	3		T15	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T37	2		T142	1		T145	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T27	1		T49	9		T38	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T152	4		T155	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T4	1		T47	10		T34	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T40	1		T204	14		T240	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1610	1			T2	3		T8	35		T10	41
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T7	1		T211	12		T190	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T3	11		T152	13		T142	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T3	11		T44	1		T36	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T3	5		T4	1		T6	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T5	1		T48	11		T142	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T1	11		T40	1		T35	26
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T34	5		T35	2		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T9	1		T111	8		T12	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T28	17		T49	1		T237	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T4	1		T35	3		T111	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T213	14		T139	1		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T287	1		T169	1		T187	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T238	16		T161	1		T175	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15983	1			T34	44		T41	20		T35	332
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T7	1		T140	10		T272	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T48	8		T223	8		T15	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T37	1		T142	1		T28	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T27	6		T49	8		T38	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T155	1		T137	5		T29	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T34	2		T83	2		T216	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T40	17		T204	4		T240	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	925	1			T36	1		T153	8		T174	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T7	13		T211	12		T206	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T3	12		T142	8		T27	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T3	12		T46	8		T189	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T3	3		T6	15		T46	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T5	9		T48	12		T142	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T1	15		T35	19		T211	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T34	2		T35	1		T27	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T9	1		T12	3		T149	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T28	10		T49	5		T84	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T35	2		T111	10		T140	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T217	13		T14	2		T148	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T187	12		T179	10		T335	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T161	4		T243	11		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T6	2		T34	1		T35	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T7	5		T140	9		T272	7

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T4	1		T35	1		T13	4
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T146	1		T217	12		T14	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T165	1		T151	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T345	7		T346	10		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T48	8		T223	3		T15	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T7	1		T37	2		T142	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T27	1		T38	3		T247	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T137	1		T29	18		T266	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T4	1		T47	10		T34	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T152	4		T155	1		T204	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T36	3		T152	14		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T7	1		T40	1		T211	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1670	1			T2	3		T8	35		T10	41
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T3	11		T44	1		T36	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T3	16		T6	6		T46	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T5	1		T142	3		T23	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T1	11		T4	1		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T48	11		T34	5		T35	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T9	1		T111	8		T211	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T37	1		T27	1		T28	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T35	2		T111	12		T145	22
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T213	14		T139	1		T147	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15906	1			T34	44		T41	20		T35	332
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T35	1		T182	5		T92	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T217	13		T14	2		T148	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T165	7		T151	4		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T346	15		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T48	8		T223	8		T15	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T7	5		T37	1		T142	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T27	6		T38	2		T347	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T137	5		T29	14		T233	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T34	2		T49	8		T239	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T155	1		T204	4		T97	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T36	1		T153	8		T49	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T7	13		T40	17		T211	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1021	1			T142	8		T174	20		T27	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T3	12		T46	8		T242	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T3	15		T6	15		T46	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T5	9		T142	2		T189	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T1	15		T35	19		T140	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T48	12		T34	2		T35	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T9	1		T211	6		T12	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T27	6		T28	10		T49	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T35	1		T111	10		T140	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T148	5		T242	2		T191	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	2		T34	1		T35	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T48	9		T223	9		T15	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T37	2		T142	2		T145	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T27	7		T49	9		T38	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T152	1		T155	2		T137	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T4	1		T47	1		T34	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T40	18		T204	5		T240	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1262	1			T2	3		T8	3		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T7	14		T211	13		T190	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T3	13		T152	1		T142	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T3	13		T44	1		T36	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T3	4		T4	1		T6	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T5	10		T48	13		T142	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T1	16		T40	1		T35	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T34	5		T35	2		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T9	2		T111	1		T12	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T28	11		T49	6		T237	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T4	1		T35	5		T111	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T213	1		T139	1		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T287	1		T169	1		T187	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T238	1		T161	5		T175	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16107	1			T6	2		T34	45		T41	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T7	6		T140	10		T272	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T48	7		T223	2		T15	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T37	1		T145	12		T28	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T49	8		T210	14		T249	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T152	3		T29	17		T233	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T47	9		T34	1		T145	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T204	13		T240	13		T97	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T8	32		T10	38		T42	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T211	11		T230	4		T206	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T3	10		T152	12		T142	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T3	10		T250	7		T93	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T3	4		T6	5		T111	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T48	10		T142	2		T155	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T1	10		T35	23		T157	19
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T34	2		T35	1		T217	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T111	7		T12	1		T210	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T28	16		T84	9		T227	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T111	11		T145	21		T140	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T213	13		T217	11		T14	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T179	9		T335	2		T348	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T238	15		T318	7		T349	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	68	1			T234	20		T151	6		T254	14
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T140	9		T272	12		T222	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T4	1		T35	2		T13	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T146	1		T217	14		T14	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T165	8		T151	5		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T345	1		T346	16		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T48	9		T223	9		T15	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T7	6		T37	2		T142	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T27	7		T38	5		T247	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T137	6		T29	15		T266	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T4	1		T47	1		T34	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T152	1		T155	2		T204	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T36	3		T152	1		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T7	14		T40	18		T211	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1363	1			T2	3		T8	3		T10	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T3	13		T44	1		T36	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T3	17		T6	16		T46	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T5	10		T142	3		T23	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T1	16		T4	1		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T48	13		T34	5		T35	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T9	2		T111	1		T211	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T37	1		T27	7		T28	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T35	3		T111	11		T145	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T213	1		T139	1		T147	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16058	1			T6	2		T34	45		T41	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T13	1		T182	5		T92	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T217	11		T14	1		T87	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T151	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T345	6		T346	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T48	7		T223	2		T15	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T37	1		T145	12		T28	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T210	14		T249	12		T248	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T29	17		T233	12		T253	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T47	9		T34	1		T49	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T152	3		T204	13		T97	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T36	1		T152	13		T153	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T211	11		T206	11		T240	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1328	1			T8	32		T10	38		T42	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T3	10		T230	4		T237	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T3	14		T6	5		T111	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T142	2		T39	1		T233	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T1	10		T35	23		T140	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T48	10		T34	2		T35	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T111	7		T12	1		T141	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T28	16		T84	9		T227	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T111	11		T145	21		T140	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T213	13		T191	9		T182	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20737

1

T1

16

T2

3

T3

30

auto[1]

auto[0]

3800

1

T1

10

T3

24

T6

5