Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T48	9		T165	8		T223	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T7	6		T37	2		T142	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T27	7		T49	9		T38	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T152	1		T155	2		T137	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T4	1		T47	1		T34	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T40	18		T23	1		T204	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1273	1			T2	3		T8	3		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T7	14		T211	13		T190	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T3	13		T152	1		T142	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T3	13		T44	1		T36	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T3	4		T4	1		T6	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T5	10		T48	13		T155	16
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T35	22		T111	1		T211	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T1	16		T34	5		T40	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T9	2		T111	11		T12	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T28	11		T149	5		T237	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T4	1		T35	5		T145	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T139	1		T217	14		T14	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T207	1		T238	1		T17	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T213	1		T228	16		T175	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16059	1			T6	2		T34	45		T41	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T48	7		T223	2		T15	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T37	1		T145	12		T28	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T49	8		T210	14		T249	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T152	3		T29	17		T233	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T47	9		T34	1		T239	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T204	13		T240	13		T97	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1297	1			T8	32		T10	38		T42	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T211	11		T230	4		T206	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T3	10		T152	12		T142	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T3	10		T250	7		T93	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T3	4		T6	5		T111	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T48	10		T155	16		T39	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T35	23		T111	7		T140	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T1	10		T34	2		T35	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T111	11		T12	1		T140	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T28	16		T149	1		T84	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T145	21		T13	1		T229	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T217	11		T14	1		T191	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T207	11		T238	15		T179	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T213	13		T228	16		T251	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T252	10		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T235	5		T180	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T223	9		T151	5		T245	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T236	6		T246	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T48	9		T165	8		T15	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T7	6		T37	2		T142	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T27	7		T38	5		T247	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T137	6		T23	1		T29	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T4	1		T47	1		T34	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T152	1		T155	2		T204	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T36	3		T152	1		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	277	1			T7	14		T40	18		T211	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1346	1			T2	3		T8	3		T10	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T44	1		T36	2		T46	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T3	17		T6	16		T46	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T3	13		T5	10		T142	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T4	1		T35	22		T140	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T1	16		T48	13		T34	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T9	2		T111	1		T211	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T40	1		T27	7		T28	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T4	1		T35	5		T111	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T213	1		T139	1		T217	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16058	1			T6	2		T34	45		T41	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T235	5		T180	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T223	2		T151	6		T245	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T236	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T48	7		T15	1		T136	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T37	1		T145	12		T28	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T210	14		T249	12		T248	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T29	17		T233	12		T253	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T47	9		T34	1		T49	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T152	3		T204	13		T97	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T36	1		T152	13		T211	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T211	11		T206	11		T240	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1300	1			T8	32		T10	38		T42	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T230	4		T237	4		T250	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T3	14		T6	5		T111	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T3	10		T142	2		T155	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T35	23		T140	10		T254	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T1	10		T48	10		T34	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T111	7		T12	1		T141	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T28	16		T149	1		T84	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T111	11		T145	21		T140	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T213	13		T217	11		T14	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20737

1

T1

16

T2

3

T3

30

auto[1]

auto[0]

3800

1

T1

10

T3

24

T6

5