Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24537

1

T1

26

T2

3

T3

54

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21642

1

T1

26

T2

3

T3

23

auto[ADC_CTRL_FILTER_COND_OUT]

2895

1

T3

31

T4

1

T5

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18931

1

T3

8

T4

3

T6

2

auto[1]

5606

1

T1

26

T2

3

T3

46

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20769

1

T1

11

T2

3

T3

27

auto[1]

3768

1

T1

15

T3

27

T5

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	49	1			T248	30		T255	12		T243	7
values[0]	14	1			T256	12		T18	2		-	-
values[1]	533	1			T3	23		T4	1		T35	3
values[2]	678	1			T40	18		T35	2		T44	1
values[3]	676	1			T3	8		T6	21		T40	1
values[4]	652	1			T9	2		T34	7		T36	4
values[5]	2960	1			T1	26		T2	3		T4	1
values[6]	485	1			T4	1		T48	23		T46	9
values[7]	624	1			T5	10		T7	20		T36	2
values[8]	731	1			T3	23		T47	10		T152	13
values[9]	1077	1			T48	16		T35	3		T142	7
minimum	16058	1			T6	2		T34	45		T41	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	665	1			T4	1		T35	3		T111	8
values[1]	713	1			T3	23		T40	18		T35	2
values[2]	720	1			T3	8		T6	21		T9	2
values[3]	2847	1			T2	3		T4	1		T8	35
values[4]	643	1			T1	26		T34	4		T35	45
values[5]	537	1			T4	1		T48	23		T36	2
values[6]	575	1			T5	10		T7	20		T37	3
values[7]	848	1			T3	23		T47	10		T35	3
values[8]	766	1			T48	16		T142	2		T211	31
values[9]	143	1			T209	3		T217	25		T14	7
minimum	16080	1			T6	2		T34	45		T41	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20737

1

T1

16

T2

3

T3

30

auto[1]

3800

1

T1

10

T3

24

T6

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T4	1		T142	12		T155	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T35	2		T111	8		T38	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T3	11		T40	1		T35	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T165	1		T12	5		T140	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T6	6		T9	1		T37	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T3	5		T40	1		T211	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1670	1			T2	3		T8	35		T10	41
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T4	1		T34	5		T36	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T1	11		T34	2		T35	26
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T111	13		T27	1		T257	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T4	1		T152	4		T210	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T48	11		T36	2		T28	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T7	1		T23	2		T27	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T5	1		T7	1		T37	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T47	10		T152	13		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T3	11		T35	2		T142	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T211	12		T145	13		T136	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T48	8		T142	1		T211	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T209	1		T217	12		T258	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T14	5		T259	1		T248	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15918	1			T34	44		T41	20		T35	332
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T142	8		T155	1		T153	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T35	1		T38	2		T140	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T3	12		T40	17		T35	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T165	7		T12	3		T140	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T6	15		T9	1		T140	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T3	3		T211	6		T28	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	987	1			T46	13		T174	20		T154	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T34	2		T36	1		T157	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T1	15		T34	2		T35	19
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T111	9		T27	6		T15	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T260	9		T261	2		T262	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T48	12		T28	10		T87	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T7	13		T27	9		T148	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T5	9		T7	5		T37	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T233	1		T240	14		T253	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T3	12		T35	1		T142	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T211	12		T136	5		T224	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T48	8		T142	1		T27	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T209	2		T217	13		T263	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T14	2		T259	15		T248	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T6	2		T34	1		T35	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T243	5		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T248	17		T255	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T256	12		T18	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T3	11		T4	1		T111	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T35	2		T111	8		T38	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T40	1		T35	1		T44	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T140	24		T206	12		T210	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T6	6		T143	2		T155	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T3	5		T40	1		T165	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T9	1		T46	1		T37	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T34	5		T36	3		T247	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1718	1			T1	11		T2	3		T8	35
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T4	1		T111	13		T257	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T4	1		T46	1		T213	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T48	11		T27	1		T28	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T7	1		T152	4		T23	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T5	1		T7	1		T36	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T47	10		T152	13		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T3	11		T28	9		T13	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	301	1			T211	12		T145	13		T209	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T48	8		T35	2		T142	4
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15906	1			T34	44		T41	20		T35	332
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T243	2		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T248	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T18	1		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T3	12		T111	10		T155	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T35	1		T38	2		T228	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T40	17		T35	1		T142	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T140	20		T206	9		T264	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T6	15		T155	15		T49	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T3	3		T165	7		T211	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T9	1		T46	13		T190	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T34	2		T36	1		T237	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1017	1			T1	15		T34	2		T35	19
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T111	9		T15	1		T160	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T46	8		T137	5		T151	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T48	12		T27	6		T28	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T7	13		T27	9		T240	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T5	9		T7	5		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T136	5		T233	1		T148	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T3	12		T28	9		T233	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T211	12		T209	2		T217	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T48	8		T35	1		T142	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	2		T34	1		T35	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T4	1		T142	9		T155	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T35	2		T111	1		T38	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T3	13		T40	18		T35	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T165	8		T12	7		T140	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T6	16		T9	2		T37	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T3	4		T40	1		T211	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1339	1			T2	3		T8	3		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T4	1		T34	5		T36	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T1	16		T34	3		T35	22
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T111	10		T27	7		T257	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T4	1		T152	1		T210	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T48	13		T36	2		T28	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T7	14		T23	2		T27	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T5	10		T7	6		T37	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T47	1		T152	1		T143	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T3	13		T35	3		T142	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T211	13		T145	1		T136	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T48	9		T142	2		T211	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T209	3		T217	14		T258	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T14	6		T259	16		T248	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16069	1			T6	2		T34	45		T41	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T142	11		T145	21		T49	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T35	1		T111	7		T140	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T3	10		T155	16		T153	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T12	1		T140	13		T206	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T6	5		T140	10		T84	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	4		T28	12		T166	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1318	1			T8	32		T10	38		T42	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T34	2		T36	1		T157	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T1	10		T34	1		T35	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T111	12		T15	1		T83	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T152	3		T210	14		T207	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T48	10		T28	16		T87	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T83	12		T241	14		T156	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T37	1		T29	17		T223	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T47	9		T152	12		T145	21
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T3	10		T142	2		T28	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T211	11		T145	12		T136	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T48	7		T211	6		T39	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T217	11		T263	16		T265	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T14	1		T248	16		T255	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T111	11		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T243	3		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T248	14		T255	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T256	1		T18	2		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T3	13		T4	1		T111	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T35	2		T111	1		T38	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T40	18		T35	2		T44	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T140	22		T206	10		T210	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T6	16		T143	2		T155	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T3	4		T40	1		T165	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T9	2		T46	14		T37	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T34	5		T36	3		T247	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1358	1			T1	16		T2	3		T8	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T4	1		T111	10		T257	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T4	1		T46	9		T213	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T48	13		T27	7		T28	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T7	14		T152	1		T23	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T5	10		T7	6		T36	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T47	1		T152	1		T143	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T3	13		T28	10		T13	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	354	1			T211	13		T145	1		T209	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T48	9		T35	3		T142	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16058	1			T6	2		T34	45		T41	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T243	4		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T248	16		T255	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T256	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T3	10		T111	11		T145	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T35	1		T111	7		T228	16
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T142	11		T153	7		T49	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T140	22		T206	11		T210	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T6	5		T155	16		T49	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T3	4		T12	1		T28	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T152	13		T15	1		T191	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T34	2		T36	1		T237	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1377	1			T1	10		T8	32		T10	38
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T111	12		T15	1		T227	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T213	13		T210	14		T151	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T48	10		T28	16		T83	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T152	3		T240	13		T241	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T37	1		T29	17		T223	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T47	9		T152	12		T145	21
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T3	10		T28	8		T13	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T211	11		T145	12		T217	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T48	7		T142	2		T211	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20737

1

T1

16

T2

3

T3

30

auto[1]

auto[0]

3800

1

T1

10

T3

24

T6

5