Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24537

1

T1

26

T2

3

T3

54

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21677

1

T1

26

T2

3

T3

31

auto[ADC_CTRL_FILTER_COND_OUT]

2860

1

T3

23

T4

1

T5

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18523

1

T1

26

T3

54

T4

2

auto[1]

6014

1

T2

3

T4

1

T6

21

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20769

1

T1

11

T2

3

T3

27

auto[1]

3768

1

T1

15

T3

27

T5

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	410	1			T34	1		T35	10		T43	4
values[0]	106	1			T27	7		T225	21		T92	16
values[1]	748	1			T1	26		T3	23		T5	10
values[2]	3008	1			T2	3		T8	35		T10	41
values[3]	470	1			T4	1		T142	5		T23	1
values[4]	496	1			T47	10		T44	1		T213	14
values[5]	744	1			T3	8		T4	1		T35	3
values[6]	429	1			T35	3		T46	9		T165	8
values[7]	519	1			T7	6		T35	45		T152	31
values[8]	567	1			T9	2		T40	1		T36	4
values[9]	1390	1			T3	23		T4	1		T7	14
minimum	15650	1			T6	2		T34	44		T41	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1032	1			T1	26		T3	23		T5	10
values[1]	2942	1			T2	3		T8	35		T10	41
values[2]	465	1			T4	1		T213	14		T211	24
values[3]	605	1			T3	8		T47	10		T35	3
values[4]	505	1			T4	1		T165	8		T145	22
values[5]	557	1			T7	6		T35	45		T46	23
values[6]	612	1			T9	2		T35	3		T152	17
values[7]	485	1			T40	1		T36	4		T37	1
values[8]	1066	1			T3	23		T4	1		T7	14
values[9]	178	1			T40	18		T190	1		T208	12
minimum	16090	1			T6	2		T34	45		T41	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20737

1

T1

16

T2

3

T3

30

auto[1]

3800

1

T1

10

T3

24

T6

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T1	11		T48	11		T34	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T3	11		T5	1		T6	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1586	1			T2	3		T8	35		T10	41
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T111	12		T155	1		T153	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T4	1		T211	12		T28	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T213	14		T138	1		T140	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T3	5		T28	9		T29	18
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T47	10		T35	2		T44	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T4	1		T139	1		T217	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T165	1		T145	22		T210	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T7	1		T35	26		T46	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T46	1		T152	14		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T35	2		T152	13		T142	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T9	1		T152	4		T155	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T40	1		T36	3		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T266	1		T224	11		T267	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	306	1			T3	11		T48	8		T35	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	283	1			T4	1		T7	1		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T208	1		T157	13		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T40	1		T190	1		T241	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15906	1			T34	44		T41	20		T35	332
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T268	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T1	15		T48	12		T34	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T3	12		T5	9		T6	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	940	1			T142	2		T174	20		T154	21
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T111	10		T155	1		T153	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T211	12		T28	14		T189	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T138	9		T140	8		T148	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T3	3		T28	9		T29	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T35	1		T211	6		T190	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T217	2		T242	12		T221	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T165	7		T226	12		T239	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T7	5		T35	19		T46	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T46	8		T136	5		T206	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T35	1		T142	1		T12	3
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T9	1		T155	15		T97	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T36	1		T49	5		T209	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T224	7		T267	12		T260	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T3	12		T48	8		T35	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T7	13		T153	16		T222	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T208	11		T157	13		T160	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T40	17		T241	15		T259	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	2		T34	1		T35	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T268	16		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	410	1			T34	1		T35	10		T43	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T27	1		T225	11		T269	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T92	7		T270	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T1	11		T48	11		T34	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T3	11		T5	1		T6	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1620	1			T2	3		T8	35		T10	41
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T111	12		T155	1		T153	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T4	1		T142	3		T23	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T140	11		T14	5		T230	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T211	12		T28	13		T29	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T47	10		T44	1		T213	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T3	5		T4	1		T46	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T35	2		T111	8		T211	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T35	2		T23	1		T27	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T46	1		T165	1		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T7	1		T35	26		T152	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T152	18		T97	1		T271	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T40	1		T36	3		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T9	1		T155	17		T98	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	419	1			T3	11		T48	8		T35	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	340	1			T4	1		T7	1		T40	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15498	1			T34	43		T41	20		T35	322
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T27	6		T225	10		T110	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T92	9		T270	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T1	15		T48	12		T34	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T3	12		T5	9		T6	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	956	1			T34	2		T174	20		T154	21
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T111	10		T155	1		T153	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T142	2		T189	11		T148	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T140	8		T14	2		T83	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T211	12		T28	14		T29	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T138	9		T148	5		T272	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T3	3		T46	13		T28	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T35	1		T211	6		T190	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T35	1		T27	9		T49	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T46	8		T165	7		T136	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T7	5		T35	19		T142	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T97	7		T271	11		T156	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T36	1		T142	8		T166	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T9	1		T155	15		T267	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	315	1			T3	12		T48	8		T35	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T7	13		T40	17		T153	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	2		T34	1		T35	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T1	16		T48	13		T34	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T3	13		T5	10		T6	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1277	1			T2	3		T8	3		T10	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T111	11		T155	2		T153	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T4	1		T211	13		T28	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T213	1		T138	10		T140	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T3	4		T28	10		T29	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T47	1		T35	2		T44	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T4	1		T139	1		T217	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T165	8		T145	1		T210	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T7	6		T35	22		T46	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T46	9		T152	1		T146	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T35	3		T152	1		T142	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T9	2		T152	1		T155	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T40	1		T36	3		T37	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T266	1		T224	8		T267	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T3	13		T48	9		T35	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T4	1		T7	14		T153	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	67	1			T208	12		T157	14		T159	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T40	18		T190	1		T241	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16058	1			T6	2		T34	45		T41	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T268	17		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T1	10		T48	10		T34	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T3	10		T6	5		T111	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1249	1			T8	32		T10	38		T42	6
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T111	11		T153	7		T14	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T211	11		T28	12		T182	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	84	1			T213	13		T140	10		T267	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T3	4		T28	8		T29	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T47	9		T35	1		T111	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T217	2		T149	1		T229	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T145	21		T210	14		T226	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T35	23		T49	12		T217	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T152	13		T136	4		T206	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T152	12		T12	1		T166	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T152	3		T155	16		T249	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T36	1		T145	12		T204	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T224	10		T267	10		T256	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T3	10		T48	7		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T222	11		T182	11		T241	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T157	12		T273	6		T231	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T248	11		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T268	15		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	410	1			T34	1		T35	10		T43	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T27	7		T225	11		T269	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T92	10		T270	7		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T1	16		T48	13		T34	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T3	13		T5	10		T6	16
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1301	1			T2	3		T8	3		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T111	11		T155	2		T153	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T4	1		T142	3		T23	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T140	9		T14	6		T230	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T211	13		T28	15		T29	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T47	1		T44	1		T213	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	285	1			T3	4		T4	1		T46	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T35	2		T111	1		T211	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T35	3		T23	1		T27	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T46	9		T165	8		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T7	6		T35	22		T152	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T152	2		T97	8		T271	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T40	1		T36	3		T37	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T9	2		T155	16		T98	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	397	1			T3	13		T48	9		T35	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	384	1			T4	1		T7	14		T40	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15650	1			T6	2		T34	44		T41	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T225	10		T269	8		T110	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T92	6		T270	4		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T1	10		T48	10		T34	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T3	10		T6	5		T111	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1275	1			T8	32		T10	38		T34	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T111	11		T153	7		T140	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T142	2		T182	5		T267	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T140	10		T14	1		T230	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T211	11		T28	12		T29	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T47	9		T213	13		T274	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T3	4		T28	8		T217	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T35	1		T111	7		T145	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T49	12		T217	11		T182	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T136	4		T275	13		T276	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T35	23		T152	12		T12	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T152	16		T156	1		T277	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T36	1		T142	11		T145	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T155	16		T249	12		T267	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	337	1			T3	10		T48	7		T37	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T224	10		T222	11		T182	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20737

1

T1

16

T2

3

T3

30

auto[1]

auto[0]

3800

1

T1

10

T3

24

T6

5