Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24537

1

T1

26

T2

3

T3

54

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

19251

1

T3

8

T4

2

T5

10

auto[ADC_CTRL_FILTER_COND_OUT]

5286

1

T1

26

T2

3

T3

46

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18686

1

T1

26

T3

46

T4

3

auto[1]

5851

1

T2

3

T3

8

T5

10

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20769

1

T1

11

T2

3

T3

27

auto[1]

3768

1

T1

15

T3

27

T5

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	245	1			T7	20		T153	16		T148	1
values[0]	6	1			T278	6		-	-		-	-
values[1]	526	1			T1	26		T4	1		T9	2
values[2]	743	1			T5	10		T152	14		T211	24
values[3]	519	1			T143	1		T23	1		T28	18
values[4]	615	1			T36	4		T142	7		T143	1
values[5]	503	1			T35	3		T23	1		T49	6
values[6]	530	1			T4	1		T34	4		T46	9
values[7]	807	1			T3	23		T4	1		T34	7
values[8]	808	1			T3	31		T48	39		T111	22
values[9]	3177	1			T2	3		T6	21		T8	35
minimum	16058	1			T6	2		T34	45		T41	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	619	1			T1	26		T5	10		T47	10
values[1]	2942	1			T2	3		T8	35		T10	41
values[2]	486	1			T142	2		T143	2		T28	18
values[3]	652	1			T36	4		T142	5		T12	8
values[4]	467	1			T35	3		T213	14		T145	13
values[5]	665	1			T4	1		T34	4		T46	9
values[6]	810	1			T3	23		T4	1		T34	7
values[7]	738	1			T3	31		T48	39		T111	22
values[8]	798	1			T6	21		T7	20		T40	1
values[9]	154	1			T111	8		T152	4		T147	1
minimum	16206	1			T4	1		T6	2		T9	2

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20737

1

T1

16

T2

3

T3

30

auto[1]

3800

1

T1

10

T3

24

T6

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T5	1		T47	10		T140	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T1	11		T40	1		T35	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T152	14		T211	12		T23	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1665	1			T2	3		T8	35		T10	41
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T189	1		T250	3		T93	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T142	1		T143	2		T28	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T142	3		T12	5		T39	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T36	3		T28	13		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T213	14		T23	1		T49	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T35	2		T145	13		T247	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T4	1		T34	2		T46	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T165	1		T143	1		T145	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T34	5		T35	26		T44	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T3	11		T4	1		T46	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T3	5		T48	19		T111	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T3	11		T138	1		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T6	6		T7	2		T35	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T40	1		T142	12		T153	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T111	8		T152	4		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	19	1			T236	1		T273	7		T17	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15945	1			T4	1		T34	44		T41	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T9	1		T279	15		T280	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T5	9		T140	9		T15	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T1	15		T40	17		T35	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T211	12		T140	11		T212	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	925	1			T174	20		T154	21		T140	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T189	11		T170	9		T281	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T142	1		T28	9		T29	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T142	2		T12	3		T39	3
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T36	1		T28	14		T222	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T49	5		T15	1		T272	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T35	1		T148	5		T282	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T34	2		T46	8		T49	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T165	7		T28	10		T190	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T34	2		T35	19		T211	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T3	12		T46	13		T111	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T3	3		T48	20		T111	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T3	12		T138	9		T217	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T6	15		T7	18		T35	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T142	8		T153	16		T204	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T283	2		T284	4		T285	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T236	7		T179	10		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T6	2		T34	1		T35	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T9	1		T279	14		T286	8

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[0]]	*	--	--	2

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T7	2		T153	8		T287	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T148	1		T267	11		T288	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T278	6		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T4	1		T47	10		T140	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T1	11		T9	1		T40	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T5	1		T152	14		T211	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T145	22		T139	1		T140	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T23	1		T189	1		T250	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T143	1		T28	9		T29	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T142	3		T12	5		T39	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T36	3		T142	1		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T23	1		T49	1		T223	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T35	2		T13	4		T247	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T4	1		T34	2		T46	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T165	1		T143	1		T145	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T34	5		T35	26		T44	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T3	11		T4	1		T46	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T3	5		T48	19		T37	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T3	11		T111	13		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T6	6		T35	1		T36	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1687	1			T2	3		T8	35		T10	41
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15906	1			T34	44		T41	20		T35	332
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T7	18		T153	8		T182	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T267	12		T232	8		T179	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T140	9		T15	1		T206	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T1	15		T9	1		T40	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	9		T211	12		T140	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T140	8		T253	11		T87	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T189	11		T282	1		T241	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T28	9		T29	14		T217	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T142	2		T12	3		T39	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T36	1		T142	1		T28	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T49	5		T15	1		T136	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T35	1		T148	5		T282	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T34	2		T46	8		T49	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T165	7		T208	11		T289	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T34	2		T35	19		T211	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T3	12		T46	13		T27	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T3	3		T48	20		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T3	12		T111	9		T155	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T6	15		T35	1		T111	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1019	1			T142	8		T153	16		T174	20
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	2		T34	1		T35	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T5	10		T47	1		T140	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T1	16		T40	18		T35	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T152	1		T211	13		T23	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1264	1			T2	3		T8	3		T10	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T189	12		T250	1		T93	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T142	2		T143	2		T28	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T142	3		T12	7		T39	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T36	3		T28	15		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T213	1		T23	1		T49	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T35	3		T145	1		T247	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T4	1		T34	3		T46	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T165	8		T143	1		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T34	5		T35	22		T44	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T3	13		T4	1		T46	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T3	4		T48	22		T111	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	13		T138	10		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T6	16		T7	20		T35	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T40	1		T142	9		T153	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T111	1		T152	1		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T236	8		T273	1		T17	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16105	1			T4	1		T6	2		T34	45
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T9	2		T279	15		T280	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T47	9		T140	9		T15	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T1	10		T35	1		T224	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T152	13		T211	11		T140	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1326	1			T8	32		T10	38		T42	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	78	1			T250	2		T93	10		T254	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T28	8		T29	17		T217	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T142	2		T12	1		T39	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T36	1		T28	12		T13	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T213	13		T223	2		T15	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T145	12		T210	9		T282	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T34	1		T49	12		T241	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T145	21		T28	16		T14	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T34	2		T35	23		T152	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T3	10		T111	12		T250	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T3	4		T48	17		T111	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T3	10		T217	11		T230	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T6	5		T155	16		T211	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T142	11		T204	13		T272	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T111	7		T152	3		T227	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T273	6		T179	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T228	16		T276	11		T290	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T279	14		T286	7		T291	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T7	20		T153	9		T287	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T148	1		T267	13		T288	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T278	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T4	1		T47	1		T140	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T1	16		T9	2		T40	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T5	10		T152	1		T211	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T145	1		T139	1		T140	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T23	1		T189	12		T250	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T143	1		T28	10		T29	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T142	3		T12	7		T39	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T36	3		T142	2		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T23	1		T49	6		T223	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T35	3		T13	3		T247	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T4	1		T34	3		T46	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T165	8		T143	1		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T34	5		T35	22		T44	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T3	13		T4	1		T46	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T3	4		T48	22		T37	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T3	13		T111	10		T155	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T6	16		T35	2		T36	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1372	1			T2	3		T8	3		T10	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16058	1			T6	2		T34	45		T41	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T153	7		T227	13		T182	5
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T267	10		T273	6		T232	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T278	5		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T47	9		T140	9		T15	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T1	10		T35	1		T224	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T152	13		T211	11		T140	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T145	21		T140	10		T253	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T250	2		T254	14		T275	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T28	8		T29	17		T217	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T142	2		T12	1		T39	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T36	1		T28	12		T210	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T223	2		T15	1		T136	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T13	1		T210	9		T282	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T34	1		T213	13		T49	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T145	12		T289	9		T292	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T34	2		T35	23		T152	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T3	10		T145	21		T28	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T3	4		T48	17		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T3	10		T111	12		T217	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T6	5		T111	18		T152	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1334	1			T8	32		T10	38		T42	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20737

1

T1

16

T2

3

T3

30

auto[1]

auto[0]

3800

1

T1

10

T3

24

T6

5