Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24537

1

T1

26

T2

3

T3

54

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21253

1

T1

26

T2

3

T3

23

auto[ADC_CTRL_FILTER_COND_OUT]

3284

1

T3

31

T4

1

T5

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18874

1

T4

1

T5

10

T6

23

auto[1]

5663

1

T1

26

T2

3

T3

54

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20769

1

T1

11

T2

3

T3

27

auto[1]

3768

1

T1

15

T3

27

T5

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	44	1			T165	8		T141	5		T293	8
values[0]	67	1			T190	1		T136	15		T177	13
values[1]	833	1			T3	23		T4	2		T5	10
values[2]	620	1			T3	23		T48	16		T34	4
values[3]	639	1			T7	6		T111	8		T142	5
values[4]	608	1			T1	26		T6	21		T7	14
values[5]	460	1			T27	10		T189	12		T266	1
values[6]	536	1			T35	3		T111	22		T143	1
values[7]	631	1			T3	8		T35	2		T211	24
values[8]	2992	1			T2	3		T4	1		T8	35
values[9]	1049	1			T48	23		T35	3		T36	4
minimum	16058	1			T6	2		T34	45		T41	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1086	1			T3	23		T4	2		T5	10
values[1]	576	1			T3	23		T48	16		T34	4
values[2]	634	1			T7	20		T46	14		T142	5
values[3]	649	1			T1	26		T6	21		T9	2
values[4]	392	1			T111	22		T143	1		T27	10
values[5]	541	1			T35	3		T211	24		T153	17
values[6]	3036	1			T2	3		T3	8		T8	35
values[7]	507	1			T4	1		T47	10		T34	7
values[8]	836	1			T48	23		T35	3		T36	4
values[9]	222	1			T152	4		T143	1		T138	10
minimum	16058	1			T6	2		T34	45		T41	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20737

1

T1

16

T2

3

T3

30

auto[1]

3800

1

T1

10

T3

24

T6

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T4	1		T142	1		T204	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T3	11		T4	1		T5	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T3	11		T23	1		T233	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T48	8		T34	2		T40	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T7	1		T46	1		T142	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T7	1		T49	9		T189	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T1	11		T9	1		T142	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T6	6		T189	1		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T111	13		T266	1		T182	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T143	1		T27	1		T39	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T211	12		T153	1		T253	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T35	2		T145	13		T29	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1682	1			T2	3		T8	35		T10	41
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T3	5		T35	1		T44	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T4	1		T47	10		T34	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T155	1		T27	1		T190	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T37	2		T165	1		T28	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T48	11		T35	2		T36	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T152	4		T138	1		T15	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T143	1		T267	3		T294	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15906	1			T34	44		T41	20		T35	332
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T142	1		T204	4		T217	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	302	1			T3	12		T5	9		T40	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T3	12		T233	12		T225	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T48	8		T34	2		T137	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T7	5		T46	13		T142	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T7	13		T49	8		T234	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T1	15		T9	1		T142	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T6	15		T189	11		T140	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T111	9		T182	5		T236	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T27	9		T39	3		T208	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T211	12		T153	16		T253	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T35	1		T29	14		T239	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	968	1			T111	10		T174	20		T154	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T3	3		T35	1		T155	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T34	2		T211	6		T28	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T155	1		T27	6		T221	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T37	1		T165	7		T28	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T48	12		T35	1		T36	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	39	1			T138	9		T15	1		T241	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T267	2		T294	8		T18	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	2		T34	1		T35	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T165	1		T141	5		T293	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T295	2		T246	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T136	10		T296	1		T297	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T190	1		T177	1		T298	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T4	1		T142	1		T204	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T3	11		T4	1		T5	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T3	11		T217	12		T233	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T48	8		T34	2		T40	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T7	1		T142	3		T23	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T111	8		T139	1		T210	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T1	11		T9	1		T46	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T6	6		T7	1		T49	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T266	1		T216	1		T93	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T27	1		T189	1		T208	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T111	13		T153	1		T253	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T35	2		T143	1		T145	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T211	12		T145	22		T28	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T3	5		T35	1		T29	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1668	1			T2	3		T4	1		T8	35
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T44	1		T152	13		T155	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T37	2		T152	4		T211	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T48	11		T35	2		T36	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15906	1			T34	44		T41	20		T35	332
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T165	7		T293	5		T299	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T295	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T136	5		T296	2		T297	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T177	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T142	1		T204	4		T14	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T3	12		T5	9		T40	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T3	12		T217	13		T233	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T48	8		T34	2		T35	19
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T7	5		T142	2		T28	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T234	14		T237	10		T222	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T1	15		T9	1		T46	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T6	15		T7	13		T49	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T216	3		T260	9		T16	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T27	9		T189	11		T208	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T111	9		T153	16		T253	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T35	1		T39	3		T282	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T211	12		T28	9		T140	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T3	3		T35	1		T29	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	994	1			T34	2		T111	10		T174	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T155	15		T206	9		T221	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T37	1		T211	6		T28	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	286	1			T48	12		T35	1		T36	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	2		T34	1		T35	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	307	1			T4	1		T142	2		T204	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	354	1			T3	13		T4	1		T5	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T3	13		T23	1		T233	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T48	9		T34	3		T40	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T7	6		T46	14		T142	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T7	14		T49	9		T189	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T1	16		T9	2		T142	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T6	16		T189	12		T146	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T111	10		T266	1		T182	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T143	1		T27	10		T39	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T211	13		T153	17		T253	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T35	3		T145	1		T29	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1313	1			T2	3		T8	3		T10	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T3	4		T35	2		T44	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T4	1		T47	1		T34	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T155	2		T27	7		T190	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T37	2		T165	8		T28	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T48	13		T35	2		T36	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T152	1		T138	10		T15	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T143	1		T267	3		T294	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16058	1			T6	2		T34	45		T41	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T204	13		T217	11		T14	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T3	10		T35	23		T140	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T3	10		T233	12		T225	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T48	7		T34	1		T111	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T142	2		T28	12		T230	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T49	8		T210	14		T234	20
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T1	10		T142	11		T145	21
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T6	5		T140	9		T224	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T111	12		T182	5		T93	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	72	1			T39	1		T274	3		T236	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T211	11		T253	13		T151	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T145	12		T29	17		T239	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1337	1			T8	32		T10	38		T42	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T3	4		T152	12		T155	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T47	9		T34	2		T28	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T182	11		T267	10		T160	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T37	1		T28	16		T49	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T48	10		T35	1		T36	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T152	3		T15	1		T249	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T267	2		T294	8		T300	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T165	8		T141	1		T293	6
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T295	8		T246	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T136	11		T296	3		T297	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T190	1		T177	13		T298	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T4	1		T142	2		T204	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T3	13		T4	1		T5	10
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T3	13		T217	14		T233	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T48	9		T34	3		T40	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T7	6		T142	3		T23	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T111	1		T139	1		T210	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T1	16		T9	2		T46	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T6	16		T7	14		T49	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T266	1		T216	4		T93	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T27	10		T189	12		T208	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T111	10		T153	17		T253	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T35	3		T143	1		T145	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T211	13		T145	1		T28	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T3	4		T35	2		T29	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1339	1			T2	3		T4	1		T8	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T44	1		T152	1		T155	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T37	2		T152	1		T211	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	352	1			T48	13		T35	2		T36	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16058	1			T6	2		T34	45		T41	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T141	4		T293	2		T232	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T295	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T136	4		T297	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T298	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T204	13		T14	1		T233	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T3	10		T140	13		T229	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T3	10		T217	11		T233	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T48	7		T34	1		T35	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T142	2		T28	12		T210	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T111	7		T210	14		T234	20
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T1	10		T142	11		T145	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T6	5		T49	8		T140	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T93	10		T207	17		T16	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T254	14		T157	9		T236	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T111	12		T253	13		T182	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T145	12		T39	1		T239	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T211	11		T145	21		T28	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T3	4		T29	17		T15	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1323	1			T8	32		T10	38		T47	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T152	12		T155	16		T206	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T37	1		T152	3		T28	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T48	10		T35	1		T36	1

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20737

1

T1

16

T2

3

T3

30

auto[1]

auto[0]

3800

1

T1

10

T3

24

T6

5