Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24537

1

T1

26

T2

3

T3

54

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21317

1

T2

3

T3

54

T4

3

auto[ADC_CTRL_FILTER_COND_OUT]

3220

1

T1

26

T47

10

T48

23

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18871

1

T3

23

T4

2

T5

10

auto[1]

5666

1

T1

26

T2

3

T3

31

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20769

1

T1

11

T2

3

T3

27

auto[1]

3768

1

T1

15

T3

27

T5

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	301	1			T152	14		T142	20		T145	22
values[0]	75	1			T35	45		T152	13		T301	2
values[1]	785	1			T3	23		T155	2		T140	25
values[2]	854	1			T4	1		T5	10		T142	5
values[3]	606	1			T111	22		T12	8		T49	14
values[4]	467	1			T34	4		T143	1		T155	32
values[5]	480	1			T7	6		T9	2		T40	1
values[6]	502	1			T34	7		T40	18		T36	4
values[7]	629	1			T4	1		T7	14		T48	16
values[8]	553	1			T3	31		T4	1		T46	9
values[9]	3227	1			T1	26		T2	3		T6	21
minimum	16058	1			T6	2		T34	45		T41	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	815	1			T155	2		T28	27		T140	25
values[1]	855	1			T4	1		T5	10		T142	5
values[2]	526	1			T34	4		T111	22		T143	1
values[3]	420	1			T7	6		T142	2		T211	7
values[4]	521	1			T9	2		T40	19		T35	3
values[5]	456	1			T34	7		T36	4		T143	1
values[6]	2965	1			T2	3		T4	1		T7	14
values[7]	566	1			T1	26		T3	31		T4	1
values[8]	938	1			T6	21		T47	10		T48	23
values[9]	139	1			T211	7		T146	1		T191	14
minimum	16336	1			T3	23		T6	2		T34	45

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20737

1

T1

16

T2

3

T3

30

auto[1]

3800

1

T1

10

T3

24

T6

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T155	1		T223	3		T141	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	248	1			T28	13		T140	14		T233	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T4	1		T5	1		T211	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T142	3		T153	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T34	2		T155	17		T12	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T111	12		T143	1		T49	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T7	1		T142	1		T23	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T211	7		T145	22		T49	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T9	1		T40	1		T35	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T40	1		T36	2		T37	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T34	5		T36	3		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T189	1		T247	1		T230	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1673	1			T2	3		T4	1		T7	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T35	2		T37	2		T28	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T3	16		T4	1		T111	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T1	11		T46	2		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	298	1			T6	6		T44	1		T152	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T47	10		T48	11		T35	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	28	1			T211	1		T302	18		T303	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	51	1			T146	1		T191	10		T228	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16029	1			T3	11		T34	44		T41	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T272	1		T207	12		T254	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T155	1		T223	8		T225	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T28	14		T140	11		T233	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	9		T211	12		T153	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T142	2		T153	16		T137	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T34	2		T155	15		T12	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T111	10		T49	1		T189	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T7	5		T142	1		T204	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T49	8		T38	2		T237	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T9	1		T35	1		T165	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T40	17		T212	9		T148	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T34	2		T36	1		T209	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T226	12		T97	12		T241	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	946	1			T7	13		T48	8		T111	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T35	1		T37	1		T28	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T3	15		T27	6		T39	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T1	15		T46	21		T216	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T6	15		T233	1		T272	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T48	12		T35	1		T142	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T211	6		T303	7		T235	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T191	4		T228	15		T304	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T3	12		T6	2		T34	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	33	1			T272	1		T158	12		T261	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T152	14		T145	22		T182	12
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T142	12		T49	1		T146	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	55	1			T35	26		T152	13		T301	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T3	11		T155	1		T223	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T140	14		T233	14		T242	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T4	1		T5	1		T211	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T142	3		T153	1		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T12	5		T221	1		T227	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T111	12		T49	13		T138	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T34	2		T155	17		T23	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T143	1		T211	7		T49	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T7	1		T9	1		T40	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T36	2		T143	1		T145	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T34	5		T36	3		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T40	1		T37	1		T189	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T4	1		T7	1		T48	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T35	2		T37	2		T28	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T3	16		T4	1		T111	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T46	1		T13	4		T257	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1717	1			T2	3		T6	6		T8	35
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T1	11		T47	10		T48	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15906	1			T34	44		T41	20		T35	332
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T182	12		T289	13		T305	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T142	8		T49	5		T191	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T35	19		T301	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T3	12		T155	1		T223	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T140	11		T233	12		T242	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T5	9		T211	12		T153	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T142	2		T153	16		T137	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T12	3		T221	15		T306	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T111	10		T49	1		T138	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T34	2		T155	15		T204	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T49	8		T38	2		T14	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T7	5		T9	1		T35	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T148	5		T239	1		T307	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T34	2		T36	1		T209	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T40	17		T212	9		T226	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	108	1			T7	13		T48	8		T111	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T35	1		T37	1		T28	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T3	15		T27	6		T39	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T46	8		T216	3		T271	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	986	1			T6	15		T211	6		T174	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T1	15		T48	12		T35	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	2		T34	1		T35	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T155	2		T223	9		T141	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T28	15		T140	12		T233	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T4	1		T5	10		T211	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T142	3		T153	17		T137	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T34	3		T155	16		T12	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T111	11		T143	1		T49	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T7	6		T142	2		T23	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T211	1		T145	1		T49	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T9	2		T40	1		T35	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T40	18		T36	2		T37	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T34	5		T36	3		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T189	1		T247	1		T230	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1288	1			T2	3		T4	1		T7	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T35	2		T37	2		T28	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T3	17		T4	1		T111	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T1	16		T46	23		T139	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	278	1			T6	16		T44	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T47	1		T48	13		T35	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T211	7		T302	1		T303	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	52	1			T146	1		T191	5		T228	16
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16136	1			T3	13		T6	2		T34	45
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T272	2		T207	1		T254	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T223	2		T141	4		T225	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T28	12		T140	13		T233	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T211	11		T153	7		T140	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	168	1			T142	2		T29	17		T223	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T34	1		T155	16		T12	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T111	11		T49	12		T14	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T204	13		T308	6		T283	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T211	6		T145	21		T49	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T28	16		T15	1		T210	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T239	1		T309	2		T256	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T34	2		T36	1		T234	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T230	4		T226	13		T182	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1331	1			T8	32		T10	38		T48	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T35	1		T37	1		T28	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T3	14		T111	7		T39	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T1	10		T13	1		T210	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T6	5		T152	13		T145	33
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T47	9		T48	10		T142	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T302	17		T303	3		T235	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T191	9		T228	16		T310	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T3	10		T35	23		T152	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	55	1			T207	11		T254	10		T158	10

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T152	1		T145	1		T182	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T142	9		T49	6		T146	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T35	22		T152	1		T301	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T3	13		T155	2		T223	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T140	12		T233	13		T242	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T4	1		T5	10		T211	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	314	1			T142	3		T153	17		T137	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	7		T221	16		T227	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T111	11		T49	2		T138	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T34	3		T155	16		T23	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T143	1		T211	1		T49	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T7	6		T9	2		T40	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T36	2		T143	1		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T34	5		T36	3		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T40	18		T37	1		T189	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T4	1		T7	14		T48	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T35	2		T37	2		T28	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	17		T4	1		T111	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T46	9		T13	3		T257	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1339	1			T2	3		T6	16		T8	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T1	16		T47	1		T48	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16058	1			T6	2		T34	45		T41	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T152	13		T145	21		T182	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T142	11		T191	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T35	23		T152	12		T311	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T3	10		T223	2		T136	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T140	13		T233	13		T250	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T211	11		T153	7		T140	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T142	2		T28	12		T29	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T12	1		T227	13		T273	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T111	11		T49	12		T206	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T34	1		T155	16		T204	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T211	6		T49	8		T14	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T28	16		T15	1		T210	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T145	21		T239	1		T309	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T34	2		T36	1		T234	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T230	4		T226	13		T182	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T48	7		T111	12		T152	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T35	1		T37	1		T28	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T3	14		T111	7		T39	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T13	1		T210	1		T256	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1364	1			T6	5		T8	32		T10	38
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T1	10		T47	9		T48	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20737

1

T1

16

T2

3

T3

30

auto[1]

auto[0]

3800

1

T1

10

T3

24

T6

5