Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24537

1

T1

26

T2

3

T3

54

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21426

1

T2

3

T3

54

T4

3

auto[ADC_CTRL_FILTER_COND_OUT]

3111

1

T1

26

T7

14

T47

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19002

1

T3

23

T4

2

T5

10

auto[1]

5535

1

T1

26

T2

3

T3

31

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20769

1

T1

11

T2

3

T3

27

auto[1]

3768

1

T1

15

T3

27

T5

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	9	1			T300	2		T312	1		T313	2
values[0]	37	1			T272	2		T97	8		T161	5
values[1]	790	1			T3	23		T35	45		T152	13
values[2]	949	1			T4	1		T5	10		T142	5
values[3]	591	1			T111	22		T143	1		T155	32
values[4]	451	1			T34	4		T211	7		T23	1
values[5]	427	1			T7	6		T9	2		T40	1
values[6]	538	1			T34	7		T40	18		T36	4
values[7]	613	1			T4	1		T7	14		T48	16
values[8]	571	1			T3	31		T4	1		T46	9
values[9]	3503	1			T1	26		T2	3		T6	21
minimum	16058	1			T6	2		T34	45		T41	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1045	1			T3	23		T35	45		T152	13
values[1]	851	1			T4	1		T5	10		T142	5
values[2]	529	1			T34	4		T111	22		T143	1
values[3]	429	1			T7	6		T142	2		T211	7
values[4]	491	1			T9	2		T40	19		T35	3
values[5]	499	1			T34	7		T36	4		T143	1
values[6]	2964	1			T2	3		T4	1		T7	14
values[7]	577	1			T1	26		T3	31		T4	1
values[8]	888	1			T6	21		T47	10		T48	23
values[9]	179	1			T211	7		T191	14		T228	32
minimum	16085	1			T6	2		T34	45		T41	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20737

1

T1

16

T2

3

T3

30

auto[1]

3800

1

T1

10

T3

24

T6

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T3	11		T152	13		T155	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	310	1			T35	26		T28	13		T140	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T4	1		T5	1		T211	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T142	3		T153	1		T137	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T34	2		T12	5		T229	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T111	12		T143	1		T155	17
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T7	1		T23	1		T49	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T142	1		T211	7		T145	22
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T9	1		T40	2		T35	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T36	2		T143	1		T247	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T34	5		T36	3		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T189	1		T247	1		T230	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1674	1			T2	3		T4	1		T8	35
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T7	1		T28	9		T257	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T3	16		T4	1		T46	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T1	11		T35	2		T46	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	291	1			T6	6		T44	1		T152	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T47	10		T48	11		T35	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T211	1		T305	3		T302	18
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	75	1			T191	10		T228	17		T304	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15914	1			T34	44		T41	20		T35	332
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T314	16		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T3	12		T155	1		T223	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T35	19		T28	14		T140	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T5	9		T211	12		T153	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T142	2		T153	16		T137	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T34	2		T12	3		T229	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T111	10		T155	15		T49	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T7	5		T49	8		T204	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T142	1		T38	2		T237	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T9	1		T40	17		T35	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T212	9		T148	5		T239	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T34	2		T36	1		T27	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	118	1			T242	8		T226	12		T97	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	973	1			T48	8		T111	9		T37	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T7	13		T28	9		T241	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T3	15		T46	8		T27	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	97	1			T1	15		T35	1		T46	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T6	15		T233	1		T272	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T48	12		T35	1		T142	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T211	6		T305	1		T303	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T191	4		T228	15		T304	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T6	2		T34	1		T35	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T300	1		T315	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	5	1			T312	1		T313	1		T20	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T161	1		T316	1		T317	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T272	1		T97	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T3	11		T152	13		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T35	26		T137	1		T233	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T4	1		T5	1		T211	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T142	3		T153	1		T28	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T12	5		T221	1		T229	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T111	12		T143	1		T155	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T34	2		T23	1		T28	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T211	7		T38	3		T14	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T7	1		T9	1		T40	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T36	2		T142	1		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T34	5		T40	1		T36	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T189	1		T247	1		T230	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T4	1		T48	8		T111	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T7	1		T35	2		T28	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T3	16		T4	1		T46	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T13	4		T257	1		T210	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1870	1			T2	3		T6	6		T8	35
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T1	11		T47	10		T48	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15906	1			T34	44		T41	20		T35	332
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T300	1		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T313	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T161	4		T316	2		T301	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T272	1		T97	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T3	12		T155	1		T223	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T35	19		T137	5		T233	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T5	9		T211	12		T153	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T142	2		T153	16		T28	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T12	3		T221	15		T229	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T111	10		T155	15		T49	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T34	2		T28	10		T49	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T38	2		T14	2		T237	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T7	5		T9	1		T35	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T142	1		T148	5		T239	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T34	2		T40	17		T36	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T212	9		T242	8		T226	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T48	8		T111	9		T37	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T7	13		T35	1		T28	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T3	15		T46	8		T27	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T216	3		T271	11		T241	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1077	1			T6	15		T211	6		T174	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T1	15		T48	12		T35	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	2		T34	1		T35	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T3	13		T152	1		T155	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T35	22		T28	15		T140	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T4	1		T5	10		T211	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	350	1			T142	3		T153	17		T137	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T34	3		T12	7		T229	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T111	11		T143	1		T155	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T7	6		T23	1		T49	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T142	2		T211	1		T145	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T9	2		T40	19		T35	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T36	2		T143	1		T247	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T34	5		T36	3		T143	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T189	1		T247	1		T230	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1312	1			T2	3		T4	1		T8	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T7	14		T28	10		T257	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T3	17		T4	1		T46	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T1	16		T35	2		T46	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T6	16		T44	1		T152	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T47	1		T48	13		T35	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T211	7		T305	2		T302	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T191	5		T228	16		T304	3
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16066	1			T6	2		T34	45		T41	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T314	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T3	10		T152	12		T223	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T35	23		T28	12		T140	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T211	11		T153	7		T140	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T142	2		T29	17		T223	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T34	1		T12	1		T229	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	91	1			T111	11		T155	16		T49	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T49	8		T204	13		T283	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	106	1			T211	6		T145	21		T237	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T28	16		T15	1		T210	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T239	1		T309	2		T277	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T34	2		T36	1		T234	20
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T230	4		T226	13		T97	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1335	1			T8	32		T10	38		T48	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T28	8		T241	3		T267	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T3	14		T111	7		T166	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T1	10		T35	1		T13	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T6	5		T152	13		T145	33
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T47	9		T48	10		T142	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T305	2		T302	17		T303	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T191	9		T228	16		T281	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T274	3		-	-		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T314	15		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T300	2		T315	1		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T312	1		T313	2		T20	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	13	1			T161	5		T316	3		T317	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T272	2		T97	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T3	13		T152	1		T155	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T35	22		T137	6		T233	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T4	1		T5	10		T211	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T142	3		T153	17		T28	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	7		T221	16		T229	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T111	11		T143	1		T155	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T34	3		T23	1		T28	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T211	1		T38	5		T14	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T7	6		T9	2		T40	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T36	2		T142	2		T143	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T34	5		T40	18		T36	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T189	1		T247	1		T230	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T4	1		T48	9		T111	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T7	14		T35	2		T28	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T3	17		T4	1		T46	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T13	3		T257	1		T210	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1445	1			T2	3		T6	16		T8	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T1	16		T47	1		T48	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16058	1			T6	2		T34	45		T41	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T311	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T3	10		T152	12		T223	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T35	23		T233	13		T250	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T211	11		T153	7		T140	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T142	2		T28	12		T29	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T12	1		T229	13		T227	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T111	11		T155	16		T49	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T34	1		T28	16		T49	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T211	6		T14	1		T237	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T15	1		T210	9		T92	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T145	21		T239	1		T309	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T34	2		T36	1		T140	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T230	4		T226	13		T249	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T48	7		T111	12		T37	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T35	1		T28	8		T15	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T3	14		T111	7		T166	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T13	1		T210	1		T241	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1502	1			T6	5		T8	32		T10	38
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T1	10		T47	9		T48	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20737

1

T1

16

T2

3

T3

30

auto[1]

auto[0]

3800

1

T1

10

T3

24

T6

5