Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24537

1

T1

26

T2

3

T3

54

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

21268

1

T1

26

T2

3

T4

1

auto[ADC_CTRL_FILTER_COND_OUT]

3269

1

T3

54

T4

2

T5

10

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18825

1

T1

26

T3

31

T4

1

auto[1]

5712

1

T2

3

T3

23

T4

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20769

1

T1

11

T2

3

T3

27

auto[1]

3768

1

T1

15

T3

27

T5

9

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	216	1			T35	45		T140	25		T15	5
values[0]	39	1			T153	17		T254	15		T318	7
values[1]	563	1			T35	2		T165	8		T143	1
values[2]	475	1			T4	2		T5	10		T35	3
values[3]	620	1			T4	1		T7	6		T48	16
values[4]	2840	1			T2	3		T3	23		T8	35
values[5]	694	1			T40	1		T152	18		T143	1
values[6]	878	1			T1	26		T3	31		T211	7
values[7]	557	1			T7	14		T47	10		T40	18
values[8]	748	1			T34	11		T111	30		T155	32
values[9]	849	1			T6	21		T9	2		T48	23
minimum	16058	1			T6	2		T34	45		T41	20

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	486	1			T4	1		T35	2		T111	22
values[1]	516	1			T4	1		T5	10		T35	3
values[2]	671	1			T3	23		T4	1		T7	6
values[3]	2838	1			T2	3		T8	35		T10	41
values[4]	779	1			T1	26		T40	1		T152	18
values[5]	731	1			T3	31		T40	18		T35	3
values[6]	628	1			T7	14		T47	10		T34	11
values[7]	773	1			T111	22		T155	32		T153	16
values[8]	807	1			T6	21		T9	2		T48	23
values[9]	64	1			T141	1		T237	15		T92	16
minimum	16244	1			T6	2		T34	45		T41	20

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20737

1

T1

16

T2

3

T3

30

auto[1]

3800

1

T1

10

T3

24

T6

5

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T257	1		T287	1		T216	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T4	1		T35	1		T111	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T4	1		T35	2		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T5	1		T44	1		T141	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T48	8		T36	2		T152	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T3	11		T4	1		T7	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1649	1			T2	3		T8	35		T10	41
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T23	1		T139	1		T190	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T1	11		T152	4		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T40	1		T152	14		T49	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T40	1		T35	2		T145	22
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T3	16		T37	1		T28	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T7	1		T34	5		T46	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T47	10		T34	2		T140	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T111	13		T155	17		T153	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T27	1		T209	1		T189	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T6	6		T36	3		T37	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T9	1		T48	11		T35	26
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T141	1		T319	1		T101	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T237	5		T92	7		T320	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15931	1			T34	44		T41	20		T35	332
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	70	1			T287	1		T254	15		T321	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T216	2		T289	1		T158	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T35	1		T111	10		T165	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T35	1		T155	1		T14	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	73	1			T5	9		T267	12		T289	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T48	8		T211	6		T27	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T3	12		T7	5		T142	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	935	1			T142	3		T174	20		T29	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	127	1			T136	5		T225	9		T226	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T1	15		T137	5		T182	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T49	5		T190	2		T206	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T40	17		T35	1		T223	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T3	15		T28	9		T140	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T7	13		T34	2		T46	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T34	2		T140	8		T148	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T111	9		T155	15		T153	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T27	9		T209	2		T189	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T6	15		T36	1		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T9	1		T48	12		T35	19
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T237	10		T92	9		T322	15
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T6	2		T34	1		T35	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T323	14		T245	2		T324	15

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	34	1			T15	4		T141	1		T325	3
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	96	1			T35	26		T140	14		T237	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T153	1		T318	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T254	15		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T143	1		T38	3		T257	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T35	1		T165	1		T287	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T4	1		T35	2		T145	22
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T4	1		T5	1		T111	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T48	8		T36	2		T152	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T4	1		T7	1		T44	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1611	1			T2	3		T8	35		T10	41
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T3	11		T23	1		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T152	4		T143	1		T213	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T40	1		T152	14		T49	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T1	11		T211	7		T145	22
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T3	16		T28	9		T140	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T7	1		T40	1		T35	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T47	10		T37	1		T140	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T34	5		T111	21		T155	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T34	2		T27	1		T209	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T6	6		T36	3		T37	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T9	1		T48	11		T46	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15906	1			T34	44		T41	20		T35	332
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T15	1		T236	7		T295	11
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T35	19		T140	11		T237	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T153	16		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T38	2		T216	2		T289	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T35	1		T165	7		T306	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T35	1		T14	2		T221	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T5	9		T111	10		T229	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T48	8		T155	1		T211	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T7	5		T142	8		T211	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	912	1			T142	3		T174	20		T154	21
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T3	12		T226	12		T304	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T137	5		T29	14		T182	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T49	5		T190	2		T136	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T1	15		T223	8		T233	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T3	15		T28	9		T140	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T7	13		T40	17		T35	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T140	8		T272	7		T182	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T34	2		T111	9		T155	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T34	2		T27	9		T209	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T6	15		T36	1		T37	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T9	1		T48	12		T46	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T6	2		T34	1		T35	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[9]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T257	1		T287	1		T216	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T4	1		T35	2		T111	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T4	1		T35	2		T155	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T5	10		T44	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T48	9		T36	2		T152	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T3	13		T4	1		T7	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1275	1			T2	3		T8	3		T10	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T23	1		T139	1		T190	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T1	16		T152	1		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T40	1		T152	1		T49	6
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T40	18		T35	3		T145	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T3	17		T37	1		T28	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T7	14		T34	5		T46	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T47	1		T34	3		T140	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T111	10		T155	16		T153	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T27	10		T209	3		T189	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T6	16		T36	3		T37	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T9	2		T48	13		T35	22
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T141	1		T319	1		T101	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T237	11		T92	10		T320	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16092	1			T6	2		T34	45		T41	20
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	77	1			T287	1		T254	1		T321	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T158	10		T326	2		T269	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T111	11		T229	13		T250	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T35	1		T145	21		T14	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T141	4		T267	10		T276	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T48	7		T152	12		T83	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T3	10		T142	11		T211	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1309	1			T8	32		T10	38		T42	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T136	4		T225	10		T226	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T1	10		T152	3		T213	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T152	13		T206	11		T327	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T145	21		T223	2		T210	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T3	14		T28	8		T140	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T34	2		T111	7		T28	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T47	9		T34	1		T140	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T111	12		T155	16		T153	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T15	1		T233	12		T240	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T6	5		T36	1		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T48	10		T35	23		T39	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T237	4		T92	6		T322	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T318	6		T328	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T254	14		T321	1		T273	2

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	37	1			T15	4		T141	1		T325	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T35	22		T140	12		T237	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T153	17		T318	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T254	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T143	1		T38	5		T257	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T35	2		T165	8		T287	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T4	1		T35	2		T145	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T4	1		T5	10		T111	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T48	9		T36	2		T152	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T4	1		T7	6		T44	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1245	1			T2	3		T8	3		T10	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T3	13		T23	1		T139	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T152	1		T143	1		T213	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T40	1		T152	1		T49	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T1	16		T211	1		T145	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T3	17		T28	10		T140	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T7	14		T40	18		T35	3
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T47	1		T37	1		T140	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T34	5		T111	11		T155	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T34	3		T27	10		T209	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T6	16		T36	3		T37	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T9	2		T48	13		T46	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16058	1			T6	2		T34	45		T41	20
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T15	1		T325	2		T329	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T35	23		T140	13		T237	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T318	6		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T254	14		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T158	10		T270	4		T232	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T250	13		T330	13		T151	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T35	1		T145	21		T14	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T111	11		T141	4		T229	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T48	7		T152	12		T83	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T142	11		T211	11		T166	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1278	1			T8	32		T10	38		T42	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T3	10		T226	13		T279	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T152	3		T213	13		T145	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	85	1			T152	13		T136	4		T206	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T1	10		T211	6		T145	21
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T3	14		T28	8		T140	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T28	12		T49	8		T93	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T47	9		T140	10		T272	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T34	2		T111	19		T155	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T34	1		T15	1		T240	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T6	5		T36	1		T37	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T48	10		T39	1		T217	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

20737

1

T1

16

T2

3

T3

30

auto[1]

auto[0]

3800

1

T1

10

T3

24

T6

5