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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.75 99.07 96.67 100.00 100.00 98.83 98.33 91.34


Total test records in report: 919
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T797 /workspace/coverage/default/15.adc_ctrl_filters_both.2867050928 Jul 09 06:33:55 PM PDT 24 Jul 09 06:37:35 PM PDT 24 343721983298 ps
T798 /workspace/coverage/default/17.adc_ctrl_poweron_counter.1521291217 Jul 09 06:34:11 PM PDT 24 Jul 09 06:34:19 PM PDT 24 4192658526 ps
T799 /workspace/coverage/default/40.adc_ctrl_stress_all.3136625494 Jul 09 06:38:48 PM PDT 24 Jul 09 06:50:59 PM PDT 24 365612227940 ps
T800 /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.4039486151 Jul 09 06:35:24 PM PDT 24 Jul 09 06:54:18 PM PDT 24 487829681217 ps
T53 /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2248727493 Jul 09 06:24:40 PM PDT 24 Jul 09 06:24:43 PM PDT 24 2552366946 ps
T133 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2847942951 Jul 09 06:24:10 PM PDT 24 Jul 09 06:24:12 PM PDT 24 1341426681 ps
T801 /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1460713579 Jul 09 06:24:56 PM PDT 24 Jul 09 06:24:57 PM PDT 24 382648292 ps
T802 /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1967394208 Jul 09 06:24:57 PM PDT 24 Jul 09 06:24:59 PM PDT 24 567271804 ps
T803 /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.406927995 Jul 09 06:24:55 PM PDT 24 Jul 09 06:24:57 PM PDT 24 466958734 ps
T804 /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3710004222 Jul 09 06:24:46 PM PDT 24 Jul 09 06:24:48 PM PDT 24 317172303 ps
T56 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.4010389863 Jul 09 06:24:04 PM PDT 24 Jul 09 06:24:11 PM PDT 24 4360114229 ps
T60 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2210998343 Jul 09 06:24:06 PM PDT 24 Jul 09 06:24:09 PM PDT 24 746455479 ps
T805 /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2044325493 Jul 09 06:24:52 PM PDT 24 Jul 09 06:24:54 PM PDT 24 402202622 ps
T65 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2753825402 Jul 09 06:24:03 PM PDT 24 Jul 09 06:24:04 PM PDT 24 764390825 ps
T54 /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2830611241 Jul 09 06:24:36 PM PDT 24 Jul 09 06:24:42 PM PDT 24 5246320049 ps
T68 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2454783609 Jul 09 06:24:27 PM PDT 24 Jul 09 06:24:30 PM PDT 24 545760022 ps
T806 /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3654405586 Jul 09 06:24:12 PM PDT 24 Jul 09 06:24:13 PM PDT 24 303146470 ps
T73 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1398694181 Jul 09 06:24:12 PM PDT 24 Jul 09 06:24:14 PM PDT 24 484964981 ps
T66 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1559893982 Jul 09 06:24:38 PM PDT 24 Jul 09 06:24:42 PM PDT 24 655758030 ps
T807 /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.4177809462 Jul 09 06:24:48 PM PDT 24 Jul 09 06:24:50 PM PDT 24 483317797 ps
T55 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.493560979 Jul 09 06:24:06 PM PDT 24 Jul 09 06:25:24 PM PDT 24 50525583128 ps
T126 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3195647329 Jul 09 06:24:36 PM PDT 24 Jul 09 06:24:37 PM PDT 24 370134995 ps
T57 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3026453586 Jul 09 06:24:16 PM PDT 24 Jul 09 06:24:20 PM PDT 24 4700202048 ps
T89 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1059457514 Jul 09 06:24:38 PM PDT 24 Jul 09 06:24:40 PM PDT 24 548608672 ps
T808 /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1070121066 Jul 09 06:24:06 PM PDT 24 Jul 09 06:24:07 PM PDT 24 375809613 ps
T90 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4045427067 Jul 09 06:24:37 PM PDT 24 Jul 09 06:24:40 PM PDT 24 332506960 ps
T127 /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2253042132 Jul 09 06:24:19 PM PDT 24 Jul 09 06:24:35 PM PDT 24 3915143350 ps
T58 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.595370448 Jul 09 06:24:17 PM PDT 24 Jul 09 06:24:30 PM PDT 24 4628382815 ps
T100 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.691871465 Jul 09 06:24:35 PM PDT 24 Jul 09 06:24:37 PM PDT 24 493620778 ps
T128 /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3785966999 Jul 09 06:24:43 PM PDT 24 Jul 09 06:25:04 PM PDT 24 5214717575 ps
T74 /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3525225275 Jul 09 06:24:39 PM PDT 24 Jul 09 06:25:02 PM PDT 24 8329359766 ps
T809 /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.523110119 Jul 09 06:24:54 PM PDT 24 Jul 09 06:24:56 PM PDT 24 543527805 ps
T350 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.4243863675 Jul 09 06:24:27 PM PDT 24 Jul 09 06:24:31 PM PDT 24 4540313474 ps
T810 /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3852715993 Jul 09 06:24:44 PM PDT 24 Jul 09 06:24:45 PM PDT 24 303981731 ps
T61 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.880816340 Jul 09 06:24:10 PM PDT 24 Jul 09 06:24:32 PM PDT 24 8038401405 ps
T112 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3024309901 Jul 09 06:24:09 PM PDT 24 Jul 09 06:24:11 PM PDT 24 309982281 ps
T129 /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3522900724 Jul 09 06:24:26 PM PDT 24 Jul 09 06:24:47 PM PDT 24 4923036914 ps
T69 /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.977028025 Jul 09 06:24:24 PM PDT 24 Jul 09 06:24:26 PM PDT 24 408970979 ps
T130 /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3189125133 Jul 09 06:24:34 PM PDT 24 Jul 09 06:24:38 PM PDT 24 2723607331 ps
T811 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.865699469 Jul 09 06:24:20 PM PDT 24 Jul 09 06:24:24 PM PDT 24 852410188 ps
T352 /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.4006467911 Jul 09 06:24:31 PM PDT 24 Jul 09 06:24:40 PM PDT 24 4392324120 ps
T353 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.423407983 Jul 09 06:24:38 PM PDT 24 Jul 09 06:25:02 PM PDT 24 8611899236 ps
T812 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1962440826 Jul 09 06:24:34 PM PDT 24 Jul 09 06:24:35 PM PDT 24 685527539 ps
T813 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3809160620 Jul 09 06:24:38 PM PDT 24 Jul 09 06:24:41 PM PDT 24 438486143 ps
T131 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.4177291401 Jul 09 06:24:25 PM PDT 24 Jul 09 06:24:26 PM PDT 24 348814173 ps
T814 /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1634999359 Jul 09 06:24:21 PM PDT 24 Jul 09 06:24:23 PM PDT 24 536534995 ps
T354 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.4048777955 Jul 09 06:24:31 PM PDT 24 Jul 09 06:24:36 PM PDT 24 4595252961 ps
T815 /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3526960497 Jul 09 06:24:55 PM PDT 24 Jul 09 06:24:57 PM PDT 24 291685887 ps
T816 /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3440514238 Jul 09 06:24:18 PM PDT 24 Jul 09 06:24:20 PM PDT 24 466440477 ps
T67 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2592282669 Jul 09 06:24:53 PM PDT 24 Jul 09 06:24:56 PM PDT 24 524634677 ps
T113 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2794585279 Jul 09 06:24:21 PM PDT 24 Jul 09 06:24:46 PM PDT 24 52114135780 ps
T817 /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1857700353 Jul 09 06:24:49 PM PDT 24 Jul 09 06:24:51 PM PDT 24 523179594 ps
T818 /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.922973970 Jul 09 06:24:48 PM PDT 24 Jul 09 06:24:50 PM PDT 24 397886561 ps
T132 /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2720785976 Jul 09 06:24:23 PM PDT 24 Jul 09 06:24:26 PM PDT 24 4442504228 ps
T819 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3951260710 Jul 09 06:24:16 PM PDT 24 Jul 09 06:24:35 PM PDT 24 27669141271 ps
T114 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.905108631 Jul 09 06:24:10 PM PDT 24 Jul 09 06:24:11 PM PDT 24 336477394 ps
T820 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2484984326 Jul 09 06:24:48 PM PDT 24 Jul 09 06:24:49 PM PDT 24 395487734 ps
T821 /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1011033577 Jul 09 06:24:47 PM PDT 24 Jul 09 06:24:49 PM PDT 24 304046738 ps
T115 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2989705939 Jul 09 06:24:09 PM PDT 24 Jul 09 06:24:12 PM PDT 24 1034266848 ps
T822 /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.824730465 Jul 09 06:24:49 PM PDT 24 Jul 09 06:24:50 PM PDT 24 346785150 ps
T823 /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.281034173 Jul 09 06:24:44 PM PDT 24 Jul 09 06:24:46 PM PDT 24 303817903 ps
T824 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2572756340 Jul 09 06:24:25 PM PDT 24 Jul 09 06:24:27 PM PDT 24 533032295 ps
T70 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2868820396 Jul 09 06:24:36 PM PDT 24 Jul 09 06:24:39 PM PDT 24 485732734 ps
T825 /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.4119330691 Jul 09 06:25:01 PM PDT 24 Jul 09 06:25:02 PM PDT 24 449525510 ps
T826 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3951258200 Jul 09 06:24:48 PM PDT 24 Jul 09 06:24:53 PM PDT 24 4691427381 ps
T827 /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3076735137 Jul 09 06:24:54 PM PDT 24 Jul 09 06:24:57 PM PDT 24 5340826654 ps
T116 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1856431526 Jul 09 06:24:45 PM PDT 24 Jul 09 06:24:47 PM PDT 24 397730029 ps
T828 /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3093464161 Jul 09 06:24:46 PM PDT 24 Jul 09 06:24:47 PM PDT 24 354854950 ps
T829 /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.111211647 Jul 09 06:24:14 PM PDT 24 Jul 09 06:24:18 PM PDT 24 413557238 ps
T830 /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1338789320 Jul 09 06:24:26 PM PDT 24 Jul 09 06:24:31 PM PDT 24 4735767110 ps
T831 /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1904068068 Jul 09 06:24:54 PM PDT 24 Jul 09 06:24:56 PM PDT 24 455421854 ps
T832 /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3503370646 Jul 09 06:24:50 PM PDT 24 Jul 09 06:24:52 PM PDT 24 510233284 ps
T833 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3865498878 Jul 09 06:24:39 PM PDT 24 Jul 09 06:24:44 PM PDT 24 675444805 ps
T834 /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2324053064 Jul 09 06:24:41 PM PDT 24 Jul 09 06:24:46 PM PDT 24 4798177699 ps
T835 /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.4024530349 Jul 09 06:24:27 PM PDT 24 Jul 09 06:24:28 PM PDT 24 419451647 ps
T836 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.608432246 Jul 09 06:24:32 PM PDT 24 Jul 09 06:24:35 PM PDT 24 646811627 ps
T837 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3498108476 Jul 09 06:24:42 PM PDT 24 Jul 09 06:24:46 PM PDT 24 579193969 ps
T117 /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1843176746 Jul 09 06:24:40 PM PDT 24 Jul 09 06:24:42 PM PDT 24 392677026 ps
T838 /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2306223073 Jul 09 06:24:38 PM PDT 24 Jul 09 06:24:45 PM PDT 24 8523850081 ps
T839 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2626723600 Jul 09 06:24:46 PM PDT 24 Jul 09 06:25:03 PM PDT 24 7591107625 ps
T840 /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.4053434299 Jul 09 06:24:37 PM PDT 24 Jul 09 06:24:40 PM PDT 24 527118509 ps
T841 /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.159478567 Jul 09 06:25:00 PM PDT 24 Jul 09 06:25:02 PM PDT 24 419780423 ps
T842 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1763745697 Jul 09 06:24:20 PM PDT 24 Jul 09 06:24:23 PM PDT 24 795877737 ps
T843 /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.363629462 Jul 09 06:24:36 PM PDT 24 Jul 09 06:24:37 PM PDT 24 563591501 ps
T844 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2987845432 Jul 09 06:24:43 PM PDT 24 Jul 09 06:24:45 PM PDT 24 531145416 ps
T845 /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2125791461 Jul 09 06:24:14 PM PDT 24 Jul 09 06:24:22 PM PDT 24 2019508743 ps
T846 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3183013637 Jul 09 06:24:08 PM PDT 24 Jul 09 06:24:25 PM PDT 24 25940359853 ps
T847 /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.870309106 Jul 09 06:24:34 PM PDT 24 Jul 09 06:24:36 PM PDT 24 670010308 ps
T848 /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2415000505 Jul 09 06:24:54 PM PDT 24 Jul 09 06:24:56 PM PDT 24 455058050 ps
T849 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1152844174 Jul 09 06:24:09 PM PDT 24 Jul 09 06:24:12 PM PDT 24 757630239 ps
T118 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2925100738 Jul 09 06:24:37 PM PDT 24 Jul 09 06:24:38 PM PDT 24 384277761 ps
T850 /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.123320409 Jul 09 06:24:55 PM PDT 24 Jul 09 06:24:57 PM PDT 24 328859357 ps
T851 /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1733099545 Jul 09 06:24:47 PM PDT 24 Jul 09 06:24:51 PM PDT 24 5509459650 ps
T852 /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3850124063 Jul 09 06:24:34 PM PDT 24 Jul 09 06:24:58 PM PDT 24 8337030384 ps
T853 /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2415498945 Jul 09 06:24:24 PM PDT 24 Jul 09 06:24:25 PM PDT 24 501141284 ps
T854 /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.1848325761 Jul 09 06:24:39 PM PDT 24 Jul 09 06:24:42 PM PDT 24 333464528 ps
T855 /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.238726266 Jul 09 06:24:03 PM PDT 24 Jul 09 06:24:05 PM PDT 24 429339319 ps
T856 /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2925975791 Jul 09 06:24:31 PM PDT 24 Jul 09 06:24:33 PM PDT 24 418549271 ps
T857 /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2017366626 Jul 09 06:24:31 PM PDT 24 Jul 09 06:24:34 PM PDT 24 527462228 ps
T858 /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.394835213 Jul 09 06:24:56 PM PDT 24 Jul 09 06:24:58 PM PDT 24 359659845 ps
T859 /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2104036246 Jul 09 06:24:30 PM PDT 24 Jul 09 06:24:35 PM PDT 24 2289948111 ps
T860 /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2847685548 Jul 09 06:24:13 PM PDT 24 Jul 09 06:24:16 PM PDT 24 454746597 ps
T861 /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1516398115 Jul 09 06:24:42 PM PDT 24 Jul 09 06:24:44 PM PDT 24 410624219 ps
T862 /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1092401224 Jul 09 06:24:08 PM PDT 24 Jul 09 06:24:11 PM PDT 24 2242978191 ps
T863 /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3323866155 Jul 09 06:24:55 PM PDT 24 Jul 09 06:24:57 PM PDT 24 328944495 ps
T864 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3599340382 Jul 09 06:24:08 PM PDT 24 Jul 09 06:24:11 PM PDT 24 586725749 ps
T865 /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.727844879 Jul 09 06:24:54 PM PDT 24 Jul 09 06:24:55 PM PDT 24 324449212 ps
T866 /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.624887540 Jul 09 06:24:58 PM PDT 24 Jul 09 06:25:00 PM PDT 24 423471748 ps
T867 /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3281982993 Jul 09 06:24:03 PM PDT 24 Jul 09 06:24:05 PM PDT 24 645001604 ps
T868 /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2465430058 Jul 09 06:24:05 PM PDT 24 Jul 09 06:24:17 PM PDT 24 5123064961 ps
T869 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3488918571 Jul 09 06:24:24 PM PDT 24 Jul 09 06:24:26 PM PDT 24 427685996 ps
T870 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3101698379 Jul 09 06:24:08 PM PDT 24 Jul 09 06:25:04 PM PDT 24 26334578049 ps
T871 /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2619747291 Jul 09 06:24:58 PM PDT 24 Jul 09 06:25:00 PM PDT 24 563605474 ps
T872 /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1785525286 Jul 09 06:24:54 PM PDT 24 Jul 09 06:24:56 PM PDT 24 419596804 ps
T873 /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.303961743 Jul 09 06:24:22 PM PDT 24 Jul 09 06:24:25 PM PDT 24 476736127 ps
T874 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2816764324 Jul 09 06:24:37 PM PDT 24 Jul 09 06:24:38 PM PDT 24 594231646 ps
T875 /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.4017001319 Jul 09 06:24:10 PM PDT 24 Jul 09 06:24:12 PM PDT 24 390927617 ps
T876 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1758366500 Jul 09 06:24:08 PM PDT 24 Jul 09 06:24:10 PM PDT 24 355820032 ps
T877 /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1282478086 Jul 09 06:24:08 PM PDT 24 Jul 09 06:24:12 PM PDT 24 886041691 ps
T878 /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1982494400 Jul 09 06:24:44 PM PDT 24 Jul 09 06:24:53 PM PDT 24 8638770667 ps
T119 /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1583616405 Jul 09 06:24:26 PM PDT 24 Jul 09 06:24:29 PM PDT 24 537386804 ps
T879 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2472408227 Jul 09 06:24:25 PM PDT 24 Jul 09 06:24:27 PM PDT 24 593308896 ps
T880 /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.4286378540 Jul 09 06:24:22 PM PDT 24 Jul 09 06:24:23 PM PDT 24 325390281 ps
T881 /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3372065583 Jul 09 06:24:15 PM PDT 24 Jul 09 06:24:16 PM PDT 24 316488701 ps
T882 /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1735797789 Jul 09 06:24:54 PM PDT 24 Jul 09 06:24:56 PM PDT 24 320332719 ps
T120 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3855831630 Jul 09 06:24:10 PM PDT 24 Jul 09 06:24:13 PM PDT 24 1094737879 ps
T883 /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1337699078 Jul 09 06:24:41 PM PDT 24 Jul 09 06:24:44 PM PDT 24 629770439 ps
T884 /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2742676094 Jul 09 06:24:10 PM PDT 24 Jul 09 06:24:23 PM PDT 24 4468638663 ps
T885 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2755684945 Jul 09 06:24:11 PM PDT 24 Jul 09 06:24:14 PM PDT 24 430204513 ps
T886 /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.454171031 Jul 09 06:24:06 PM PDT 24 Jul 09 06:24:16 PM PDT 24 8224842590 ps
T887 /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1017240832 Jul 09 06:24:20 PM PDT 24 Jul 09 06:24:23 PM PDT 24 358174209 ps
T888 /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3552261706 Jul 09 06:24:22 PM PDT 24 Jul 09 06:24:27 PM PDT 24 1937409643 ps
T889 /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3997872522 Jul 09 06:24:36 PM PDT 24 Jul 09 06:24:49 PM PDT 24 4745505963 ps
T121 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.627484481 Jul 09 06:24:32 PM PDT 24 Jul 09 06:24:34 PM PDT 24 583959368 ps
T890 /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.95928606 Jul 09 06:24:25 PM PDT 24 Jul 09 06:24:27 PM PDT 24 468474387 ps
T891 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.979313207 Jul 09 06:24:18 PM PDT 24 Jul 09 06:24:20 PM PDT 24 392017806 ps
T892 /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2202499820 Jul 09 06:24:43 PM PDT 24 Jul 09 06:24:45 PM PDT 24 527010899 ps
T893 /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3783208316 Jul 09 06:24:55 PM PDT 24 Jul 09 06:24:57 PM PDT 24 366157169 ps
T894 /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2815844573 Jul 09 06:24:46 PM PDT 24 Jul 09 06:24:48 PM PDT 24 471406623 ps
T895 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3286384810 Jul 09 06:24:11 PM PDT 24 Jul 09 06:24:13 PM PDT 24 463469411 ps
T896 /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2273510274 Jul 09 06:24:38 PM PDT 24 Jul 09 06:24:40 PM PDT 24 405933899 ps
T897 /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1329438952 Jul 09 06:24:39 PM PDT 24 Jul 09 06:24:53 PM PDT 24 4745048523 ps
T898 /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3742674892 Jul 09 06:24:45 PM PDT 24 Jul 09 06:24:47 PM PDT 24 512597024 ps
T899 /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2050702368 Jul 09 06:24:53 PM PDT 24 Jul 09 06:24:54 PM PDT 24 355367816 ps
T900 /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2136347205 Jul 09 06:24:20 PM PDT 24 Jul 09 06:24:22 PM PDT 24 506235064 ps
T901 /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1690071117 Jul 09 06:24:26 PM PDT 24 Jul 09 06:24:28 PM PDT 24 592041033 ps
T123 /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1829402654 Jul 09 06:24:35 PM PDT 24 Jul 09 06:24:36 PM PDT 24 399578556 ps
T902 /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.210959643 Jul 09 06:24:12 PM PDT 24 Jul 09 06:24:22 PM PDT 24 4643693228 ps
T903 /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3764004716 Jul 09 06:24:54 PM PDT 24 Jul 09 06:24:55 PM PDT 24 482336383 ps
T904 /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1835549399 Jul 09 06:24:56 PM PDT 24 Jul 09 06:24:58 PM PDT 24 416664621 ps
T122 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2840387390 Jul 09 06:24:09 PM PDT 24 Jul 09 06:24:12 PM PDT 24 610964323 ps
T905 /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.455182617 Jul 09 06:24:37 PM PDT 24 Jul 09 06:24:39 PM PDT 24 680284544 ps
T906 /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.4209691680 Jul 09 06:24:32 PM PDT 24 Jul 09 06:24:34 PM PDT 24 417507961 ps
T907 /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2539098406 Jul 09 06:24:22 PM PDT 24 Jul 09 06:24:24 PM PDT 24 602227947 ps
T908 /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2272110481 Jul 09 06:24:55 PM PDT 24 Jul 09 06:24:58 PM PDT 24 1110963606 ps
T909 /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.431478832 Jul 09 06:24:38 PM PDT 24 Jul 09 06:24:39 PM PDT 24 384316802 ps
T910 /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1617793733 Jul 09 06:24:08 PM PDT 24 Jul 09 06:24:10 PM PDT 24 607200447 ps
T911 /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.215776229 Jul 09 06:24:11 PM PDT 24 Jul 09 06:24:13 PM PDT 24 955699824 ps
T912 /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.713290526 Jul 09 06:24:39 PM PDT 24 Jul 09 06:24:51 PM PDT 24 4563267045 ps
T124 /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3508060589 Jul 09 06:24:10 PM PDT 24 Jul 09 06:24:13 PM PDT 24 790263391 ps
T913 /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3428143356 Jul 09 06:24:38 PM PDT 24 Jul 09 06:24:44 PM PDT 24 626590008 ps
T914 /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.4176929748 Jul 09 06:24:51 PM PDT 24 Jul 09 06:24:53 PM PDT 24 5996592806 ps
T915 /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1342864266 Jul 09 06:24:47 PM PDT 24 Jul 09 06:24:49 PM PDT 24 335048693 ps
T916 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3335136983 Jul 09 06:24:23 PM PDT 24 Jul 09 06:24:26 PM PDT 24 636713245 ps
T125 /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3879820364 Jul 09 06:24:46 PM PDT 24 Jul 09 06:24:48 PM PDT 24 599266345 ps
T917 /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3197524841 Jul 09 06:24:55 PM PDT 24 Jul 09 06:24:57 PM PDT 24 394107387 ps
T918 /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2794917715 Jul 09 06:24:28 PM PDT 24 Jul 09 06:24:42 PM PDT 24 2831449810 ps
T919 /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.4257602457 Jul 09 06:24:23 PM PDT 24 Jul 09 06:24:34 PM PDT 24 4267911833 ps
T351 /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1790219061 Jul 09 06:24:25 PM PDT 24 Jul 09 06:24:31 PM PDT 24 9024448603 ps

Test location /workspace/coverage/default/10.adc_ctrl_clock_gating.3549976117
Short name T3
Test name
Test status
Simulation time 521709568631 ps
CPU time 166.31 seconds
Started Jul 09 06:33:29 PM PDT 24
Finished Jul 09 06:36:17 PM PDT 24
Peak memory 201864 kb
Host smart-c985717a-8dec-47b0-98a2-0ce0a7e167ce
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549976117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_clock_gat
ing.3549976117
Directory /workspace/10.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all_with_rand_reset.386566779
Short name T35
Test name
Test status
Simulation time 609620025454 ps
CPU time 868.75 seconds
Started Jul 09 06:33:11 PM PDT 24
Finished Jul 09 06:47:51 PM PDT 24
Peak memory 210776 kb
Host smart-9e320ca3-7bfa-4807-ab84-78d963a93299
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386566779 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all_with_rand_reset.386566779
Directory /workspace/5.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_both.1488243574
Short name T111
Test name
Test status
Simulation time 517846705839 ps
CPU time 613.93 seconds
Started Jul 09 06:38:10 PM PDT 24
Finished Jul 09 06:48:26 PM PDT 24
Peak memory 201876 kb
Host smart-ea3bf4fb-fcaf-4921-abb7-2ae0cd0dbbc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488243574 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_both.1488243574
Directory /workspace/38.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all_with_rand_reset.2400148317
Short name T12
Test name
Test status
Simulation time 150354183961 ps
CPU time 466.93 seconds
Started Jul 09 06:33:28 PM PDT 24
Finished Jul 09 06:41:18 PM PDT 24
Peak memory 210700 kb
Host smart-623271c9-5336-4250-b2b9-480d072dc17b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400148317 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all_with_rand_reset.2400148317
Directory /workspace/9.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_both.1700745443
Short name T211
Test name
Test status
Simulation time 488902506693 ps
CPU time 1056.85 seconds
Started Jul 09 06:36:36 PM PDT 24
Finished Jul 09 06:54:14 PM PDT 24
Peak memory 201908 kb
Host smart-7b4f50f3-8f84-4f88-81d2-c226f51bd191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700745443 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_both.1700745443
Directory /workspace/30.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_clock_gating.1521102566
Short name T28
Test name
Test status
Simulation time 491374771719 ps
CPU time 1136.16 seconds
Started Jul 09 06:39:11 PM PDT 24
Finished Jul 09 06:58:08 PM PDT 24
Peak memory 201872 kb
Host smart-0df5ac72-1d87-4db5-8393-291643b3601b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521102566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_clock_gat
ing.1521102566
Directory /workspace/42.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all_with_rand_reset.4173689564
Short name T34
Test name
Test status
Simulation time 118531162206 ps
CPU time 121.31 seconds
Started Jul 09 06:34:15 PM PDT 24
Finished Jul 09 06:36:17 PM PDT 24
Peak memory 217920 kb
Host smart-7a345587-aa57-4b9a-90b4-1a35d31a20d9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173689564 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all_with_rand_reset.4173689564
Directory /workspace/18.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup.1762687510
Short name T152
Test name
Test status
Simulation time 588614615510 ps
CPU time 1377.88 seconds
Started Jul 09 06:33:14 PM PDT 24
Finished Jul 09 06:56:21 PM PDT 24
Peak memory 201920 kb
Host smart-e21ec927-30b6-4ebc-af4c-43a5749d4dd4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762687510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_
wakeup.1762687510
Directory /workspace/6.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_clock_gating.1937645499
Short name T142
Test name
Test status
Simulation time 504284558768 ps
CPU time 642.92 seconds
Started Jul 09 06:33:42 PM PDT 24
Finished Jul 09 06:44:27 PM PDT 24
Peak memory 201808 kb
Host smart-df374558-2063-4ce4-a118-7fb9a2cb77f5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937645499 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_clock_gat
ing.1937645499
Directory /workspace/13.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_errors.1559893982
Short name T66
Test name
Test status
Simulation time 655758030 ps
CPU time 3.14 seconds
Started Jul 09 06:24:38 PM PDT 24
Finished Jul 09 06:24:42 PM PDT 24
Peak memory 201732 kb
Host smart-119b2665-14e7-4e0c-b76c-854fe1091af0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559893982 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_errors.1559893982
Directory /workspace/14.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_both.2767249128
Short name T267
Test name
Test status
Simulation time 532494379135 ps
CPU time 801.25 seconds
Started Jul 09 06:33:50 PM PDT 24
Finished Jul 09 06:47:13 PM PDT 24
Peak memory 201880 kb
Host smart-16104bf1-2738-49bd-9864-d3c61a71085f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767249128 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_both.2767249128
Directory /workspace/14.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/0.adc_ctrl_sec_cm.4073214837
Short name T62
Test name
Test status
Simulation time 3684465528 ps
CPU time 9.31 seconds
Started Jul 09 06:32:42 PM PDT 24
Finished Jul 09 06:33:13 PM PDT 24
Peak memory 217156 kb
Host smart-00f1ce1b-335b-42d9-8def-33926c877cd3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073214837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_sec_cm.4073214837
Directory /workspace/0.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all.2178877421
Short name T49
Test name
Test status
Simulation time 581646881041 ps
CPU time 531.11 seconds
Started Jul 09 06:37:14 PM PDT 24
Finished Jul 09 06:46:07 PM PDT 24
Peak memory 202128 kb
Host smart-ce847f34-bea6-411a-b671-e81c75890f8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178877421 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all
.2178877421
Directory /workspace/33.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup.3708345245
Short name T254
Test name
Test status
Simulation time 355286117388 ps
CPU time 200.29 seconds
Started Jul 09 06:36:07 PM PDT 24
Finished Jul 09 06:39:29 PM PDT 24
Peak memory 201924 kb
Host smart-9af6e3d6-7b9a-4bbe-9949-5f8ea9d96256
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708345245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters
_wakeup.3708345245
Directory /workspace/28.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt.1520607732
Short name T5
Test name
Test status
Simulation time 161693864274 ps
CPU time 355.28 seconds
Started Jul 09 06:33:09 PM PDT 24
Finished Jul 09 06:39:16 PM PDT 24
Peak memory 201812 kb
Host smart-daeaeee9-971c-4c34-984b-a6b44b5d5c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520607732 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrupt.1520607732
Directory /workspace/5.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_bit_bash.493560979
Short name T55
Test name
Test status
Simulation time 50525583128 ps
CPU time 77.39 seconds
Started Jul 09 06:24:06 PM PDT 24
Finished Jul 09 06:25:24 PM PDT 24
Peak memory 201840 kb
Host smart-01617b9f-5079-493d-9d67-8743af67f303
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493560979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_bit_b
ash.493560979
Directory /workspace/0.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/16.adc_ctrl_clock_gating.2548657525
Short name T289
Test name
Test status
Simulation time 501337550853 ps
CPU time 155.07 seconds
Started Jul 09 06:34:01 PM PDT 24
Finished Jul 09 06:36:38 PM PDT 24
Peak memory 201952 kb
Host smart-79141641-3d03-45c0-86ef-45ac9d3e72ab
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548657525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_clock_gat
ing.2548657525
Directory /workspace/16.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all_with_rand_reset.2799510071
Short name T15
Test name
Test status
Simulation time 174620472773 ps
CPU time 194.48 seconds
Started Jul 09 06:37:29 PM PDT 24
Finished Jul 09 06:40:44 PM PDT 24
Peak memory 217856 kb
Host smart-dee3fd70-2184-47d1-a762-6c7c1ff63533
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799510071 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all_with_rand_reset.2799510071
Directory /workspace/35.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_both.1430371647
Short name T217
Test name
Test status
Simulation time 370265481373 ps
CPU time 294.58 seconds
Started Jul 09 06:39:52 PM PDT 24
Finished Jul 09 06:44:49 PM PDT 24
Peak memory 201940 kb
Host smart-8032deec-37c2-433d-9a97-6a49a46730de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430371647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_both.1430371647
Directory /workspace/46.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_both.3258297386
Short name T151
Test name
Test status
Simulation time 564813163245 ps
CPU time 1269.59 seconds
Started Jul 09 06:33:00 PM PDT 24
Finished Jul 09 06:54:25 PM PDT 24
Peak memory 201916 kb
Host smart-28199d7c-e792-40ec-864d-661ce66f6904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258297386 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_both.3258297386
Directory /workspace/3.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup.850065586
Short name T210
Test name
Test status
Simulation time 584260389185 ps
CPU time 1311.15 seconds
Started Jul 09 06:37:44 PM PDT 24
Finished Jul 09 06:59:37 PM PDT 24
Peak memory 201916 kb
Host smart-fbf3c6ac-b1ec-415b-8c2e-5ac4b3fc36b6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850065586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_
wakeup.850065586
Directory /workspace/36.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_both.2896486902
Short name T208
Test name
Test status
Simulation time 162802271556 ps
CPU time 362.64 seconds
Started Jul 09 06:39:32 PM PDT 24
Finished Jul 09 06:45:36 PM PDT 24
Peak memory 201928 kb
Host smart-7ed2a2ec-93eb-4192-9754-7c757389bf04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896486902 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_both.2896486902
Directory /workspace/44.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/46.adc_ctrl_clock_gating.1393372849
Short name T272
Test name
Test status
Simulation time 391352106133 ps
CPU time 221.5 seconds
Started Jul 09 06:39:52 PM PDT 24
Finished Jul 09 06:43:34 PM PDT 24
Peak memory 201896 kb
Host smart-bcfffa90-c6cc-4e58-8fdc-858691dfd0ef
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393372849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_clock_gat
ing.1393372849
Directory /workspace/46.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/10.adc_ctrl_alert_test.3084511521
Short name T71
Test name
Test status
Simulation time 526533125 ps
CPU time 1.81 seconds
Started Jul 09 06:33:34 PM PDT 24
Finished Jul 09 06:33:38 PM PDT 24
Peak memory 201644 kb
Host smart-454ca490-717f-4797-9945-eef9af97ea3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084511521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_alert_test.3084511521
Directory /workspace/10.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_clock_gating.2705749729
Short name T335
Test name
Test status
Simulation time 555196472099 ps
CPU time 344.48 seconds
Started Jul 09 06:40:12 PM PDT 24
Finished Jul 09 06:45:58 PM PDT 24
Peak memory 201968 kb
Host smart-caa1488d-34f0-42cf-ad01-372a17111b76
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705749729 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_clock_gat
ing.2705749729
Directory /workspace/48.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt.2470017578
Short name T242
Test name
Test status
Simulation time 488542544626 ps
CPU time 598.65 seconds
Started Jul 09 06:34:29 PM PDT 24
Finished Jul 09 06:44:29 PM PDT 24
Peak memory 202148 kb
Host smart-79fc4f62-6d7c-41ef-9100-7eb056b99389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470017578 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interrupt.2470017578
Directory /workspace/20.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup_fixed.769316734
Short name T42
Test name
Test status
Simulation time 203247821017 ps
CPU time 114.92 seconds
Started Jul 09 06:33:28 PM PDT 24
Finished Jul 09 06:35:25 PM PDT 24
Peak memory 201916 kb
Host smart-20061b18-c8a7-4aa1-a3ad-2dc5aa0a375b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769316734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.
adc_ctrl_filters_wakeup_fixed.769316734
Directory /workspace/10.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all_with_rand_reset.4062814234
Short name T136
Test name
Test status
Simulation time 80145437222 ps
CPU time 91.85 seconds
Started Jul 09 06:37:18 PM PDT 24
Finished Jul 09 06:38:53 PM PDT 24
Peak memory 218144 kb
Host smart-8f469768-b68f-440c-ae50-b76be1362f80
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062814234 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all_with_rand_reset.4062814234
Directory /workspace/34.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all_with_rand_reset.2576961014
Short name T18
Test name
Test status
Simulation time 282024036223 ps
CPU time 309.79 seconds
Started Jul 09 06:32:58 PM PDT 24
Finished Jul 09 06:38:24 PM PDT 24
Peak memory 212196 kb
Host smart-dd08cd83-932f-4f3e-ad4f-a6ce24e5ce62
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576961014 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all_with_rand_reset.2576961014
Directory /workspace/2.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_both.23463977
Short name T248
Test name
Test status
Simulation time 361074999977 ps
CPU time 467.67 seconds
Started Jul 09 06:40:03 PM PDT 24
Finished Jul 09 06:47:52 PM PDT 24
Peak memory 201892 kb
Host smart-be38709e-3584-4b28-8800-f1ef6c0e01b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23463977 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_both.23463977
Directory /workspace/47.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all.1687587963
Short name T153
Test name
Test status
Simulation time 346910857008 ps
CPU time 154.68 seconds
Started Jul 09 06:33:03 PM PDT 24
Finished Jul 09 06:35:51 PM PDT 24
Peak memory 201756 kb
Host smart-769dd9da-e263-4416-a952-f9546061e9f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687587963 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all.
1687587963
Directory /workspace/3.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_intg_err.423407983
Short name T353
Test name
Test status
Simulation time 8611899236 ps
CPU time 22.83 seconds
Started Jul 09 06:24:38 PM PDT 24
Finished Jul 09 06:25:02 PM PDT 24
Peak memory 201828 kb
Host smart-eebb8146-4094-4633-928f-007b9e5cdf41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423407983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_in
tg_err.423407983
Directory /workspace/16.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_both.1689898800
Short name T228
Test name
Test status
Simulation time 182712119664 ps
CPU time 67.46 seconds
Started Jul 09 06:34:10 PM PDT 24
Finished Jul 09 06:35:20 PM PDT 24
Peak memory 201972 kb
Host smart-979d42bf-b1e9-4906-bdb4-e185e4a98df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689898800 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_both.1689898800
Directory /workspace/17.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/33.adc_ctrl_clock_gating.815595089
Short name T232
Test name
Test status
Simulation time 493803607064 ps
CPU time 554.97 seconds
Started Jul 09 06:37:06 PM PDT 24
Finished Jul 09 06:46:22 PM PDT 24
Peak memory 202120 kb
Host smart-613a1b35-8977-4e8a-8f18-790304563936
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815595089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_clock_gati
ng.815595089
Directory /workspace/33.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/34.adc_ctrl_clock_gating.3015036053
Short name T92
Test name
Test status
Simulation time 178699561067 ps
CPU time 394.94 seconds
Started Jul 09 06:37:21 PM PDT 24
Finished Jul 09 06:43:58 PM PDT 24
Peak memory 201912 kb
Host smart-c3ea6b6d-c650-488d-b259-982ce812089c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015036053 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_clock_gat
ing.3015036053
Directory /workspace/34.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all.278960762
Short name T236
Test name
Test status
Simulation time 548255813148 ps
CPU time 1164.28 seconds
Started Jul 09 06:35:18 PM PDT 24
Finished Jul 09 06:54:45 PM PDT 24
Peak memory 201956 kb
Host smart-34179bf6-d23a-476f-b096-d399c90b4d80
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278960762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all.
278960762
Directory /workspace/23.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all_with_rand_reset.2557836643
Short name T239
Test name
Test status
Simulation time 170243026215 ps
CPU time 90.83 seconds
Started Jul 09 06:33:52 PM PDT 24
Finished Jul 09 06:35:24 PM PDT 24
Peak memory 210212 kb
Host smart-3322f61f-a282-4bd1-b041-490c5d619f9b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557836643 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all_with_rand_reset.2557836643
Directory /workspace/14.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_clock_gating.88844179
Short name T300
Test name
Test status
Simulation time 536662763110 ps
CPU time 768.58 seconds
Started Jul 09 06:36:06 PM PDT 24
Finished Jul 09 06:48:56 PM PDT 24
Peak memory 201952 kb
Host smart-aef1dcbf-f624-48b6-88af-bc1d19265f00
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88844179 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_ga
ting_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_clock_gatin
g.88844179
Directory /workspace/28.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup.3678846251
Short name T278
Test name
Test status
Simulation time 370922329034 ps
CPU time 439.15 seconds
Started Jul 09 06:33:56 PM PDT 24
Finished Jul 09 06:41:18 PM PDT 24
Peak memory 201948 kb
Host smart-54b55850-5fa6-493e-806b-13aed80f86f3
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678846251 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters
_wakeup.3678846251
Directory /workspace/15.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_both.2439029872
Short name T263
Test name
Test status
Simulation time 416397789318 ps
CPU time 961.97 seconds
Started Jul 09 06:35:46 PM PDT 24
Finished Jul 09 06:51:49 PM PDT 24
Peak memory 202016 kb
Host smart-a7776cd9-7169-4d99-80d5-3fe53a9ccb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439029872 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_both.2439029872
Directory /workspace/26.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_clock_gating.2001562973
Short name T301
Test name
Test status
Simulation time 523344402284 ps
CPU time 458.08 seconds
Started Jul 09 06:35:24 PM PDT 24
Finished Jul 09 06:43:03 PM PDT 24
Peak memory 201932 kb
Host smart-f33a8dd4-d676-458f-b7a3-30e88db947e8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001562973 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_clock_gat
ing.2001562973
Directory /workspace/24.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all_with_rand_reset.1893808900
Short name T16
Test name
Test status
Simulation time 351430662162 ps
CPU time 185.87 seconds
Started Jul 09 06:33:25 PM PDT 24
Finished Jul 09 06:36:34 PM PDT 24
Peak memory 210544 kb
Host smart-33da77d7-377a-44d8-b561-6ced1b2f1d03
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893808900 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all_with_rand_reset.1893808900
Directory /workspace/8.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all_with_rand_reset.2890904453
Short name T291
Test name
Test status
Simulation time 313367119752 ps
CPU time 181.68 seconds
Started Jul 09 06:33:22 PM PDT 24
Finished Jul 09 06:36:28 PM PDT 24
Peak memory 210652 kb
Host smart-709f9e5b-0d03-4eef-88f4-c9bf9f67b7f1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890904453 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all_with_rand_reset.2890904453
Directory /workspace/7.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_both.437180559
Short name T235
Test name
Test status
Simulation time 487456706983 ps
CPU time 297.83 seconds
Started Jul 09 06:37:18 PM PDT 24
Finished Jul 09 06:42:19 PM PDT 24
Peak memory 201948 kb
Host smart-8a03e577-a799-41a4-907c-b3b76276c786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437180559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_both.437180559
Directory /workspace/34.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all.2278969835
Short name T206
Test name
Test status
Simulation time 304825262281 ps
CPU time 880.74 seconds
Started Jul 09 06:33:33 PM PDT 24
Finished Jul 09 06:48:15 PM PDT 24
Peak memory 210436 kb
Host smart-6148d137-2b50-4514-91ca-eadb5119008e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278969835 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all
.2278969835
Directory /workspace/11.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all_with_rand_reset.1256821883
Short name T101
Test name
Test status
Simulation time 542441030734 ps
CPU time 240.39 seconds
Started Jul 09 06:33:37 PM PDT 24
Finished Jul 09 06:37:40 PM PDT 24
Peak memory 210516 kb
Host smart-ae408a26-14cd-477c-8273-2a92f5c2e1d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256821883 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all_with_rand_reset.1256821883
Directory /workspace/12.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt.3275229645
Short name T244
Test name
Test status
Simulation time 478361054942 ps
CPU time 1161.46 seconds
Started Jul 09 06:33:38 PM PDT 24
Finished Jul 09 06:53:02 PM PDT 24
Peak memory 201912 kb
Host smart-8407a4f8-5cd7-46a6-ab26-360d1bda1422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275229645 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interrupt.3275229645
Directory /workspace/13.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all.3068353691
Short name T243
Test name
Test status
Simulation time 578328436035 ps
CPU time 939.3 seconds
Started Jul 09 06:36:42 PM PDT 24
Finished Jul 09 06:52:23 PM PDT 24
Peak memory 210396 kb
Host smart-5fa7968d-8d0f-4034-9e81-c820d86df472
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068353691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all
.3068353691
Directory /workspace/30.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup.1367986478
Short name T298
Test name
Test status
Simulation time 348276256118 ps
CPU time 793.56 seconds
Started Jul 09 06:39:28 PM PDT 24
Finished Jul 09 06:52:43 PM PDT 24
Peak memory 201908 kb
Host smart-c4b9c87c-1dd6-4185-bd93-eba62888cddb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367986478 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters
_wakeup.1367986478
Directory /workspace/44.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_rw.3024309901
Short name T112
Test name
Test status
Simulation time 309982281 ps
CPU time 1.19 seconds
Started Jul 09 06:24:09 PM PDT 24
Finished Jul 09 06:24:11 PM PDT 24
Peak memory 201524 kb
Host smart-4ac41802-50f5-4d22-b703-1841d4a7cd41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024309901 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_rw.3024309901
Directory /workspace/1.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_interrupt_fixed.3260107017
Short name T401
Test name
Test status
Simulation time 333663401346 ps
CPU time 732.6 seconds
Started Jul 09 06:33:35 PM PDT 24
Finished Jul 09 06:45:50 PM PDT 24
Peak memory 201960 kb
Host smart-84317673-ea53-46eb-993e-5381e10fd60f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260107017 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_interru
pt_fixed.3260107017
Directory /workspace/13.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_both.2490725442
Short name T344
Test name
Test status
Simulation time 535791529664 ps
CPU time 976.59 seconds
Started Jul 09 06:38:52 PM PDT 24
Finished Jul 09 06:55:10 PM PDT 24
Peak memory 201992 kb
Host smart-1e400332-9041-4fc1-85b4-b7c20c3def9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490725442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_both.2490725442
Directory /workspace/41.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup.1739552033
Short name T167
Test name
Test status
Simulation time 641459411343 ps
CPU time 136.55 seconds
Started Jul 09 06:33:38 PM PDT 24
Finished Jul 09 06:35:57 PM PDT 24
Peak memory 201976 kb
Host smart-bef4b60e-ac42-4db4-a7b5-b1a64f6fceca
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739552033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters
_wakeup.1739552033
Directory /workspace/11.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all.535134119
Short name T245
Test name
Test status
Simulation time 240976623191 ps
CPU time 729.42 seconds
Started Jul 09 06:34:04 PM PDT 24
Finished Jul 09 06:46:15 PM PDT 24
Peak memory 210432 kb
Host smart-daaa45df-1fe1-46a4-a6c9-d889f12af3c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535134119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all.
535134119
Directory /workspace/16.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all.3154888474
Short name T268
Test name
Test status
Simulation time 355762610373 ps
CPU time 786.05 seconds
Started Jul 09 06:36:51 PM PDT 24
Finished Jul 09 06:49:58 PM PDT 24
Peak memory 201932 kb
Host smart-ab57023c-cb56-4769-8523-3315816e9d17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154888474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all
.3154888474
Directory /workspace/31.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_both.3140215442
Short name T346
Test name
Test status
Simulation time 178020314151 ps
CPU time 399.14 seconds
Started Jul 09 06:33:33 PM PDT 24
Finished Jul 09 06:40:14 PM PDT 24
Peak memory 201932 kb
Host smart-36eff0b1-18b1-4727-9a02-ddf9c0a3c496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140215442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_both.3140215442
Directory /workspace/11.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_both.1643046151
Short name T330
Test name
Test status
Simulation time 327041784747 ps
CPU time 728.78 seconds
Started Jul 09 06:34:20 PM PDT 24
Finished Jul 09 06:46:31 PM PDT 24
Peak memory 201936 kb
Host smart-89b3f674-6a0e-4780-a4dd-5e2f3fcd947c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643046151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_both.1643046151
Directory /workspace/19.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup.1170825068
Short name T207
Test name
Test status
Simulation time 374176138259 ps
CPU time 427.25 seconds
Started Jul 09 06:36:22 PM PDT 24
Finished Jul 09 06:43:30 PM PDT 24
Peak memory 201984 kb
Host smart-ad2d0f6f-226d-4a41-a5b1-8de7984947ec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170825068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters
_wakeup.1170825068
Directory /workspace/29.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_both.1644361030
Short name T331
Test name
Test status
Simulation time 196217233117 ps
CPU time 435.34 seconds
Started Jul 09 06:37:04 PM PDT 24
Finished Jul 09 06:44:20 PM PDT 24
Peak memory 201932 kb
Host smart-029a324b-64a7-4bd1-a254-48a2feeeae57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644361030 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_both.1644361030
Directory /workspace/33.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all_with_rand_reset.706914700
Short name T97
Test name
Test status
Simulation time 597221776855 ps
CPU time 117.78 seconds
Started Jul 09 06:38:03 PM PDT 24
Finished Jul 09 06:40:02 PM PDT 24
Peak memory 210244 kb
Host smart-90763f65-4311-4ac5-aba3-fac57acf56b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706914700 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all_with_rand_reset.706914700
Directory /workspace/37.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all_with_rand_reset.2977795389
Short name T110
Test name
Test status
Simulation time 152903461197 ps
CPU time 97.56 seconds
Started Jul 09 06:33:07 PM PDT 24
Finished Jul 09 06:34:57 PM PDT 24
Peak memory 217860 kb
Host smart-6a173aa2-e2d9-4d3b-94fc-fb791b95b4d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977795389 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all_with_rand_reset.2977795389
Directory /workspace/4.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_clock_gating.603143628
Short name T295
Test name
Test status
Simulation time 520203900770 ps
CPU time 775.22 seconds
Started Jul 09 06:33:19 PM PDT 24
Finished Jul 09 06:46:20 PM PDT 24
Peak memory 201836 kb
Host smart-64c9f76a-7cdd-4c40-ad4e-e150d4524941
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603143628 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_clock_gatin
g.603143628
Directory /workspace/7.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_both.504575639
Short name T308
Test name
Test status
Simulation time 166854730763 ps
CPU time 103.77 seconds
Started Jul 09 06:33:40 PM PDT 24
Finished Jul 09 06:35:26 PM PDT 24
Peak memory 201868 kb
Host smart-87259889-5244-4079-9c70-3c08d53926e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504575639 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_both.504575639
Directory /workspace/13.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup.2659446047
Short name T314
Test name
Test status
Simulation time 170062236743 ps
CPU time 203.73 seconds
Started Jul 09 06:34:00 PM PDT 24
Finished Jul 09 06:37:26 PM PDT 24
Peak memory 201956 kb
Host smart-1b7bd271-edc9-4d37-a3f8-78f0293cb886
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659446047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters
_wakeup.2659446047
Directory /workspace/16.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup.182117329
Short name T318
Test name
Test status
Simulation time 529444361699 ps
CPU time 308.22 seconds
Started Jul 09 06:35:23 PM PDT 24
Finished Jul 09 06:40:32 PM PDT 24
Peak memory 201900 kb
Host smart-67116192-7e39-4b41-b462-74e0afe5b4c0
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182117329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_
wakeup.182117329
Directory /workspace/24.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/44.adc_ctrl_clock_gating.220412278
Short name T313
Test name
Test status
Simulation time 536520136752 ps
CPU time 366.51 seconds
Started Jul 09 06:39:28 PM PDT 24
Finished Jul 09 06:45:35 PM PDT 24
Peak memory 201892 kb
Host smart-e78f6b80-b310-4f91-b5f4-d2ca027ffc4c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220412278 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_clock_gati
ng.220412278
Directory /workspace/44.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all_with_rand_reset.2188735953
Short name T274
Test name
Test status
Simulation time 238382226706 ps
CPU time 190.45 seconds
Started Jul 09 06:40:03 PM PDT 24
Finished Jul 09 06:43:16 PM PDT 24
Peak memory 218204 kb
Host smart-649d8785-96d4-41af-926a-9b1c60d5ee05
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188735953 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all_with_rand_reset.2188735953
Directory /workspace/47.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_clock_gating.1796893049
Short name T231
Test name
Test status
Simulation time 319082521504 ps
CPU time 585.92 seconds
Started Jul 09 06:33:49 PM PDT 24
Finished Jul 09 06:43:37 PM PDT 24
Peak memory 201968 kb
Host smart-1b458fd5-6064-4d24-a7b2-a1a0a57b4540
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796893049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_clock_gat
ing.1796893049
Directory /workspace/14.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_fsm_reset.3322584524
Short name T201
Test name
Test status
Simulation time 130270073298 ps
CPU time 488.44 seconds
Started Jul 09 06:33:54 PM PDT 24
Finished Jul 09 06:42:04 PM PDT 24
Peak memory 202268 kb
Host smart-120293e9-de7a-455a-bdb7-28cb11d1d7ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322584524 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_fsm_reset.3322584524
Directory /workspace/15.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_both.1520249211
Short name T293
Test name
Test status
Simulation time 490921453666 ps
CPU time 317.2 seconds
Started Jul 09 06:34:43 PM PDT 24
Finished Jul 09 06:40:01 PM PDT 24
Peak memory 201932 kb
Host smart-5eade35a-9340-4a59-a8f6-0bdb4672c6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520249211 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_both.1520249211
Directory /workspace/21.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled.1013011798
Short name T333
Test name
Test status
Simulation time 495122784420 ps
CPU time 971.49 seconds
Started Jul 09 06:33:14 PM PDT 24
Finished Jul 09 06:49:34 PM PDT 24
Peak memory 201996 kb
Host smart-1c25511e-55d6-4dfa-828f-0f272e2c124b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013011798 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled.1013011798
Directory /workspace/6.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_stress_all.1849469004
Short name T204
Test name
Test status
Simulation time 279675095173 ps
CPU time 893.64 seconds
Started Jul 09 06:33:23 PM PDT 24
Finished Jul 09 06:48:21 PM PDT 24
Peak memory 210412 kb
Host smart-87b94761-df07-4a68-a815-0b134fc52b92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849469004 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_stress_all.
1849469004
Directory /workspace/8.adc_ctrl_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_intg_err.3525225275
Short name T74
Test name
Test status
Simulation time 8329359766 ps
CPU time 22.28 seconds
Started Jul 09 06:24:39 PM PDT 24
Finished Jul 09 06:25:02 PM PDT 24
Peak memory 201796 kb
Host smart-65ff191c-2f08-45ce-a546-78539b8c39a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525225275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_i
ntg_err.3525225275
Directory /workspace/12.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_intg_err.880816340
Short name T61
Test name
Test status
Simulation time 8038401405 ps
CPU time 21.12 seconds
Started Jul 09 06:24:10 PM PDT 24
Finished Jul 09 06:24:32 PM PDT 24
Peak memory 201828 kb
Host smart-153acb52-b6be-40e6-bf87-cacee161876a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880816340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_int
g_err.880816340
Directory /workspace/3.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_both.2247830790
Short name T83
Test name
Test status
Simulation time 346752676259 ps
CPU time 707.47 seconds
Started Jul 09 06:32:43 PM PDT 24
Finished Jul 09 06:44:51 PM PDT 24
Peak memory 201896 kb
Host smart-cf7d3ee7-5e71-49c6-852f-d965175bb9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247830790 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_both.2247830790
Directory /workspace/0.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all.2719576173
Short name T220
Test name
Test status
Simulation time 387826254123 ps
CPU time 767.86 seconds
Started Jul 09 06:32:53 PM PDT 24
Finished Jul 09 06:45:58 PM PDT 24
Peak memory 202200 kb
Host smart-18496897-848a-4d2d-96da-f9b96340f1eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719576173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all.
2719576173
Directory /workspace/1.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_wakeup.3583229016
Short name T325
Test name
Test status
Simulation time 185917427414 ps
CPU time 202.74 seconds
Started Jul 09 06:33:28 PM PDT 24
Finished Jul 09 06:36:53 PM PDT 24
Peak memory 201924 kb
Host smart-ce5355f3-8eb7-4e59-9a2d-ab419478fde4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583229016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters
_wakeup.3583229016
Directory /workspace/10.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/11.adc_ctrl_fsm_reset.3231397172
Short name T205
Test name
Test status
Simulation time 113982486884 ps
CPU time 575.08 seconds
Started Jul 09 06:33:38 PM PDT 24
Finished Jul 09 06:43:15 PM PDT 24
Peak memory 202308 kb
Host smart-51c43908-ea28-4f9f-9685-4fab243939b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231397172 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_fsm_reset.3231397172
Directory /workspace/11.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_clock_gating.2634852760
Short name T751
Test name
Test status
Simulation time 433965970543 ps
CPU time 155.39 seconds
Started Jul 09 06:32:53 PM PDT 24
Finished Jul 09 06:35:46 PM PDT 24
Peak memory 201920 kb
Host smart-026c72fd-1917-4d10-8fca-b8eb9d4b1ad1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634852760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_clock_gati
ng.2634852760
Directory /workspace/2.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup.3626350638
Short name T273
Test name
Test status
Simulation time 569024238646 ps
CPU time 324.48 seconds
Started Jul 09 06:34:29 PM PDT 24
Finished Jul 09 06:39:55 PM PDT 24
Peak memory 201904 kb
Host smart-63308e29-505f-49a9-bc7c-59cb50784e75
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626350638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters
_wakeup.3626350638
Directory /workspace/20.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup.2776457489
Short name T311
Test name
Test status
Simulation time 182946665825 ps
CPU time 79.6 seconds
Started Jul 09 06:36:45 PM PDT 24
Finished Jul 09 06:38:05 PM PDT 24
Peak memory 202008 kb
Host smart-27905980-f1d2-4b70-8c07-2d20a369a39c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776457489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters
_wakeup.2776457489
Directory /workspace/31.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup.3748161663
Short name T256
Test name
Test status
Simulation time 531281947448 ps
CPU time 629.56 seconds
Started Jul 09 06:38:17 PM PDT 24
Finished Jul 09 06:48:50 PM PDT 24
Peak memory 201924 kb
Host smart-b32808d2-3b45-404f-8526-0887f655a8f2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748161663 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters
_wakeup.3748161663
Directory /workspace/39.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt.739778857
Short name T177
Test name
Test status
Simulation time 500443566981 ps
CPU time 331.69 seconds
Started Jul 09 06:38:54 PM PDT 24
Finished Jul 09 06:44:27 PM PDT 24
Peak memory 201904 kb
Host smart-5ac2fb5d-422d-457e-a434-a3c0c3875042
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739778857 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interrupt.739778857
Directory /workspace/41.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup.2057396602
Short name T252
Test name
Test status
Simulation time 348250881428 ps
CPU time 208.03 seconds
Started Jul 09 06:38:53 PM PDT 24
Finished Jul 09 06:42:22 PM PDT 24
Peak memory 201968 kb
Host smart-39357b43-0754-410c-b611-6b7b7adbed6e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057396602 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters
_wakeup.2057396602
Directory /workspace/41.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all_with_rand_reset.2986858405
Short name T336
Test name
Test status
Simulation time 156275703871 ps
CPU time 370.89 seconds
Started Jul 09 06:40:27 PM PDT 24
Finished Jul 09 06:46:40 PM PDT 24
Peak memory 210968 kb
Host smart-021c4cc9-509a-4aa7-8a2e-b60491a752af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986858405 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all_with_rand_reset.2986858405
Directory /workspace/49.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt.456710493
Short name T334
Test name
Test status
Simulation time 321286340544 ps
CPU time 93.43 seconds
Started Jul 09 06:33:19 PM PDT 24
Finished Jul 09 06:34:59 PM PDT 24
Peak memory 201916 kb
Host smart-7ed5c5d2-d40c-4ba5-9fec-e01c844c2967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456710493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrupt.456710493
Directory /workspace/7.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_aliasing.1282478086
Short name T877
Test name
Test status
Simulation time 886041691 ps
CPU time 2.85 seconds
Started Jul 09 06:24:08 PM PDT 24
Finished Jul 09 06:24:12 PM PDT 24
Peak memory 201740 kb
Host smart-669885e0-57fb-4052-abf5-8f9d15d6124b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282478086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_alia
sing.1282478086
Directory /workspace/0.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_hw_reset.2847942951
Short name T133
Test name
Test status
Simulation time 1341426681 ps
CPU time 1.54 seconds
Started Jul 09 06:24:10 PM PDT 24
Finished Jul 09 06:24:12 PM PDT 24
Peak memory 201524 kb
Host smart-769ebcb2-9186-4e50-9995-a59d11ef7f3d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847942951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_hw_r
eset.2847942951
Directory /workspace/0.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_mem_rw_with_rand_reset.2753825402
Short name T65
Test name
Test status
Simulation time 764390825 ps
CPU time 1.17 seconds
Started Jul 09 06:24:03 PM PDT 24
Finished Jul 09 06:24:04 PM PDT 24
Peak memory 201540 kb
Host smart-bc804aaf-a163-452f-ace0-ccb849e57b13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753825402 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 0.adc_ctrl_csr_mem_rw_with_rand_reset.2753825402
Directory /workspace/0.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_csr_rw.905108631
Short name T114
Test name
Test status
Simulation time 336477394 ps
CPU time 1.18 seconds
Started Jul 09 06:24:10 PM PDT 24
Finished Jul 09 06:24:11 PM PDT 24
Peak memory 201524 kb
Host smart-658f52d0-a79b-45fc-99fa-a7b88b62df11
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905108631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_csr_rw.905108631
Directory /workspace/0.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_intr_test.1070121066
Short name T808
Test name
Test status
Simulation time 375809613 ps
CPU time 0.89 seconds
Started Jul 09 06:24:06 PM PDT 24
Finished Jul 09 06:24:07 PM PDT 24
Peak memory 201428 kb
Host smart-955e357e-bbd1-4ad8-8d21-edf65cbbfec2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070121066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_intr_test.1070121066
Directory /workspace/0.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_same_csr_outstanding.2465430058
Short name T868
Test name
Test status
Simulation time 5123064961 ps
CPU time 11.68 seconds
Started Jul 09 06:24:05 PM PDT 24
Finished Jul 09 06:24:17 PM PDT 24
Peak memory 201832 kb
Host smart-b99d7df0-e989-421c-9e47-3653eca204ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465430058 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_c
trl_same_csr_outstanding.2465430058
Directory /workspace/0.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_errors.2210998343
Short name T60
Test name
Test status
Simulation time 746455479 ps
CPU time 2.46 seconds
Started Jul 09 06:24:06 PM PDT 24
Finished Jul 09 06:24:09 PM PDT 24
Peak memory 218132 kb
Host smart-f57a060d-585c-4890-9676-71062b44fb99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210998343 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_errors.2210998343
Directory /workspace/0.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.adc_ctrl_tl_intg_err.454171031
Short name T886
Test name
Test status
Simulation time 8224842590 ps
CPU time 9.75 seconds
Started Jul 09 06:24:06 PM PDT 24
Finished Jul 09 06:24:16 PM PDT 24
Peak memory 201720 kb
Host smart-cde7cc33-01e0-42b1-b53d-481f14349203
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454171031 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_tl_int
g_err.454171031
Directory /workspace/0.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_aliasing.2840387390
Short name T122
Test name
Test status
Simulation time 610964323 ps
CPU time 2.57 seconds
Started Jul 09 06:24:09 PM PDT 24
Finished Jul 09 06:24:12 PM PDT 24
Peak memory 201744 kb
Host smart-2661a1b2-8265-4493-bc61-6fdd41658dc0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840387390 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_alia
sing.2840387390
Directory /workspace/1.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_bit_bash.3101698379
Short name T870
Test name
Test status
Simulation time 26334578049 ps
CPU time 54.66 seconds
Started Jul 09 06:24:08 PM PDT 24
Finished Jul 09 06:25:04 PM PDT 24
Peak memory 201756 kb
Host smart-858eec86-c305-49ed-873b-a6fad73cd2ec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101698379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_bit_
bash.3101698379
Directory /workspace/1.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_hw_reset.3599340382
Short name T864
Test name
Test status
Simulation time 586725749 ps
CPU time 2.13 seconds
Started Jul 09 06:24:08 PM PDT 24
Finished Jul 09 06:24:11 PM PDT 24
Peak memory 201508 kb
Host smart-b01af234-dc00-4ba2-a31d-4bbf6e29f993
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599340382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_csr_hw_r
eset.3599340382
Directory /workspace/1.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_csr_mem_rw_with_rand_reset.1617793733
Short name T910
Test name
Test status
Simulation time 607200447 ps
CPU time 1.51 seconds
Started Jul 09 06:24:08 PM PDT 24
Finished Jul 09 06:24:10 PM PDT 24
Peak memory 201588 kb
Host smart-1deb9e80-7782-4a01-8cca-0b43fbe6c540
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617793733 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 1.adc_ctrl_csr_mem_rw_with_rand_reset.1617793733
Directory /workspace/1.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_intr_test.238726266
Short name T855
Test name
Test status
Simulation time 429339319 ps
CPU time 1.65 seconds
Started Jul 09 06:24:03 PM PDT 24
Finished Jul 09 06:24:05 PM PDT 24
Peak memory 201424 kb
Host smart-6545fe09-c45c-4987-9e3d-2731a9257c4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238726266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_intr_test.238726266
Directory /workspace/1.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_same_csr_outstanding.1092401224
Short name T862
Test name
Test status
Simulation time 2242978191 ps
CPU time 2.3 seconds
Started Jul 09 06:24:08 PM PDT 24
Finished Jul 09 06:24:11 PM PDT 24
Peak memory 201612 kb
Host smart-e2962f05-4dfa-4c2a-910b-aac223737592
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092401224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_c
trl_same_csr_outstanding.1092401224
Directory /workspace/1.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_errors.3281982993
Short name T867
Test name
Test status
Simulation time 645001604 ps
CPU time 1.5 seconds
Started Jul 09 06:24:03 PM PDT 24
Finished Jul 09 06:24:05 PM PDT 24
Peak memory 209764 kb
Host smart-f4357b33-77a3-4c8a-ad74-76a86efe9056
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281982993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_errors.3281982993
Directory /workspace/1.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.adc_ctrl_tl_intg_err.4010389863
Short name T56
Test name
Test status
Simulation time 4360114229 ps
CPU time 6.65 seconds
Started Jul 09 06:24:04 PM PDT 24
Finished Jul 09 06:24:11 PM PDT 24
Peak memory 201792 kb
Host smart-646e3c97-3366-41bc-a385-0d2407f95321
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010389863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_tl_in
tg_err.4010389863
Directory /workspace/1.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_mem_rw_with_rand_reset.4209691680
Short name T906
Test name
Test status
Simulation time 417507961 ps
CPU time 1.45 seconds
Started Jul 09 06:24:32 PM PDT 24
Finished Jul 09 06:24:34 PM PDT 24
Peak memory 201572 kb
Host smart-34a9b7a8-fd49-48e6-9785-4b5b1c38b926
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209691680 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 10.adc_ctrl_csr_mem_rw_with_rand_reset.4209691680
Directory /workspace/10.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_csr_rw.2925100738
Short name T118
Test name
Test status
Simulation time 384277761 ps
CPU time 0.99 seconds
Started Jul 09 06:24:37 PM PDT 24
Finished Jul 09 06:24:38 PM PDT 24
Peak memory 201508 kb
Host smart-31c9694c-1105-48c1-9fb4-ce63af9fb441
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925100738 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_csr_rw.2925100738
Directory /workspace/10.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_intr_test.2925975791
Short name T856
Test name
Test status
Simulation time 418549271 ps
CPU time 0.78 seconds
Started Jul 09 06:24:31 PM PDT 24
Finished Jul 09 06:24:33 PM PDT 24
Peak memory 201388 kb
Host smart-06b264ff-20da-466b-9046-cc53829fc930
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925975791 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_intr_test.2925975791
Directory /workspace/10.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_same_csr_outstanding.2104036246
Short name T859
Test name
Test status
Simulation time 2289948111 ps
CPU time 4.42 seconds
Started Jul 09 06:24:30 PM PDT 24
Finished Jul 09 06:24:35 PM PDT 24
Peak memory 201676 kb
Host smart-aec903d0-d975-4c8a-8158-33bff5c9a234
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104036246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_
ctrl_same_csr_outstanding.2104036246
Directory /workspace/10.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_errors.2017366626
Short name T857
Test name
Test status
Simulation time 527462228 ps
CPU time 2.31 seconds
Started Jul 09 06:24:31 PM PDT 24
Finished Jul 09 06:24:34 PM PDT 24
Peak memory 201768 kb
Host smart-afa615d6-e96c-43c0-861e-2e1f89020184
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017366626 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_errors.2017366626
Directory /workspace/10.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.adc_ctrl_tl_intg_err.4048777955
Short name T354
Test name
Test status
Simulation time 4595252961 ps
CPU time 4.19 seconds
Started Jul 09 06:24:31 PM PDT 24
Finished Jul 09 06:24:36 PM PDT 24
Peak memory 201816 kb
Host smart-2b3bac64-5393-4ea8-80fe-27711c4b9ea5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048777955 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_tl_i
ntg_err.4048777955
Directory /workspace/10.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_mem_rw_with_rand_reset.691871465
Short name T100
Test name
Test status
Simulation time 493620778 ps
CPU time 1.94 seconds
Started Jul 09 06:24:35 PM PDT 24
Finished Jul 09 06:24:37 PM PDT 24
Peak memory 201580 kb
Host smart-2e6082e2-1148-4025-9c50-c6f7723927ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691871465 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 11.adc_ctrl_csr_mem_rw_with_rand_reset.691871465
Directory /workspace/11.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_csr_rw.1829402654
Short name T123
Test name
Test status
Simulation time 399578556 ps
CPU time 0.95 seconds
Started Jul 09 06:24:35 PM PDT 24
Finished Jul 09 06:24:36 PM PDT 24
Peak memory 201516 kb
Host smart-17e8245c-b8ac-4379-b32a-8be1c62c363f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829402654 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_csr_rw.1829402654
Directory /workspace/11.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_intr_test.1848325761
Short name T854
Test name
Test status
Simulation time 333464528 ps
CPU time 0.98 seconds
Started Jul 09 06:24:39 PM PDT 24
Finished Jul 09 06:24:42 PM PDT 24
Peak memory 201392 kb
Host smart-c2f3bb49-846d-4b54-a97f-fc3bdc0989b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848325761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_intr_test.1848325761
Directory /workspace/11.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_same_csr_outstanding.1329438952
Short name T897
Test name
Test status
Simulation time 4745048523 ps
CPU time 11.92 seconds
Started Jul 09 06:24:39 PM PDT 24
Finished Jul 09 06:24:53 PM PDT 24
Peak memory 201796 kb
Host smart-5d8bfc35-f71d-4f43-8633-2357b0efd8d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329438952 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_
ctrl_same_csr_outstanding.1329438952
Directory /workspace/11.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_errors.608432246
Short name T836
Test name
Test status
Simulation time 646811627 ps
CPU time 1.8 seconds
Started Jul 09 06:24:32 PM PDT 24
Finished Jul 09 06:24:35 PM PDT 24
Peak memory 201804 kb
Host smart-e6125c53-954a-45e3-9d12-9abd075d7495
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608432246 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_errors.608432246
Directory /workspace/11.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.adc_ctrl_tl_intg_err.3850124063
Short name T852
Test name
Test status
Simulation time 8337030384 ps
CPU time 23.48 seconds
Started Jul 09 06:24:34 PM PDT 24
Finished Jul 09 06:24:58 PM PDT 24
Peak memory 201772 kb
Host smart-1eff64f1-4b11-47ea-ad7b-7c3e32951eea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850124063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_tl_i
ntg_err.3850124063
Directory /workspace/11.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_mem_rw_with_rand_reset.455182617
Short name T905
Test name
Test status
Simulation time 680284544 ps
CPU time 1.45 seconds
Started Jul 09 06:24:37 PM PDT 24
Finished Jul 09 06:24:39 PM PDT 24
Peak memory 201552 kb
Host smart-538833c4-edf3-46b9-a86c-6e1d676904f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455182617 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 12.adc_ctrl_csr_mem_rw_with_rand_reset.455182617
Directory /workspace/12.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_csr_rw.2816764324
Short name T874
Test name
Test status
Simulation time 594231646 ps
CPU time 1.02 seconds
Started Jul 09 06:24:37 PM PDT 24
Finished Jul 09 06:24:38 PM PDT 24
Peak memory 201516 kb
Host smart-813aa356-814f-4515-ad61-515f2b0fc618
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816764324 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_csr_rw.2816764324
Directory /workspace/12.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_intr_test.2273510274
Short name T896
Test name
Test status
Simulation time 405933899 ps
CPU time 0.83 seconds
Started Jul 09 06:24:38 PM PDT 24
Finished Jul 09 06:24:40 PM PDT 24
Peak memory 201388 kb
Host smart-ca287640-5c25-4dab-97f7-23e269579828
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273510274 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_intr_test.2273510274
Directory /workspace/12.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_same_csr_outstanding.3189125133
Short name T130
Test name
Test status
Simulation time 2723607331 ps
CPU time 3 seconds
Started Jul 09 06:24:34 PM PDT 24
Finished Jul 09 06:24:38 PM PDT 24
Peak memory 201624 kb
Host smart-63ff5f3e-72e2-45dd-bc4e-393c6a3e6f7f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189125133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_
ctrl_same_csr_outstanding.3189125133
Directory /workspace/12.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.adc_ctrl_tl_errors.4045427067
Short name T90
Test name
Test status
Simulation time 332506960 ps
CPU time 1.83 seconds
Started Jul 09 06:24:37 PM PDT 24
Finished Jul 09 06:24:40 PM PDT 24
Peak memory 201796 kb
Host smart-17c4e9dc-f756-4dd0-b511-30ae45c2a746
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045427067 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_tl_errors.4045427067
Directory /workspace/12.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_mem_rw_with_rand_reset.870309106
Short name T847
Test name
Test status
Simulation time 670010308 ps
CPU time 1.19 seconds
Started Jul 09 06:24:34 PM PDT 24
Finished Jul 09 06:24:36 PM PDT 24
Peak memory 209956 kb
Host smart-4a0811cc-e3aa-441d-97fc-0aa65c5254c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870309106 -assert nopostproc +UVM_TESTNAME=
adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 13.adc_ctrl_csr_mem_rw_with_rand_reset.870309106
Directory /workspace/13.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_csr_rw.3195647329
Short name T126
Test name
Test status
Simulation time 370134995 ps
CPU time 0.98 seconds
Started Jul 09 06:24:36 PM PDT 24
Finished Jul 09 06:24:37 PM PDT 24
Peak memory 201508 kb
Host smart-4e6d3132-d148-4bbf-b2c3-c0f78d13222b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195647329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_csr_rw.3195647329
Directory /workspace/13.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_intr_test.363629462
Short name T843
Test name
Test status
Simulation time 563591501 ps
CPU time 0.75 seconds
Started Jul 09 06:24:36 PM PDT 24
Finished Jul 09 06:24:37 PM PDT 24
Peak memory 201436 kb
Host smart-b94a03da-852b-4975-85c6-12c8eff7c9dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363629462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_intr_test.363629462
Directory /workspace/13.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_same_csr_outstanding.2830611241
Short name T54
Test name
Test status
Simulation time 5246320049 ps
CPU time 6.41 seconds
Started Jul 09 06:24:36 PM PDT 24
Finished Jul 09 06:24:42 PM PDT 24
Peak memory 201836 kb
Host smart-941d350c-1002-4579-9c72-66ce519b1099
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830611241 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_
ctrl_same_csr_outstanding.2830611241
Directory /workspace/13.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_errors.2868820396
Short name T70
Test name
Test status
Simulation time 485732734 ps
CPU time 2.01 seconds
Started Jul 09 06:24:36 PM PDT 24
Finished Jul 09 06:24:39 PM PDT 24
Peak memory 201804 kb
Host smart-e5e6cfc3-833d-484e-94e7-a2b8c37ae3fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868820396 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_errors.2868820396
Directory /workspace/13.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.adc_ctrl_tl_intg_err.3997872522
Short name T889
Test name
Test status
Simulation time 4745505963 ps
CPU time 12.28 seconds
Started Jul 09 06:24:36 PM PDT 24
Finished Jul 09 06:24:49 PM PDT 24
Peak memory 201796 kb
Host smart-e470a03d-01e3-41c0-9736-50684d3f64b3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997872522 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_tl_i
ntg_err.3997872522
Directory /workspace/13.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_mem_rw_with_rand_reset.4053434299
Short name T840
Test name
Test status
Simulation time 527118509 ps
CPU time 1.1 seconds
Started Jul 09 06:24:37 PM PDT 24
Finished Jul 09 06:24:40 PM PDT 24
Peak memory 201556 kb
Host smart-528f60b3-c5e0-441a-8108-160d6590a097
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053434299 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 14.adc_ctrl_csr_mem_rw_with_rand_reset.4053434299
Directory /workspace/14.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_csr_rw.3809160620
Short name T813
Test name
Test status
Simulation time 438486143 ps
CPU time 1.84 seconds
Started Jul 09 06:24:38 PM PDT 24
Finished Jul 09 06:24:41 PM PDT 24
Peak memory 201528 kb
Host smart-b28b3d4b-3223-41db-afc9-403004a46832
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809160620 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_csr_rw.3809160620
Directory /workspace/14.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_intr_test.431478832
Short name T909
Test name
Test status
Simulation time 384316802 ps
CPU time 0.81 seconds
Started Jul 09 06:24:38 PM PDT 24
Finished Jul 09 06:24:39 PM PDT 24
Peak memory 201412 kb
Host smart-2cd4bb51-051e-4d0e-b304-2a60627c6942
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431478832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_intr_test.431478832
Directory /workspace/14.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_same_csr_outstanding.2248727493
Short name T53
Test name
Test status
Simulation time 2552366946 ps
CPU time 2.27 seconds
Started Jul 09 06:24:40 PM PDT 24
Finished Jul 09 06:24:43 PM PDT 24
Peak memory 201892 kb
Host smart-df18605f-15a6-4084-ba7f-79c58728d8d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248727493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_
ctrl_same_csr_outstanding.2248727493
Directory /workspace/14.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.adc_ctrl_tl_intg_err.2306223073
Short name T838
Test name
Test status
Simulation time 8523850081 ps
CPU time 5.14 seconds
Started Jul 09 06:24:38 PM PDT 24
Finished Jul 09 06:24:45 PM PDT 24
Peak memory 201860 kb
Host smart-c4ab318a-f0dd-43ad-ac8e-e2a58c1ca6cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306223073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_tl_i
ntg_err.2306223073
Directory /workspace/14.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_mem_rw_with_rand_reset.1059457514
Short name T89
Test name
Test status
Simulation time 548608672 ps
CPU time 1.28 seconds
Started Jul 09 06:24:38 PM PDT 24
Finished Jul 09 06:24:40 PM PDT 24
Peak memory 201580 kb
Host smart-47d53499-ec37-4051-bcb2-c0cc3a762b02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059457514 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 15.adc_ctrl_csr_mem_rw_with_rand_reset.1059457514
Directory /workspace/15.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_csr_rw.1843176746
Short name T117
Test name
Test status
Simulation time 392677026 ps
CPU time 1.06 seconds
Started Jul 09 06:24:40 PM PDT 24
Finished Jul 09 06:24:42 PM PDT 24
Peak memory 201488 kb
Host smart-7ed5405f-802b-4444-bd62-68c2dde2fae4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1843176746 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_csr_rw.1843176746
Directory /workspace/15.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_intr_test.281034173
Short name T823
Test name
Test status
Simulation time 303817903 ps
CPU time 1.31 seconds
Started Jul 09 06:24:44 PM PDT 24
Finished Jul 09 06:24:46 PM PDT 24
Peak memory 201436 kb
Host smart-166ac3c5-d6db-4cbb-bffc-53ef65f17cc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281034173 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_intr_test.281034173
Directory /workspace/15.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_same_csr_outstanding.713290526
Short name T912
Test name
Test status
Simulation time 4563267045 ps
CPU time 10.87 seconds
Started Jul 09 06:24:39 PM PDT 24
Finished Jul 09 06:24:51 PM PDT 24
Peak memory 201860 kb
Host smart-f9ae0d63-d89d-4a31-865a-b134149527be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713290526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_c
trl_same_csr_outstanding.713290526
Directory /workspace/15.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_errors.3865498878
Short name T833
Test name
Test status
Simulation time 675444805 ps
CPU time 3.24 seconds
Started Jul 09 06:24:39 PM PDT 24
Finished Jul 09 06:24:44 PM PDT 24
Peak memory 209964 kb
Host smart-e619c986-7fc2-486f-a216-06972cfc0f82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865498878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_errors.3865498878
Directory /workspace/15.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.adc_ctrl_tl_intg_err.1982494400
Short name T878
Test name
Test status
Simulation time 8638770667 ps
CPU time 7.83 seconds
Started Jul 09 06:24:44 PM PDT 24
Finished Jul 09 06:24:53 PM PDT 24
Peak memory 201888 kb
Host smart-31182ee9-3135-42df-a950-ac3cc246c542
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982494400 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_tl_i
ntg_err.1982494400
Directory /workspace/15.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_mem_rw_with_rand_reset.2202499820
Short name T892
Test name
Test status
Simulation time 527010899 ps
CPU time 2.06 seconds
Started Jul 09 06:24:43 PM PDT 24
Finished Jul 09 06:24:45 PM PDT 24
Peak memory 201524 kb
Host smart-688b35cf-bf87-471e-af1f-2c6d6723ee83
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202499820 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 16.adc_ctrl_csr_mem_rw_with_rand_reset.2202499820
Directory /workspace/16.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_csr_rw.2987845432
Short name T844
Test name
Test status
Simulation time 531145416 ps
CPU time 1.87 seconds
Started Jul 09 06:24:43 PM PDT 24
Finished Jul 09 06:24:45 PM PDT 24
Peak memory 201688 kb
Host smart-2f5d0878-2a93-4240-b4b3-62761bfffecd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987845432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_csr_rw.2987845432
Directory /workspace/16.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_intr_test.1516398115
Short name T861
Test name
Test status
Simulation time 410624219 ps
CPU time 1.61 seconds
Started Jul 09 06:24:42 PM PDT 24
Finished Jul 09 06:24:44 PM PDT 24
Peak memory 201408 kb
Host smart-e65a5826-1aa7-43f9-bc09-a752f31027a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516398115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_intr_test.1516398115
Directory /workspace/16.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_same_csr_outstanding.2324053064
Short name T834
Test name
Test status
Simulation time 4798177699 ps
CPU time 4.21 seconds
Started Jul 09 06:24:41 PM PDT 24
Finished Jul 09 06:24:46 PM PDT 24
Peak memory 201760 kb
Host smart-c71c512a-b19d-44e5-bc5f-aaa775f57f2f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324053064 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_
ctrl_same_csr_outstanding.2324053064
Directory /workspace/16.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.adc_ctrl_tl_errors.3428143356
Short name T913
Test name
Test status
Simulation time 626590008 ps
CPU time 4.21 seconds
Started Jul 09 06:24:38 PM PDT 24
Finished Jul 09 06:24:44 PM PDT 24
Peak memory 209988 kb
Host smart-b03a6e8d-b990-4622-b34a-33b04b3c2cfa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428143356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_tl_errors.3428143356
Directory /workspace/16.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_mem_rw_with_rand_reset.3742674892
Short name T898
Test name
Test status
Simulation time 512597024 ps
CPU time 2.07 seconds
Started Jul 09 06:24:45 PM PDT 24
Finished Jul 09 06:24:47 PM PDT 24
Peak memory 201576 kb
Host smart-aec7b235-7d1a-4285-abb5-153aa644ddad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742674892 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 17.adc_ctrl_csr_mem_rw_with_rand_reset.3742674892
Directory /workspace/17.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_csr_rw.1856431526
Short name T116
Test name
Test status
Simulation time 397730029 ps
CPU time 1.11 seconds
Started Jul 09 06:24:45 PM PDT 24
Finished Jul 09 06:24:47 PM PDT 24
Peak memory 201476 kb
Host smart-3f9abc45-890c-48a2-a46c-eacafb34e141
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856431526 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_csr_rw.1856431526
Directory /workspace/17.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_intr_test.3852715993
Short name T810
Test name
Test status
Simulation time 303981731 ps
CPU time 1.02 seconds
Started Jul 09 06:24:44 PM PDT 24
Finished Jul 09 06:24:45 PM PDT 24
Peak memory 201404 kb
Host smart-e8195015-37e3-4a99-b968-0f4f39e2161f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852715993 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_intr_test.3852715993
Directory /workspace/17.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_same_csr_outstanding.3785966999
Short name T128
Test name
Test status
Simulation time 5214717575 ps
CPU time 20.75 seconds
Started Jul 09 06:24:43 PM PDT 24
Finished Jul 09 06:25:04 PM PDT 24
Peak memory 201808 kb
Host smart-240adca5-f95a-4843-8dbd-7874afd1f1ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785966999 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_
ctrl_same_csr_outstanding.3785966999
Directory /workspace/17.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_errors.3498108476
Short name T837
Test name
Test status
Simulation time 579193969 ps
CPU time 3.32 seconds
Started Jul 09 06:24:42 PM PDT 24
Finished Jul 09 06:24:46 PM PDT 24
Peak memory 210952 kb
Host smart-4b78b32f-2b3d-4c1d-a30b-bd904abf9daf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498108476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_errors.3498108476
Directory /workspace/17.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.adc_ctrl_tl_intg_err.4176929748
Short name T914
Test name
Test status
Simulation time 5996592806 ps
CPU time 2.44 seconds
Started Jul 09 06:24:51 PM PDT 24
Finished Jul 09 06:24:53 PM PDT 24
Peak memory 201848 kb
Host smart-b40eed06-fe1c-464e-a3f1-68bde2eddf7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176929748 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_tl_i
ntg_err.4176929748
Directory /workspace/17.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_mem_rw_with_rand_reset.2592282669
Short name T67
Test name
Test status
Simulation time 524634677 ps
CPU time 2.17 seconds
Started Jul 09 06:24:53 PM PDT 24
Finished Jul 09 06:24:56 PM PDT 24
Peak memory 201568 kb
Host smart-14328337-7346-44fd-832a-37847eba25be
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592282669 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 18.adc_ctrl_csr_mem_rw_with_rand_reset.2592282669
Directory /workspace/18.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_csr_rw.1904068068
Short name T831
Test name
Test status
Simulation time 455421854 ps
CPU time 1.81 seconds
Started Jul 09 06:24:54 PM PDT 24
Finished Jul 09 06:24:56 PM PDT 24
Peak memory 201468 kb
Host smart-08b3998c-3af8-42ed-b3ff-cbac4138027b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904068068 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_csr_rw.1904068068
Directory /workspace/18.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_intr_test.1342864266
Short name T915
Test name
Test status
Simulation time 335048693 ps
CPU time 1.44 seconds
Started Jul 09 06:24:47 PM PDT 24
Finished Jul 09 06:24:49 PM PDT 24
Peak memory 201448 kb
Host smart-6c8acf32-6e24-4844-945b-4908dc108855
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342864266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_intr_test.1342864266
Directory /workspace/18.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_same_csr_outstanding.1733099545
Short name T851
Test name
Test status
Simulation time 5509459650 ps
CPU time 3.11 seconds
Started Jul 09 06:24:47 PM PDT 24
Finished Jul 09 06:24:51 PM PDT 24
Peak memory 201840 kb
Host smart-6043a4a2-d8fc-4d19-a148-fce206e8f86f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733099545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_
ctrl_same_csr_outstanding.1733099545
Directory /workspace/18.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_errors.1337699078
Short name T883
Test name
Test status
Simulation time 629770439 ps
CPU time 2.35 seconds
Started Jul 09 06:24:41 PM PDT 24
Finished Jul 09 06:24:44 PM PDT 24
Peak memory 209996 kb
Host smart-93cccbd7-2fd8-440c-a1d4-f1ae128ee6b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337699078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_errors.1337699078
Directory /workspace/18.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.adc_ctrl_tl_intg_err.2626723600
Short name T839
Test name
Test status
Simulation time 7591107625 ps
CPU time 16.08 seconds
Started Jul 09 06:24:46 PM PDT 24
Finished Jul 09 06:25:03 PM PDT 24
Peak memory 201884 kb
Host smart-b7c64ab7-71d6-4ed4-a4f0-676eee8608b9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626723600 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_tl_i
ntg_err.2626723600
Directory /workspace/18.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_mem_rw_with_rand_reset.2484984326
Short name T820
Test name
Test status
Simulation time 395487734 ps
CPU time 1.13 seconds
Started Jul 09 06:24:48 PM PDT 24
Finished Jul 09 06:24:49 PM PDT 24
Peak memory 201584 kb
Host smart-e8189b6f-350f-4386-b0f0-9239965fd57f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484984326 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 19.adc_ctrl_csr_mem_rw_with_rand_reset.2484984326
Directory /workspace/19.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_csr_rw.3879820364
Short name T125
Test name
Test status
Simulation time 599266345 ps
CPU time 1.09 seconds
Started Jul 09 06:24:46 PM PDT 24
Finished Jul 09 06:24:48 PM PDT 24
Peak memory 201688 kb
Host smart-0ad7d915-c20e-4248-9463-e6ff85d471a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879820364 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_csr_rw.3879820364
Directory /workspace/19.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_intr_test.3197524841
Short name T917
Test name
Test status
Simulation time 394107387 ps
CPU time 1.56 seconds
Started Jul 09 06:24:55 PM PDT 24
Finished Jul 09 06:24:57 PM PDT 24
Peak memory 201388 kb
Host smart-93ab86db-8e4f-4761-a021-f484fba4a6b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197524841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_intr_test.3197524841
Directory /workspace/19.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_same_csr_outstanding.3076735137
Short name T827
Test name
Test status
Simulation time 5340826654 ps
CPU time 2.22 seconds
Started Jul 09 06:24:54 PM PDT 24
Finished Jul 09 06:24:57 PM PDT 24
Peak memory 201840 kb
Host smart-0f94d311-9d07-475f-aa19-1efb821211d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076735137 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_
ctrl_same_csr_outstanding.3076735137
Directory /workspace/19.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_errors.2272110481
Short name T908
Test name
Test status
Simulation time 1110963606 ps
CPU time 2.28 seconds
Started Jul 09 06:24:55 PM PDT 24
Finished Jul 09 06:24:58 PM PDT 24
Peak memory 201740 kb
Host smart-0cea01c2-1ccf-4e29-8f3a-4ba964817708
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272110481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_errors.2272110481
Directory /workspace/19.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.adc_ctrl_tl_intg_err.3951258200
Short name T826
Test name
Test status
Simulation time 4691427381 ps
CPU time 5.27 seconds
Started Jul 09 06:24:48 PM PDT 24
Finished Jul 09 06:24:53 PM PDT 24
Peak memory 201876 kb
Host smart-fa111130-6691-412e-9c44-05fd8f05e2ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951258200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_tl_i
ntg_err.3951258200
Directory /workspace/19.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_aliasing.215776229
Short name T911
Test name
Test status
Simulation time 955699824 ps
CPU time 1.8 seconds
Started Jul 09 06:24:11 PM PDT 24
Finished Jul 09 06:24:13 PM PDT 24
Peak memory 201704 kb
Host smart-960ef648-08d8-4a2d-9d37-31ea790df964
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215776229 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_alias
ing.215776229
Directory /workspace/2.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_bit_bash.3183013637
Short name T846
Test name
Test status
Simulation time 25940359853 ps
CPU time 16.22 seconds
Started Jul 09 06:24:08 PM PDT 24
Finished Jul 09 06:24:25 PM PDT 24
Peak memory 201832 kb
Host smart-cabfcb21-0a44-4717-9064-f0c5cf19dde7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183013637 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_bit_
bash.3183013637
Directory /workspace/2.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_hw_reset.2989705939
Short name T115
Test name
Test status
Simulation time 1034266848 ps
CPU time 2.93 seconds
Started Jul 09 06:24:09 PM PDT 24
Finished Jul 09 06:24:12 PM PDT 24
Peak memory 201488 kb
Host smart-81376f66-1549-42eb-b700-c527c2a0c957
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989705939 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_hw_r
eset.2989705939
Directory /workspace/2.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_mem_rw_with_rand_reset.1398694181
Short name T73
Test name
Test status
Simulation time 484964981 ps
CPU time 1.24 seconds
Started Jul 09 06:24:12 PM PDT 24
Finished Jul 09 06:24:14 PM PDT 24
Peak memory 209780 kb
Host smart-84e1ee11-0d73-4ec7-a4b2-136adb611174
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398694181 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 2.adc_ctrl_csr_mem_rw_with_rand_reset.1398694181
Directory /workspace/2.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_csr_rw.1758366500
Short name T876
Test name
Test status
Simulation time 355820032 ps
CPU time 1.63 seconds
Started Jul 09 06:24:08 PM PDT 24
Finished Jul 09 06:24:10 PM PDT 24
Peak memory 201492 kb
Host smart-caa5fdad-142d-4aae-ad52-63e779474900
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758366500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_csr_rw.1758366500
Directory /workspace/2.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_intr_test.4017001319
Short name T875
Test name
Test status
Simulation time 390927617 ps
CPU time 1.49 seconds
Started Jul 09 06:24:10 PM PDT 24
Finished Jul 09 06:24:12 PM PDT 24
Peak memory 201440 kb
Host smart-9e1dbae5-9bd8-4c73-b05e-e75cb8da84da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017001319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_intr_test.4017001319
Directory /workspace/2.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_same_csr_outstanding.2125791461
Short name T845
Test name
Test status
Simulation time 2019508743 ps
CPU time 8.33 seconds
Started Jul 09 06:24:14 PM PDT 24
Finished Jul 09 06:24:22 PM PDT 24
Peak memory 201504 kb
Host smart-17b78388-8024-401c-9f5c-7d5b29f34248
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125791461 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_c
trl_same_csr_outstanding.2125791461
Directory /workspace/2.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_errors.1152844174
Short name T849
Test name
Test status
Simulation time 757630239 ps
CPU time 2.41 seconds
Started Jul 09 06:24:09 PM PDT 24
Finished Jul 09 06:24:12 PM PDT 24
Peak memory 210012 kb
Host smart-755a1642-ff38-4bdd-810c-c4e2779af771
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152844174 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_errors.1152844174
Directory /workspace/2.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.adc_ctrl_tl_intg_err.2742676094
Short name T884
Test name
Test status
Simulation time 4468638663 ps
CPU time 11.96 seconds
Started Jul 09 06:24:10 PM PDT 24
Finished Jul 09 06:24:23 PM PDT 24
Peak memory 201856 kb
Host smart-cdb789c3-76a1-49ce-9acb-0835576093b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742676094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_tl_in
tg_err.2742676094
Directory /workspace/2.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.adc_ctrl_intr_test.4177809462
Short name T807
Test name
Test status
Simulation time 483317797 ps
CPU time 0.92 seconds
Started Jul 09 06:24:48 PM PDT 24
Finished Jul 09 06:24:50 PM PDT 24
Peak memory 201316 kb
Host smart-4335180b-8f45-4847-acab-072c619877ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177809462 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_intr_test.4177809462
Directory /workspace/20.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.adc_ctrl_intr_test.3323866155
Short name T863
Test name
Test status
Simulation time 328944495 ps
CPU time 0.85 seconds
Started Jul 09 06:24:55 PM PDT 24
Finished Jul 09 06:24:57 PM PDT 24
Peak memory 201392 kb
Host smart-e02011c6-c511-4147-84ea-874df913fd22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323866155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_intr_test.3323866155
Directory /workspace/21.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.adc_ctrl_intr_test.3093464161
Short name T828
Test name
Test status
Simulation time 354854950 ps
CPU time 0.77 seconds
Started Jul 09 06:24:46 PM PDT 24
Finished Jul 09 06:24:47 PM PDT 24
Peak memory 201444 kb
Host smart-b064e0a8-69f9-49a2-8f04-a09fc834342d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093464161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_intr_test.3093464161
Directory /workspace/22.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.adc_ctrl_intr_test.1011033577
Short name T821
Test name
Test status
Simulation time 304046738 ps
CPU time 1.37 seconds
Started Jul 09 06:24:47 PM PDT 24
Finished Jul 09 06:24:49 PM PDT 24
Peak memory 201448 kb
Host smart-1637cbf7-41b9-4a46-80e9-576f5ecd622d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011033577 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_intr_test.1011033577
Directory /workspace/23.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.adc_ctrl_intr_test.922973970
Short name T818
Test name
Test status
Simulation time 397886561 ps
CPU time 0.86 seconds
Started Jul 09 06:24:48 PM PDT 24
Finished Jul 09 06:24:50 PM PDT 24
Peak memory 201268 kb
Host smart-e594bae4-4635-4e0d-ba75-23db944b0bec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922973970 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_intr_test.922973970
Directory /workspace/24.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.adc_ctrl_intr_test.523110119
Short name T809
Test name
Test status
Simulation time 543527805 ps
CPU time 0.99 seconds
Started Jul 09 06:24:54 PM PDT 24
Finished Jul 09 06:24:56 PM PDT 24
Peak memory 201432 kb
Host smart-fad3b4a4-fe6a-42a0-8224-2338a028580d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523110119 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_intr_test.523110119
Directory /workspace/25.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.adc_ctrl_intr_test.2815844573
Short name T894
Test name
Test status
Simulation time 471406623 ps
CPU time 0.95 seconds
Started Jul 09 06:24:46 PM PDT 24
Finished Jul 09 06:24:48 PM PDT 24
Peak memory 201608 kb
Host smart-c0e1be84-5eb5-4338-ac0d-90de6b16def8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815844573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_intr_test.2815844573
Directory /workspace/26.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.adc_ctrl_intr_test.2415000505
Short name T848
Test name
Test status
Simulation time 455058050 ps
CPU time 0.93 seconds
Started Jul 09 06:24:54 PM PDT 24
Finished Jul 09 06:24:56 PM PDT 24
Peak memory 201420 kb
Host smart-f27bc2f9-e9dd-49e9-a833-89d7c36168b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415000505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_intr_test.2415000505
Directory /workspace/27.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.adc_ctrl_intr_test.1785525286
Short name T872
Test name
Test status
Simulation time 419596804 ps
CPU time 1.5 seconds
Started Jul 09 06:24:54 PM PDT 24
Finished Jul 09 06:24:56 PM PDT 24
Peak memory 201392 kb
Host smart-8b5f48fa-ba31-4ef4-879b-2812f0aed174
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785525286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_intr_test.1785525286
Directory /workspace/28.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.adc_ctrl_intr_test.1735797789
Short name T882
Test name
Test status
Simulation time 320332719 ps
CPU time 0.99 seconds
Started Jul 09 06:24:54 PM PDT 24
Finished Jul 09 06:24:56 PM PDT 24
Peak memory 201432 kb
Host smart-70f998b9-164a-495b-af2d-1cfcac070d4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735797789 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_intr_test.1735797789
Directory /workspace/29.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_aliasing.3508060589
Short name T124
Test name
Test status
Simulation time 790263391 ps
CPU time 2.26 seconds
Started Jul 09 06:24:10 PM PDT 24
Finished Jul 09 06:24:13 PM PDT 24
Peak memory 201744 kb
Host smart-f76cb878-2491-41b1-a136-133c243b459d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508060589 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_alia
sing.3508060589
Directory /workspace/3.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_bit_bash.3951260710
Short name T819
Test name
Test status
Simulation time 27669141271 ps
CPU time 18.96 seconds
Started Jul 09 06:24:16 PM PDT 24
Finished Jul 09 06:24:35 PM PDT 24
Peak memory 201848 kb
Host smart-414b389e-5aa1-4f83-b206-bac5e96c1a04
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951260710 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_bit_
bash.3951260710
Directory /workspace/3.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_hw_reset.3855831630
Short name T120
Test name
Test status
Simulation time 1094737879 ps
CPU time 1.89 seconds
Started Jul 09 06:24:10 PM PDT 24
Finished Jul 09 06:24:13 PM PDT 24
Peak memory 201468 kb
Host smart-3e7138e8-63cd-42b0-9d8e-bd6effb0700f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855831630 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_hw_r
eset.3855831630
Directory /workspace/3.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_mem_rw_with_rand_reset.2755684945
Short name T885
Test name
Test status
Simulation time 430204513 ps
CPU time 1.74 seconds
Started Jul 09 06:24:11 PM PDT 24
Finished Jul 09 06:24:14 PM PDT 24
Peak memory 201584 kb
Host smart-7001b63e-956f-46eb-920e-c0a1bb0f917d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755684945 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 3.adc_ctrl_csr_mem_rw_with_rand_reset.2755684945
Directory /workspace/3.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_csr_rw.3286384810
Short name T895
Test name
Test status
Simulation time 463469411 ps
CPU time 1.8 seconds
Started Jul 09 06:24:11 PM PDT 24
Finished Jul 09 06:24:13 PM PDT 24
Peak memory 201508 kb
Host smart-327d0b56-c363-4728-b485-345d96013fbb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286384810 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_csr_rw.3286384810
Directory /workspace/3.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_intr_test.3654405586
Short name T806
Test name
Test status
Simulation time 303146470 ps
CPU time 0.93 seconds
Started Jul 09 06:24:12 PM PDT 24
Finished Jul 09 06:24:13 PM PDT 24
Peak memory 201448 kb
Host smart-ce239ec5-438e-4161-9d34-b55e7ce9d5a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654405586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_intr_test.3654405586
Directory /workspace/3.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_same_csr_outstanding.210959643
Short name T902
Test name
Test status
Simulation time 4643693228 ps
CPU time 8.87 seconds
Started Jul 09 06:24:12 PM PDT 24
Finished Jul 09 06:24:22 PM PDT 24
Peak memory 201816 kb
Host smart-d0363d72-8608-4169-8053-44306d0ad277
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210959643 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=ad
c_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ct
rl_same_csr_outstanding.210959643
Directory /workspace/3.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.adc_ctrl_tl_errors.2847685548
Short name T860
Test name
Test status
Simulation time 454746597 ps
CPU time 1.79 seconds
Started Jul 09 06:24:13 PM PDT 24
Finished Jul 09 06:24:16 PM PDT 24
Peak memory 201764 kb
Host smart-accd5829-dc57-4905-99b7-1b0fc5135a8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847685548 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_tl_errors.2847685548
Directory /workspace/3.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.adc_ctrl_intr_test.1857700353
Short name T817
Test name
Test status
Simulation time 523179594 ps
CPU time 1.76 seconds
Started Jul 09 06:24:49 PM PDT 24
Finished Jul 09 06:24:51 PM PDT 24
Peak memory 201416 kb
Host smart-1aefbc6a-09a9-46fc-81cb-722f1e48a52f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857700353 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_intr_test.1857700353
Directory /workspace/30.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.adc_ctrl_intr_test.3526960497
Short name T815
Test name
Test status
Simulation time 291685887 ps
CPU time 1.29 seconds
Started Jul 09 06:24:55 PM PDT 24
Finished Jul 09 06:24:57 PM PDT 24
Peak memory 201432 kb
Host smart-1859d384-6973-4fa1-ae86-696741497203
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526960497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_intr_test.3526960497
Directory /workspace/31.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.adc_ctrl_intr_test.824730465
Short name T822
Test name
Test status
Simulation time 346785150 ps
CPU time 1.33 seconds
Started Jul 09 06:24:49 PM PDT 24
Finished Jul 09 06:24:50 PM PDT 24
Peak memory 201428 kb
Host smart-acb31619-8a74-4c87-809a-22cf4b3d4c92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824730465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_intr_test.824730465
Directory /workspace/32.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.adc_ctrl_intr_test.3503370646
Short name T832
Test name
Test status
Simulation time 510233284 ps
CPU time 1.7 seconds
Started Jul 09 06:24:50 PM PDT 24
Finished Jul 09 06:24:52 PM PDT 24
Peak memory 201448 kb
Host smart-583680d3-3634-4011-989b-fe45421a6d17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503370646 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_intr_test.3503370646
Directory /workspace/33.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.adc_ctrl_intr_test.3710004222
Short name T804
Test name
Test status
Simulation time 317172303 ps
CPU time 0.82 seconds
Started Jul 09 06:24:46 PM PDT 24
Finished Jul 09 06:24:48 PM PDT 24
Peak memory 201428 kb
Host smart-1ed1209e-4876-4530-b732-8d08cd315f08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710004222 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_intr_test.3710004222
Directory /workspace/34.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.adc_ctrl_intr_test.3764004716
Short name T903
Test name
Test status
Simulation time 482336383 ps
CPU time 0.88 seconds
Started Jul 09 06:24:54 PM PDT 24
Finished Jul 09 06:24:55 PM PDT 24
Peak memory 201440 kb
Host smart-cf76d196-860a-4bd5-802a-53b9833a909a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764004716 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_intr_test.3764004716
Directory /workspace/35.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.adc_ctrl_intr_test.2044325493
Short name T805
Test name
Test status
Simulation time 402202622 ps
CPU time 1.3 seconds
Started Jul 09 06:24:52 PM PDT 24
Finished Jul 09 06:24:54 PM PDT 24
Peak memory 201436 kb
Host smart-6952b33a-ed8e-4cc9-96c3-30d7d39ade0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044325493 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_intr_test.2044325493
Directory /workspace/36.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.adc_ctrl_intr_test.2050702368
Short name T899
Test name
Test status
Simulation time 355367816 ps
CPU time 0.88 seconds
Started Jul 09 06:24:53 PM PDT 24
Finished Jul 09 06:24:54 PM PDT 24
Peak memory 201416 kb
Host smart-9e696840-b70e-46dd-a505-947b1e99ca74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050702368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_intr_test.2050702368
Directory /workspace/37.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.adc_ctrl_intr_test.727844879
Short name T865
Test name
Test status
Simulation time 324449212 ps
CPU time 1.37 seconds
Started Jul 09 06:24:54 PM PDT 24
Finished Jul 09 06:24:55 PM PDT 24
Peak memory 201448 kb
Host smart-2ada9e77-16c8-4b63-aece-8cfd007fb27e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727844879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_intr_test.727844879
Directory /workspace/38.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.adc_ctrl_intr_test.394835213
Short name T858
Test name
Test status
Simulation time 359659845 ps
CPU time 1.01 seconds
Started Jul 09 06:24:56 PM PDT 24
Finished Jul 09 06:24:58 PM PDT 24
Peak memory 201388 kb
Host smart-c4c6be24-e6d4-47d1-ae77-4ac6f096c340
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394835213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_intr_test.394835213
Directory /workspace/39.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_aliasing.865699469
Short name T811
Test name
Test status
Simulation time 852410188 ps
CPU time 2.96 seconds
Started Jul 09 06:24:20 PM PDT 24
Finished Jul 09 06:24:24 PM PDT 24
Peak memory 201740 kb
Host smart-461a7a2a-4d2d-4a07-a2b5-f466c1af7868
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865699469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_alias
ing.865699469
Directory /workspace/4.adc_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_bit_bash.2794585279
Short name T113
Test name
Test status
Simulation time 52114135780 ps
CPU time 24.93 seconds
Started Jul 09 06:24:21 PM PDT 24
Finished Jul 09 06:24:46 PM PDT 24
Peak memory 201832 kb
Host smart-f160bcdf-8fcb-49ce-ae99-bcc7d8ffa8b4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794585279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_bit_
bash.2794585279
Directory /workspace/4.adc_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_hw_reset.1763745697
Short name T842
Test name
Test status
Simulation time 795877737 ps
CPU time 1.83 seconds
Started Jul 09 06:24:20 PM PDT 24
Finished Jul 09 06:24:23 PM PDT 24
Peak memory 201504 kb
Host smart-04f56f4c-c635-4585-b7e2-c20099f8a5c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763745697 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_hw_r
eset.1763745697
Directory /workspace/4.adc_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_mem_rw_with_rand_reset.2136347205
Short name T900
Test name
Test status
Simulation time 506235064 ps
CPU time 1.68 seconds
Started Jul 09 06:24:20 PM PDT 24
Finished Jul 09 06:24:22 PM PDT 24
Peak memory 201736 kb
Host smart-cff8d2d2-c9a6-48cd-a394-90afbfed337c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136347205 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 4.adc_ctrl_csr_mem_rw_with_rand_reset.2136347205
Directory /workspace/4.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_csr_rw.979313207
Short name T891
Test name
Test status
Simulation time 392017806 ps
CPU time 0.91 seconds
Started Jul 09 06:24:18 PM PDT 24
Finished Jul 09 06:24:20 PM PDT 24
Peak memory 201516 kb
Host smart-645fd15b-752b-4efc-a60b-412839fa7006
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979313207 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_csr_rw.979313207
Directory /workspace/4.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_intr_test.3372065583
Short name T881
Test name
Test status
Simulation time 316488701 ps
CPU time 0.92 seconds
Started Jul 09 06:24:15 PM PDT 24
Finished Jul 09 06:24:16 PM PDT 24
Peak memory 201424 kb
Host smart-16701d32-9692-4342-a847-e5ae731d6da9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372065583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_intr_test.3372065583
Directory /workspace/4.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_same_csr_outstanding.2253042132
Short name T127
Test name
Test status
Simulation time 3915143350 ps
CPU time 16.45 seconds
Started Jul 09 06:24:19 PM PDT 24
Finished Jul 09 06:24:35 PM PDT 24
Peak memory 201896 kb
Host smart-5a426f1c-c5bf-4cb2-a650-2b637bb3180e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253042132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_c
trl_same_csr_outstanding.2253042132
Directory /workspace/4.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_errors.111211647
Short name T829
Test name
Test status
Simulation time 413557238 ps
CPU time 3.47 seconds
Started Jul 09 06:24:14 PM PDT 24
Finished Jul 09 06:24:18 PM PDT 24
Peak memory 217496 kb
Host smart-4a85951a-93ee-418e-91f0-73e4425c8789
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111211647 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_errors.111211647
Directory /workspace/4.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.adc_ctrl_tl_intg_err.3026453586
Short name T57
Test name
Test status
Simulation time 4700202048 ps
CPU time 4.01 seconds
Started Jul 09 06:24:16 PM PDT 24
Finished Jul 09 06:24:20 PM PDT 24
Peak memory 201844 kb
Host smart-c56eff34-dbd7-43ef-a81d-b5a02b9cfa44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026453586 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_tl_in
tg_err.3026453586
Directory /workspace/4.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.adc_ctrl_intr_test.1967394208
Short name T802
Test name
Test status
Simulation time 567271804 ps
CPU time 1.05 seconds
Started Jul 09 06:24:57 PM PDT 24
Finished Jul 09 06:24:59 PM PDT 24
Peak memory 201448 kb
Host smart-32505dc5-2763-48f9-9691-5d214934d704
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967394208 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_intr_test.1967394208
Directory /workspace/40.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.adc_ctrl_intr_test.1460713579
Short name T801
Test name
Test status
Simulation time 382648292 ps
CPU time 0.83 seconds
Started Jul 09 06:24:56 PM PDT 24
Finished Jul 09 06:24:57 PM PDT 24
Peak memory 201420 kb
Host smart-5d8adf9f-9f16-43c2-b103-82471274db89
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460713579 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_intr_test.1460713579
Directory /workspace/41.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.adc_ctrl_intr_test.159478567
Short name T841
Test name
Test status
Simulation time 419780423 ps
CPU time 1.15 seconds
Started Jul 09 06:25:00 PM PDT 24
Finished Jul 09 06:25:02 PM PDT 24
Peak memory 201448 kb
Host smart-48a8b243-e858-461f-8ba5-c0e2ece65292
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159478567 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_intr_test.159478567
Directory /workspace/42.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.adc_ctrl_intr_test.4119330691
Short name T825
Test name
Test status
Simulation time 449525510 ps
CPU time 1.14 seconds
Started Jul 09 06:25:01 PM PDT 24
Finished Jul 09 06:25:02 PM PDT 24
Peak memory 201436 kb
Host smart-cdc8baf7-6b4d-4c79-9b5f-01a1ad83bc14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119330691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_intr_test.4119330691
Directory /workspace/43.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.adc_ctrl_intr_test.2619747291
Short name T871
Test name
Test status
Simulation time 563605474 ps
CPU time 0.97 seconds
Started Jul 09 06:24:58 PM PDT 24
Finished Jul 09 06:25:00 PM PDT 24
Peak memory 201440 kb
Host smart-4124f1e1-e601-4f06-93de-b499fe25b437
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619747291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_intr_test.2619747291
Directory /workspace/44.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.adc_ctrl_intr_test.123320409
Short name T850
Test name
Test status
Simulation time 328859357 ps
CPU time 1.36 seconds
Started Jul 09 06:24:55 PM PDT 24
Finished Jul 09 06:24:57 PM PDT 24
Peak memory 201448 kb
Host smart-510777c7-f887-4e05-b328-2e3eb3e74b2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123320409 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_intr_test.123320409
Directory /workspace/45.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.adc_ctrl_intr_test.3783208316
Short name T893
Test name
Test status
Simulation time 366157169 ps
CPU time 1.45 seconds
Started Jul 09 06:24:55 PM PDT 24
Finished Jul 09 06:24:57 PM PDT 24
Peak memory 201416 kb
Host smart-0849441d-35b2-47b9-bbcf-667e54b1bd70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783208316 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_intr_test.3783208316
Directory /workspace/46.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.adc_ctrl_intr_test.1835549399
Short name T904
Test name
Test status
Simulation time 416664621 ps
CPU time 1.54 seconds
Started Jul 09 06:24:56 PM PDT 24
Finished Jul 09 06:24:58 PM PDT 24
Peak memory 201428 kb
Host smart-06e54521-3ab9-4d95-8cd8-efadec4c5648
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835549399 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_intr_test.1835549399
Directory /workspace/47.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.adc_ctrl_intr_test.624887540
Short name T866
Test name
Test status
Simulation time 423471748 ps
CPU time 1.48 seconds
Started Jul 09 06:24:58 PM PDT 24
Finished Jul 09 06:25:00 PM PDT 24
Peak memory 201452 kb
Host smart-e33bb964-9c23-42f2-80f1-cfb4dd0c8fd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624887540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_intr_test.624887540
Directory /workspace/48.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.adc_ctrl_intr_test.406927995
Short name T803
Test name
Test status
Simulation time 466958734 ps
CPU time 0.91 seconds
Started Jul 09 06:24:55 PM PDT 24
Finished Jul 09 06:24:57 PM PDT 24
Peak memory 201336 kb
Host smart-fe596e29-7913-48a9-a157-9787dbf906b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406927995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_intr_test.406927995
Directory /workspace/49.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_mem_rw_with_rand_reset.1634999359
Short name T814
Test name
Test status
Simulation time 536534995 ps
CPU time 2.29 seconds
Started Jul 09 06:24:21 PM PDT 24
Finished Jul 09 06:24:23 PM PDT 24
Peak memory 201748 kb
Host smart-0260136c-b15c-4f10-9ae2-f1188a29b274
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634999359 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 5.adc_ctrl_csr_mem_rw_with_rand_reset.1634999359
Directory /workspace/5.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_csr_rw.4177291401
Short name T131
Test name
Test status
Simulation time 348814173 ps
CPU time 1.13 seconds
Started Jul 09 06:24:25 PM PDT 24
Finished Jul 09 06:24:26 PM PDT 24
Peak memory 201448 kb
Host smart-1639f9cd-65df-4ace-aa4c-a4457f0a7ee8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177291401 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_csr_rw.4177291401
Directory /workspace/5.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_intr_test.3440514238
Short name T816
Test name
Test status
Simulation time 466440477 ps
CPU time 0.9 seconds
Started Jul 09 06:24:18 PM PDT 24
Finished Jul 09 06:24:20 PM PDT 24
Peak memory 201388 kb
Host smart-7f5e092c-ec29-4627-926f-44ce575bde01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440514238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_intr_test.3440514238
Directory /workspace/5.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_same_csr_outstanding.3552261706
Short name T888
Test name
Test status
Simulation time 1937409643 ps
CPU time 4.62 seconds
Started Jul 09 06:24:22 PM PDT 24
Finished Jul 09 06:24:27 PM PDT 24
Peak memory 201496 kb
Host smart-3248da47-755f-4a8d-8bd6-33b1dfb0534b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552261706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_c
trl_same_csr_outstanding.3552261706
Directory /workspace/5.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_errors.1017240832
Short name T887
Test name
Test status
Simulation time 358174209 ps
CPU time 2.16 seconds
Started Jul 09 06:24:20 PM PDT 24
Finished Jul 09 06:24:23 PM PDT 24
Peak memory 201804 kb
Host smart-2c3aa375-d499-4d24-8cbf-7da5130e8c7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017240832 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_errors.1017240832
Directory /workspace/5.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.adc_ctrl_tl_intg_err.595370448
Short name T58
Test name
Test status
Simulation time 4628382815 ps
CPU time 12.04 seconds
Started Jul 09 06:24:17 PM PDT 24
Finished Jul 09 06:24:30 PM PDT 24
Peak memory 201812 kb
Host smart-91eef96c-ed17-4051-b264-c198700b5f21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595370448 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_tl_int
g_err.595370448
Directory /workspace/5.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_mem_rw_with_rand_reset.2539098406
Short name T907
Test name
Test status
Simulation time 602227947 ps
CPU time 1.47 seconds
Started Jul 09 06:24:22 PM PDT 24
Finished Jul 09 06:24:24 PM PDT 24
Peak memory 201572 kb
Host smart-79155d15-13b9-467a-b501-e1a27a18e41f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539098406 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 6.adc_ctrl_csr_mem_rw_with_rand_reset.2539098406
Directory /workspace/6.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_csr_rw.3488918571
Short name T869
Test name
Test status
Simulation time 427685996 ps
CPU time 1.71 seconds
Started Jul 09 06:24:24 PM PDT 24
Finished Jul 09 06:24:26 PM PDT 24
Peak memory 201520 kb
Host smart-a5725745-37ee-4545-ab2c-3d9059a4a0d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488918571 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_csr_rw.3488918571
Directory /workspace/6.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_intr_test.303961743
Short name T873
Test name
Test status
Simulation time 476736127 ps
CPU time 1.65 seconds
Started Jul 09 06:24:22 PM PDT 24
Finished Jul 09 06:24:25 PM PDT 24
Peak memory 201392 kb
Host smart-d7dd72e2-d05e-4cc8-bb7b-7dde61707615
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303961743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_intr_test.303961743
Directory /workspace/6.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_same_csr_outstanding.2720785976
Short name T132
Test name
Test status
Simulation time 4442504228 ps
CPU time 2.92 seconds
Started Jul 09 06:24:23 PM PDT 24
Finished Jul 09 06:24:26 PM PDT 24
Peak memory 201736 kb
Host smart-407a0494-ede0-49c9-b923-6c6cb490c540
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720785976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_c
trl_same_csr_outstanding.2720785976
Directory /workspace/6.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_errors.3335136983
Short name T916
Test name
Test status
Simulation time 636713245 ps
CPU time 3.1 seconds
Started Jul 09 06:24:23 PM PDT 24
Finished Jul 09 06:24:26 PM PDT 24
Peak memory 201808 kb
Host smart-b3068cd9-67b9-496a-9674-3e49b8266522
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335136983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_errors.3335136983
Directory /workspace/6.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.adc_ctrl_tl_intg_err.4257602457
Short name T919
Test name
Test status
Simulation time 4267911833 ps
CPU time 10.84 seconds
Started Jul 09 06:24:23 PM PDT 24
Finished Jul 09 06:24:34 PM PDT 24
Peak memory 201864 kb
Host smart-fa61e5c9-9377-461a-a9f9-a2eb1b69e9dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257602457 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_tl_in
tg_err.4257602457
Directory /workspace/6.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_mem_rw_with_rand_reset.2572756340
Short name T824
Test name
Test status
Simulation time 533032295 ps
CPU time 1.58 seconds
Started Jul 09 06:24:25 PM PDT 24
Finished Jul 09 06:24:27 PM PDT 24
Peak memory 201560 kb
Host smart-f944ad30-824f-4afd-9d4c-7d9aac2b5606
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572756340 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 7.adc_ctrl_csr_mem_rw_with_rand_reset.2572756340
Directory /workspace/7.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_csr_rw.95928606
Short name T890
Test name
Test status
Simulation time 468474387 ps
CPU time 1.41 seconds
Started Jul 09 06:24:25 PM PDT 24
Finished Jul 09 06:24:27 PM PDT 24
Peak memory 201524 kb
Host smart-b353f39f-5863-47c5-9652-de556e6dad87
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95928606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_csr_rw.95928606
Directory /workspace/7.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_intr_test.4286378540
Short name T880
Test name
Test status
Simulation time 325390281 ps
CPU time 1.3 seconds
Started Jul 09 06:24:22 PM PDT 24
Finished Jul 09 06:24:23 PM PDT 24
Peak memory 201328 kb
Host smart-9c63e292-2ae3-4895-b0be-f15cc4bce827
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286378540 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_intr_test.4286378540
Directory /workspace/7.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_same_csr_outstanding.3522900724
Short name T129
Test name
Test status
Simulation time 4923036914 ps
CPU time 20.36 seconds
Started Jul 09 06:24:26 PM PDT 24
Finished Jul 09 06:24:47 PM PDT 24
Peak memory 201828 kb
Host smart-7c820795-edd4-4d8c-8702-752dd7b3ddbc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522900724 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_c
trl_same_csr_outstanding.3522900724
Directory /workspace/7.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_errors.2472408227
Short name T879
Test name
Test status
Simulation time 593308896 ps
CPU time 2.22 seconds
Started Jul 09 06:24:25 PM PDT 24
Finished Jul 09 06:24:27 PM PDT 24
Peak memory 201756 kb
Host smart-ab3e807d-b2d1-47c6-a853-d027cef2b507
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472408227 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_errors.2472408227
Directory /workspace/7.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.adc_ctrl_tl_intg_err.1790219061
Short name T351
Test name
Test status
Simulation time 9024448603 ps
CPU time 5.27 seconds
Started Jul 09 06:24:25 PM PDT 24
Finished Jul 09 06:24:31 PM PDT 24
Peak memory 201844 kb
Host smart-e2832e68-bfc0-42b0-a019-df3aae8ab2f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790219061 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_tl_in
tg_err.1790219061
Directory /workspace/7.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_mem_rw_with_rand_reset.1690071117
Short name T901
Test name
Test status
Simulation time 592041033 ps
CPU time 1.45 seconds
Started Jul 09 06:24:26 PM PDT 24
Finished Jul 09 06:24:28 PM PDT 24
Peak memory 201476 kb
Host smart-97ee1d0e-7683-4a87-9dcf-40f8cc90c7d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690071117 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 8.adc_ctrl_csr_mem_rw_with_rand_reset.1690071117
Directory /workspace/8.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_csr_rw.627484481
Short name T121
Test name
Test status
Simulation time 583959368 ps
CPU time 1.09 seconds
Started Jul 09 06:24:32 PM PDT 24
Finished Jul 09 06:24:34 PM PDT 24
Peak memory 201468 kb
Host smart-2caae41c-f5e4-47c8-9661-741110fe05ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627484481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_csr_rw.627484481
Directory /workspace/8.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_intr_test.2415498945
Short name T853
Test name
Test status
Simulation time 501141284 ps
CPU time 1.23 seconds
Started Jul 09 06:24:24 PM PDT 24
Finished Jul 09 06:24:25 PM PDT 24
Peak memory 201392 kb
Host smart-b40835b4-0255-4cbe-b749-8cdd94b7e686
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415498945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_intr_test.2415498945
Directory /workspace/8.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_same_csr_outstanding.2794917715
Short name T918
Test name
Test status
Simulation time 2831449810 ps
CPU time 13.02 seconds
Started Jul 09 06:24:28 PM PDT 24
Finished Jul 09 06:24:42 PM PDT 24
Peak memory 201632 kb
Host smart-b5bf7433-460f-47b4-8b6c-3eaf620c9684
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794917715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_c
trl_same_csr_outstanding.2794917715
Directory /workspace/8.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_errors.977028025
Short name T69
Test name
Test status
Simulation time 408970979 ps
CPU time 1.47 seconds
Started Jul 09 06:24:24 PM PDT 24
Finished Jul 09 06:24:26 PM PDT 24
Peak memory 201792 kb
Host smart-03e1f2cb-9531-48d6-817a-b76479eaeaee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977028025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_errors.977028025
Directory /workspace/8.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.adc_ctrl_tl_intg_err.4243863675
Short name T350
Test name
Test status
Simulation time 4540313474 ps
CPU time 4.28 seconds
Started Jul 09 06:24:27 PM PDT 24
Finished Jul 09 06:24:31 PM PDT 24
Peak memory 201732 kb
Host smart-99bc9fac-72cc-4c3a-bc9f-59ff4cdf47c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243863675 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_tl_in
tg_err.4243863675
Directory /workspace/8.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_mem_rw_with_rand_reset.1962440826
Short name T812
Test name
Test status
Simulation time 685527539 ps
CPU time 1.1 seconds
Started Jul 09 06:24:34 PM PDT 24
Finished Jul 09 06:24:35 PM PDT 24
Peak memory 201568 kb
Host smart-cb5f9398-1aa2-44e3-9f7b-24660a5a827d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962440826 -assert nopostproc +UVM_TESTNAME
=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb
-cm_log /dev/null -cm_name 9.adc_ctrl_csr_mem_rw_with_rand_reset.1962440826
Directory /workspace/9.adc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_csr_rw.1583616405
Short name T119
Test name
Test status
Simulation time 537386804 ps
CPU time 2.02 seconds
Started Jul 09 06:24:26 PM PDT 24
Finished Jul 09 06:24:29 PM PDT 24
Peak memory 201512 kb
Host smart-7905ffe2-b00f-4c5b-a937-0bdfd43cbf17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583616405 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_csr_rw.1583616405
Directory /workspace/9.adc_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_intr_test.4024530349
Short name T835
Test name
Test status
Simulation time 419451647 ps
CPU time 0.86 seconds
Started Jul 09 06:24:27 PM PDT 24
Finished Jul 09 06:24:28 PM PDT 24
Peak memory 201436 kb
Host smart-cf40be42-a777-4300-806f-f470f3fb42e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024530349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_intr_test.4024530349
Directory /workspace/9.adc_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_same_csr_outstanding.1338789320
Short name T830
Test name
Test status
Simulation time 4735767110 ps
CPU time 3.61 seconds
Started Jul 09 06:24:26 PM PDT 24
Finished Jul 09 06:24:31 PM PDT 24
Peak memory 201848 kb
Host smart-1cba19bc-2ad5-409c-9521-decc53c211c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338789320 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=a
dc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_c
trl_same_csr_outstanding.1338789320
Directory /workspace/9.adc_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_errors.2454783609
Short name T68
Test name
Test status
Simulation time 545760022 ps
CPU time 2.61 seconds
Started Jul 09 06:24:27 PM PDT 24
Finished Jul 09 06:24:30 PM PDT 24
Peak memory 218124 kb
Host smart-5ba4a50e-1dbe-42a2-957c-2516d0d071a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454783609 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_errors.2454783609
Directory /workspace/9.adc_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.adc_ctrl_tl_intg_err.4006467911
Short name T352
Test name
Test status
Simulation time 4392324120 ps
CPU time 9.1 seconds
Started Jul 09 06:24:31 PM PDT 24
Finished Jul 09 06:24:40 PM PDT 24
Peak memory 201796 kb
Host smart-ab7d2420-c840-4baf-ae50-224c1f5ffdd1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006467911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_tl_in
tg_err.4006467911
Directory /workspace/9.adc_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.adc_ctrl_alert_test.682599469
Short name T515
Test name
Test status
Simulation time 363850930 ps
CPU time 0.9 seconds
Started Jul 09 06:32:42 PM PDT 24
Finished Jul 09 06:33:05 PM PDT 24
Peak memory 201616 kb
Host smart-192b977a-dd76-4b5b-a999-7da2264bc87e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682599469 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_alert_test.682599469
Directory /workspace/0.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.adc_ctrl_clock_gating.4014673839
Short name T230
Test name
Test status
Simulation time 191322926523 ps
CPU time 180.34 seconds
Started Jul 09 06:32:46 PM PDT 24
Finished Jul 09 06:36:06 PM PDT 24
Peak memory 201892 kb
Host smart-30c09e7a-57ed-49a6-a25f-2396e715d79f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014673839 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_clock_gati
ng.4014673839
Directory /workspace/0.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt.765319272
Short name T581
Test name
Test status
Simulation time 169587816453 ps
CPU time 31.68 seconds
Started Jul 09 06:32:41 PM PDT 24
Finished Jul 09 06:33:35 PM PDT 24
Peak memory 201948 kb
Host smart-b67282a2-d94c-4148-b3bd-5ae963aa63a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765319272 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrupt.765319272
Directory /workspace/0.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_interrupt_fixed.2179022127
Short name T500
Test name
Test status
Simulation time 493791230703 ps
CPU time 1142.06 seconds
Started Jul 09 06:32:42 PM PDT 24
Finished Jul 09 06:52:06 PM PDT 24
Peak memory 201852 kb
Host smart-42e755aa-7f41-4bcc-8151-373efcb8fcf6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179022127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_interrup
t_fixed.2179022127
Directory /workspace/0.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled.2059459377
Short name T178
Test name
Test status
Simulation time 479645556829 ps
CPU time 130.22 seconds
Started Jul 09 06:32:36 PM PDT 24
Finished Jul 09 06:35:09 PM PDT 24
Peak memory 201940 kb
Host smart-884c79cf-1ed2-4129-8e3c-8d5dc1fffb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059459377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled.2059459377
Directory /workspace/0.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_polled_fixed.914312662
Short name T562
Test name
Test status
Simulation time 163444286499 ps
CPU time 100.45 seconds
Started Jul 09 06:32:37 PM PDT 24
Finished Jul 09 06:34:40 PM PDT 24
Peak memory 201964 kb
Host smart-3cf4aeba-bbfb-41ea-81a1-cf3348973856
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=914312662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_polled_fixed
.914312662
Directory /workspace/0.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup.902901818
Short name T249
Test name
Test status
Simulation time 161671130272 ps
CPU time 183.9 seconds
Started Jul 09 06:32:51 PM PDT 24
Finished Jul 09 06:36:13 PM PDT 24
Peak memory 201968 kb
Host smart-af42f3bf-e61c-45c2-b559-8e6ec03e46d1
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902901818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_filters_w
akeup.902901818
Directory /workspace/0.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/0.adc_ctrl_filters_wakeup_fixed.3564807904
Short name T669
Test name
Test status
Simulation time 603938320347 ps
CPU time 1453.87 seconds
Started Jul 09 06:32:41 PM PDT 24
Finished Jul 09 06:57:17 PM PDT 24
Peak memory 201948 kb
Host smart-0426330a-788f-43e5-8611-988291926452
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564807904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.
adc_ctrl_filters_wakeup_fixed.3564807904
Directory /workspace/0.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/0.adc_ctrl_fsm_reset.2157715760
Short name T561
Test name
Test status
Simulation time 120576635563 ps
CPU time 484.77 seconds
Started Jul 09 06:33:26 PM PDT 24
Finished Jul 09 06:41:34 PM PDT 24
Peak memory 202316 kb
Host smart-2bad6f88-1ec9-4dd9-8be3-a54c92945181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157715760 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_fsm_reset.2157715760
Directory /workspace/0.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/0.adc_ctrl_lowpower_counter.3550207905
Short name T102
Test name
Test status
Simulation time 24263353688 ps
CPU time 56.88 seconds
Started Jul 09 06:32:42 PM PDT 24
Finished Jul 09 06:34:00 PM PDT 24
Peak memory 201676 kb
Host smart-ad387a79-111b-4d33-99bf-590b51d930d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550207905 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_lowpower_counter.3550207905
Directory /workspace/0.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_poweron_counter.438325215
Short name T421
Test name
Test status
Simulation time 4645549172 ps
CPU time 4.3 seconds
Started Jul 09 06:32:43 PM PDT 24
Finished Jul 09 06:33:08 PM PDT 24
Peak memory 201724 kb
Host smart-e17ec381-49d0-4c40-a281-bc2f90ff966a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438325215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_poweron_counter.438325215
Directory /workspace/0.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/0.adc_ctrl_smoke.3224522488
Short name T614
Test name
Test status
Simulation time 6005446778 ps
CPU time 4.6 seconds
Started Jul 09 06:32:36 PM PDT 24
Finished Jul 09 06:33:04 PM PDT 24
Peak memory 201616 kb
Host smart-5c1e0cfc-589c-4026-8898-bb1a814fdfc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224522488 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_smoke.3224522488
Directory /workspace/0.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all.1261206366
Short name T317
Test name
Test status
Simulation time 338240178960 ps
CPU time 825.12 seconds
Started Jul 09 06:32:40 PM PDT 24
Finished Jul 09 06:46:47 PM PDT 24
Peak memory 201968 kb
Host smart-8d9b9a7a-4488-41d0-b396-06919210d97f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261206366 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all.
1261206366
Directory /workspace/0.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.adc_ctrl_stress_all_with_rand_reset.2528995923
Short name T794
Test name
Test status
Simulation time 64028665105 ps
CPU time 182.71 seconds
Started Jul 09 06:32:41 PM PDT 24
Finished Jul 09 06:36:06 PM PDT 24
Peak memory 210612 kb
Host smart-bbac6116-abd9-4ef3-8990-6332be8d8189
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528995923 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 0.adc_ctrl_stress_all_with_rand_reset.2528995923
Directory /workspace/0.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_alert_test.2742674503
Short name T577
Test name
Test status
Simulation time 387125739 ps
CPU time 1.09 seconds
Started Jul 09 06:32:54 PM PDT 24
Finished Jul 09 06:33:11 PM PDT 24
Peak memory 201676 kb
Host smart-56c3fc61-61b2-41af-aa48-18b660623b4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742674503 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_alert_test.2742674503
Directory /workspace/1.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.adc_ctrl_clock_gating.2172690432
Short name T636
Test name
Test status
Simulation time 348085960163 ps
CPU time 344.32 seconds
Started Jul 09 06:32:49 PM PDT 24
Finished Jul 09 06:38:52 PM PDT 24
Peak memory 201892 kb
Host smart-7531b784-3b83-453e-9423-4368bec20442
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172690432 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_clock_gati
ng.2172690432
Directory /workspace/1.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_both.1606706880
Short name T225
Test name
Test status
Simulation time 546699358654 ps
CPU time 615.36 seconds
Started Jul 09 06:32:50 PM PDT 24
Finished Jul 09 06:43:23 PM PDT 24
Peak memory 201928 kb
Host smart-3e2f448e-c89b-42a9-8543-8c1c1ab8a9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606706880 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_both.1606706880
Directory /workspace/1.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt.2448697411
Short name T138
Test name
Test status
Simulation time 169335092282 ps
CPU time 353.41 seconds
Started Jul 09 06:32:50 PM PDT 24
Finished Jul 09 06:39:01 PM PDT 24
Peak memory 201880 kb
Host smart-c0633116-72fa-4856-a29b-1d1a3a1afcb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448697411 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrupt.2448697411
Directory /workspace/1.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_interrupt_fixed.3127676302
Short name T647
Test name
Test status
Simulation time 324735024081 ps
CPU time 208.09 seconds
Started Jul 09 06:32:50 PM PDT 24
Finished Jul 09 06:36:36 PM PDT 24
Peak memory 202076 kb
Host smart-b4345594-e6b8-4cbf-90b3-f8fd0fb10342
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127676302 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_interrup
t_fixed.3127676302
Directory /workspace/1.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled.1666388691
Short name T744
Test name
Test status
Simulation time 161819179906 ps
CPU time 99.8 seconds
Started Jul 09 06:32:51 PM PDT 24
Finished Jul 09 06:34:49 PM PDT 24
Peak memory 201888 kb
Host smart-673b79a7-ab5e-4ddf-9d15-3aa33e8200bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666388691 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled.1666388691
Directory /workspace/1.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_polled_fixed.1022699943
Short name T517
Test name
Test status
Simulation time 333814278225 ps
CPU time 744.95 seconds
Started Jul 09 06:32:49 PM PDT 24
Finished Jul 09 06:45:33 PM PDT 24
Peak memory 201840 kb
Host smart-ef04837a-cccd-46b2-8042-4b56c6dbad8c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022699943 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_polled_fixe
d.1022699943
Directory /workspace/1.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup.876569580
Short name T338
Test name
Test status
Simulation time 379452019402 ps
CPU time 859.63 seconds
Started Jul 09 06:32:50 PM PDT 24
Finished Jul 09 06:47:28 PM PDT 24
Peak memory 201912 kb
Host smart-8b60c5d6-7876-4aea-9745-347f03a4af8b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876569580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_filters_w
akeup.876569580
Directory /workspace/1.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/1.adc_ctrl_filters_wakeup_fixed.4169124139
Short name T689
Test name
Test status
Simulation time 211216038743 ps
CPU time 240.83 seconds
Started Jul 09 06:32:49 PM PDT 24
Finished Jul 09 06:37:09 PM PDT 24
Peak memory 201884 kb
Host smart-0186da76-3609-49e0-9765-991b2e5d461c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169124139 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.
adc_ctrl_filters_wakeup_fixed.4169124139
Directory /workspace/1.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/1.adc_ctrl_fsm_reset.4123534329
Short name T78
Test name
Test status
Simulation time 74464277778 ps
CPU time 297.57 seconds
Started Jul 09 06:32:51 PM PDT 24
Finished Jul 09 06:38:06 PM PDT 24
Peak memory 202244 kb
Host smart-28b81c9e-eac7-4c00-adf4-ab340ac27af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123534329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_fsm_reset.4123534329
Directory /workspace/1.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/1.adc_ctrl_lowpower_counter.3561235896
Short name T718
Test name
Test status
Simulation time 44053211171 ps
CPU time 26.46 seconds
Started Jul 09 06:32:49 PM PDT 24
Finished Jul 09 06:33:34 PM PDT 24
Peak memory 201556 kb
Host smart-9df79e18-851d-4d71-9ece-63020cdef3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561235896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_lowpower_counter.3561235896
Directory /workspace/1.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_poweron_counter.3170720892
Short name T135
Test name
Test status
Simulation time 3298589979 ps
CPU time 4.47 seconds
Started Jul 09 06:32:49 PM PDT 24
Finished Jul 09 06:33:12 PM PDT 24
Peak memory 201744 kb
Host smart-4df5b664-7719-471d-8111-f69dd5b91fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170720892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_poweron_counter.3170720892
Directory /workspace/1.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/1.adc_ctrl_sec_cm.27298136
Short name T63
Test name
Test status
Simulation time 4287045306 ps
CPU time 10.34 seconds
Started Jul 09 06:32:53 PM PDT 24
Finished Jul 09 06:33:20 PM PDT 24
Peak memory 217132 kb
Host smart-b3395a69-ecac-4132-8570-68f740443f8f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27298136 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_sec_cm.27298136
Directory /workspace/1.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.adc_ctrl_smoke.2176077644
Short name T436
Test name
Test status
Simulation time 5525346578 ps
CPU time 10.74 seconds
Started Jul 09 06:32:46 PM PDT 24
Finished Jul 09 06:33:16 PM PDT 24
Peak memory 201708 kb
Host smart-576cf973-5619-499d-b18f-3dbb1ec473f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176077644 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_smoke.2176077644
Directory /workspace/1.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/1.adc_ctrl_stress_all_with_rand_reset.131442091
Short name T503
Test name
Test status
Simulation time 82502303788 ps
CPU time 197.52 seconds
Started Jul 09 06:32:51 PM PDT 24
Finished Jul 09 06:36:26 PM PDT 24
Peak memory 210500 kb
Host smart-ea3ffed1-a091-439c-84c2-7eab5b97f6a7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131442091 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 1.adc_ctrl_stress_all_with_rand_reset.131442091
Directory /workspace/1.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_both.1112168235
Short name T191
Test name
Test status
Simulation time 166569286550 ps
CPU time 352.4 seconds
Started Jul 09 06:33:29 PM PDT 24
Finished Jul 09 06:39:23 PM PDT 24
Peak memory 201948 kb
Host smart-961c3e70-adda-4b4c-8c18-259f5b2aec0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112168235 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_both.1112168235
Directory /workspace/10.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt.3092240903
Short name T260
Test name
Test status
Simulation time 327446230891 ps
CPU time 200.81 seconds
Started Jul 09 06:33:26 PM PDT 24
Finished Jul 09 06:36:50 PM PDT 24
Peak memory 201908 kb
Host smart-46fec48d-a9af-4826-8c9f-dd074408c54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092240903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interrupt.3092240903
Directory /workspace/10.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_interrupt_fixed.3639600339
Short name T589
Test name
Test status
Simulation time 162601755647 ps
CPU time 341.47 seconds
Started Jul 09 06:33:29 PM PDT 24
Finished Jul 09 06:39:12 PM PDT 24
Peak memory 201912 kb
Host smart-78b7716d-582d-4f17-a8bb-6da307839178
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639600339 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_interru
pt_fixed.3639600339
Directory /workspace/10.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled.756410275
Short name T150
Test name
Test status
Simulation time 491513110138 ps
CPU time 157.42 seconds
Started Jul 09 06:33:29 PM PDT 24
Finished Jul 09 06:36:08 PM PDT 24
Peak memory 202016 kb
Host smart-e84e40be-7277-4d68-a57c-eeed19d7833b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756410275 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled.756410275
Directory /workspace/10.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/10.adc_ctrl_filters_polled_fixed.2517395640
Short name T81
Test name
Test status
Simulation time 163784854283 ps
CPU time 204.04 seconds
Started Jul 09 06:33:29 PM PDT 24
Finished Jul 09 06:36:55 PM PDT 24
Peak memory 201904 kb
Host smart-11f300a3-9811-402c-88c3-2d72714bc896
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517395640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_filters_polled_fix
ed.2517395640
Directory /workspace/10.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/10.adc_ctrl_fsm_reset.3976581575
Short name T203
Test name
Test status
Simulation time 119423709083 ps
CPU time 365.94 seconds
Started Jul 09 06:33:33 PM PDT 24
Finished Jul 09 06:39:41 PM PDT 24
Peak memory 202276 kb
Host smart-2bd7a97b-e238-4eec-80f7-81883d9b78ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976581575 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_fsm_reset.3976581575
Directory /workspace/10.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/10.adc_ctrl_lowpower_counter.3356231043
Short name T371
Test name
Test status
Simulation time 23720497075 ps
CPU time 27.57 seconds
Started Jul 09 06:33:33 PM PDT 24
Finished Jul 09 06:34:02 PM PDT 24
Peak memory 201728 kb
Host smart-d67feb5a-d29c-4886-9595-80e4f6fea66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356231043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_lowpower_counter.3356231043
Directory /workspace/10.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_poweron_counter.3764179662
Short name T374
Test name
Test status
Simulation time 3159884993 ps
CPU time 4 seconds
Started Jul 09 06:33:33 PM PDT 24
Finished Jul 09 06:33:38 PM PDT 24
Peak memory 201708 kb
Host smart-f3b94adb-b049-4806-84c3-4ccbf740518b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764179662 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_poweron_counter.3764179662
Directory /workspace/10.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/10.adc_ctrl_smoke.2311382269
Short name T646
Test name
Test status
Simulation time 5995575975 ps
CPU time 4.95 seconds
Started Jul 09 06:33:29 PM PDT 24
Finished Jul 09 06:33:36 PM PDT 24
Peak memory 201720 kb
Host smart-d18810d8-95a5-4176-a7e0-517cb7487d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311382269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_smoke.2311382269
Directory /workspace/10.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all.1561511876
Short name T634
Test name
Test status
Simulation time 441691615979 ps
CPU time 798.27 seconds
Started Jul 09 06:33:33 PM PDT 24
Finished Jul 09 06:46:54 PM PDT 24
Peak memory 212904 kb
Host smart-9cd7513a-e597-4181-83b7-55e94a10975d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561511876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all
.1561511876
Directory /workspace/10.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.adc_ctrl_stress_all_with_rand_reset.3252112133
Short name T198
Test name
Test status
Simulation time 20813676110 ps
CPU time 45.17 seconds
Started Jul 09 06:33:35 PM PDT 24
Finished Jul 09 06:34:22 PM PDT 24
Peak memory 210604 kb
Host smart-ec283357-fdf2-4956-a1c2-b720e3897d5a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252112133 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 10.adc_ctrl_stress_all_with_rand_reset.3252112133
Directory /workspace/10.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.adc_ctrl_alert_test.716755714
Short name T664
Test name
Test status
Simulation time 438003855 ps
CPU time 0.66 seconds
Started Jul 09 06:33:38 PM PDT 24
Finished Jul 09 06:33:41 PM PDT 24
Peak memory 201636 kb
Host smart-c66080e5-4ff2-4be1-8c9e-63715484e63a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716755714 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_alert_test.716755714
Directory /workspace/11.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/11.adc_ctrl_clock_gating.422469259
Short name T233
Test name
Test status
Simulation time 516284101865 ps
CPU time 124.13 seconds
Started Jul 09 06:33:33 PM PDT 24
Finished Jul 09 06:35:40 PM PDT 24
Peak memory 202092 kb
Host smart-784318d6-e2b9-44f3-a667-04ddc8d24c82
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422469259 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_clock_gati
ng.422469259
Directory /workspace/11.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt.2594088041
Short name T189
Test name
Test status
Simulation time 326505703266 ps
CPU time 165.06 seconds
Started Jul 09 06:33:33 PM PDT 24
Finished Jul 09 06:36:21 PM PDT 24
Peak memory 202056 kb
Host smart-cd38f478-3844-4f12-a873-783b99296073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594088041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interrupt.2594088041
Directory /workspace/11.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_interrupt_fixed.3131832514
Short name T721
Test name
Test status
Simulation time 326289285984 ps
CPU time 86.93 seconds
Started Jul 09 06:33:32 PM PDT 24
Finished Jul 09 06:35:00 PM PDT 24
Peak memory 201864 kb
Host smart-baae4174-2115-413e-8509-bc3931a17f42
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131832514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_interru
pt_fixed.3131832514
Directory /workspace/11.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled.1142160587
Short name T188
Test name
Test status
Simulation time 488886914376 ps
CPU time 170.2 seconds
Started Jul 09 06:33:33 PM PDT 24
Finished Jul 09 06:36:26 PM PDT 24
Peak memory 201928 kb
Host smart-91ece5b7-7c08-4d1a-b3a7-88c12c044f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142160587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled.1142160587
Directory /workspace/11.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_polled_fixed.3168314742
Short name T411
Test name
Test status
Simulation time 164801294012 ps
CPU time 349.25 seconds
Started Jul 09 06:33:32 PM PDT 24
Finished Jul 09 06:39:22 PM PDT 24
Peak memory 201904 kb
Host smart-f95d6357-26be-402b-bbe8-ba7a705fb10f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168314742 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_filters_polled_fix
ed.3168314742
Directory /workspace/11.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_filters_wakeup_fixed.3500191596
Short name T458
Test name
Test status
Simulation time 410767815542 ps
CPU time 882.2 seconds
Started Jul 09 06:33:32 PM PDT 24
Finished Jul 09 06:48:16 PM PDT 24
Peak memory 201824 kb
Host smart-b1bd65c8-acac-4507-a0c2-67727bfcb10d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500191596 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11
.adc_ctrl_filters_wakeup_fixed.3500191596
Directory /workspace/11.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/11.adc_ctrl_lowpower_counter.2360418341
Short name T365
Test name
Test status
Simulation time 43362698116 ps
CPU time 51.41 seconds
Started Jul 09 06:33:32 PM PDT 24
Finished Jul 09 06:34:24 PM PDT 24
Peak memory 201708 kb
Host smart-52614211-a4c3-4edd-8a60-5d095a504ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360418341 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_lowpower_counter.2360418341
Directory /workspace/11.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_poweron_counter.915279135
Short name T104
Test name
Test status
Simulation time 5251600585 ps
CPU time 11.75 seconds
Started Jul 09 06:33:32 PM PDT 24
Finished Jul 09 06:33:44 PM PDT 24
Peak memory 201720 kb
Host smart-776be47a-bb4a-45f7-871f-13b1c8950c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915279135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_poweron_counter.915279135
Directory /workspace/11.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/11.adc_ctrl_smoke.2760451580
Short name T793
Test name
Test status
Simulation time 5682736352 ps
CPU time 6.58 seconds
Started Jul 09 06:33:34 PM PDT 24
Finished Jul 09 06:33:43 PM PDT 24
Peak memory 201700 kb
Host smart-8e02a853-08f0-4ee6-b3cd-8ff9236996b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760451580 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_smoke.2760451580
Directory /workspace/11.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/11.adc_ctrl_stress_all_with_rand_reset.1807227452
Short name T31
Test name
Test status
Simulation time 158763562835 ps
CPU time 321.21 seconds
Started Jul 09 06:33:35 PM PDT 24
Finished Jul 09 06:38:58 PM PDT 24
Peak memory 210252 kb
Host smart-7be7b746-6ec4-4ab1-a409-68a0ac3c98e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807227452 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 11.adc_ctrl_stress_all_with_rand_reset.1807227452
Directory /workspace/11.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_alert_test.1454638771
Short name T375
Test name
Test status
Simulation time 470776364 ps
CPU time 0.91 seconds
Started Jul 09 06:33:37 PM PDT 24
Finished Jul 09 06:33:40 PM PDT 24
Peak memory 201660 kb
Host smart-08738a58-9006-4c93-b379-8daab500474e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454638771 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_alert_test.1454638771
Directory /workspace/12.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.adc_ctrl_clock_gating.3500806717
Short name T559
Test name
Test status
Simulation time 167233726834 ps
CPU time 190.84 seconds
Started Jul 09 06:33:36 PM PDT 24
Finished Jul 09 06:36:49 PM PDT 24
Peak memory 202156 kb
Host smart-e6a77fe8-bf58-4701-8f2b-00f7a1943e8c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500806717 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_clock_gat
ing.3500806717
Directory /workspace/12.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_both.21400486
Short name T157
Test name
Test status
Simulation time 495034829021 ps
CPU time 306.24 seconds
Started Jul 09 06:33:38 PM PDT 24
Finished Jul 09 06:38:46 PM PDT 24
Peak memory 201924 kb
Host smart-2284ebfd-25ad-493f-a0a8-2fdc7ecb0381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21400486 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_both.21400486
Directory /workspace/12.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt.3102329287
Short name T639
Test name
Test status
Simulation time 322327436296 ps
CPU time 695.58 seconds
Started Jul 09 06:33:35 PM PDT 24
Finished Jul 09 06:45:13 PM PDT 24
Peak memory 202008 kb
Host smart-dfed820f-c36c-4200-8596-7d2110fe9e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102329287 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interrupt.3102329287
Directory /workspace/12.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_interrupt_fixed.1765487267
Short name T95
Test name
Test status
Simulation time 165593316481 ps
CPU time 147.28 seconds
Started Jul 09 06:33:36 PM PDT 24
Finished Jul 09 06:36:05 PM PDT 24
Peak memory 201820 kb
Host smart-1fbdbfca-5aa6-47e8-b759-343ba75c751b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765487267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_interru
pt_fixed.1765487267
Directory /workspace/12.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled.2641208221
Short name T185
Test name
Test status
Simulation time 321854919368 ps
CPU time 75.33 seconds
Started Jul 09 06:33:38 PM PDT 24
Finished Jul 09 06:34:56 PM PDT 24
Peak memory 201984 kb
Host smart-2b63e8e0-9c5b-41c6-8b87-3599cc24c00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641208221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled.2641208221
Directory /workspace/12.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_polled_fixed.1270392699
Short name T553
Test name
Test status
Simulation time 167935922892 ps
CPU time 155.15 seconds
Started Jul 09 06:33:40 PM PDT 24
Finished Jul 09 06:36:17 PM PDT 24
Peak memory 201336 kb
Host smart-d400ef4e-3485-48b8-84bb-d915e7ce5b59
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270392699 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters_polled_fix
ed.1270392699
Directory /workspace/12.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup.1695324998
Short name T250
Test name
Test status
Simulation time 619929507745 ps
CPU time 169.75 seconds
Started Jul 09 06:33:36 PM PDT 24
Finished Jul 09 06:36:28 PM PDT 24
Peak memory 201992 kb
Host smart-14441d8c-27d3-4891-b70a-208c1a456e14
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695324998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_filters
_wakeup.1695324998
Directory /workspace/12.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/12.adc_ctrl_filters_wakeup_fixed.455728086
Short name T368
Test name
Test status
Simulation time 614304530745 ps
CPU time 333.89 seconds
Started Jul 09 06:33:39 PM PDT 24
Finished Jul 09 06:39:15 PM PDT 24
Peak memory 201904 kb
Host smart-4aa57978-b557-4ab1-a5be-6d81b9b21755
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455728086 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.
adc_ctrl_filters_wakeup_fixed.455728086
Directory /workspace/12.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/12.adc_ctrl_fsm_reset.1127722063
Short name T43
Test name
Test status
Simulation time 82215806105 ps
CPU time 448.47 seconds
Started Jul 09 06:33:39 PM PDT 24
Finished Jul 09 06:41:10 PM PDT 24
Peak memory 202296 kb
Host smart-2d2e6403-a69e-4159-8e88-071ab19eadeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127722063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_fsm_reset.1127722063
Directory /workspace/12.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/12.adc_ctrl_lowpower_counter.2976862515
Short name T632
Test name
Test status
Simulation time 26859654570 ps
CPU time 17.37 seconds
Started Jul 09 06:33:38 PM PDT 24
Finished Jul 09 06:33:57 PM PDT 24
Peak memory 201652 kb
Host smart-e4763b16-7a2f-4c3c-954b-9b05c47c92f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976862515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_lowpower_counter.2976862515
Directory /workspace/12.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_poweron_counter.1241998226
Short name T741
Test name
Test status
Simulation time 4911727102 ps
CPU time 3.61 seconds
Started Jul 09 06:33:36 PM PDT 24
Finished Jul 09 06:33:42 PM PDT 24
Peak memory 201680 kb
Host smart-1aab7bea-8f94-4dbd-a723-e98ae58b54a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241998226 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_poweron_counter.1241998226
Directory /workspace/12.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/12.adc_ctrl_smoke.3351925801
Short name T512
Test name
Test status
Simulation time 5888082383 ps
CPU time 13.69 seconds
Started Jul 09 06:33:33 PM PDT 24
Finished Jul 09 06:33:49 PM PDT 24
Peak memory 201692 kb
Host smart-fc208c8f-7b02-47ba-82df-e19eb387d8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351925801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_smoke.3351925801
Directory /workspace/12.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/12.adc_ctrl_stress_all.2259563133
Short name T196
Test name
Test status
Simulation time 270777868171 ps
CPU time 387.66 seconds
Started Jul 09 06:33:36 PM PDT 24
Finished Jul 09 06:40:06 PM PDT 24
Peak memory 218576 kb
Host smart-c2434faf-0dc5-4c7e-9966-4a1d5760d681
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259563133 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.adc_ctrl_stress_all
.2259563133
Directory /workspace/12.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_alert_test.855210623
Short name T85
Test name
Test status
Simulation time 440874871 ps
CPU time 1.02 seconds
Started Jul 09 06:33:42 PM PDT 24
Finished Jul 09 06:33:45 PM PDT 24
Peak memory 201852 kb
Host smart-0a0afa92-4c4b-4099-bff7-27497f2543c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855210623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_alert_test.855210623
Directory /workspace/13.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled.3946415089
Short name T320
Test name
Test status
Simulation time 316777584216 ps
CPU time 620.64 seconds
Started Jul 09 06:33:40 PM PDT 24
Finished Jul 09 06:44:02 PM PDT 24
Peak memory 201388 kb
Host smart-1079795a-9d4c-4976-ba46-078215027e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946415089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled.3946415089
Directory /workspace/13.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_polled_fixed.1214825312
Short name T564
Test name
Test status
Simulation time 331321204271 ps
CPU time 744.4 seconds
Started Jul 09 06:33:39 PM PDT 24
Finished Jul 09 06:46:06 PM PDT 24
Peak memory 201876 kb
Host smart-af5a459b-0d9f-4053-87ed-2b7de8b0ef45
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214825312 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters_polled_fix
ed.1214825312
Directory /workspace/13.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup.3494922233
Short name T180
Test name
Test status
Simulation time 367912449211 ps
CPU time 169.66 seconds
Started Jul 09 06:33:38 PM PDT 24
Finished Jul 09 06:36:29 PM PDT 24
Peak memory 201856 kb
Host smart-a388b583-b579-447a-9bc7-b5925ff8615e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494922233 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_filters
_wakeup.3494922233
Directory /workspace/13.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/13.adc_ctrl_filters_wakeup_fixed.801012162
Short name T372
Test name
Test status
Simulation time 615124143000 ps
CPU time 664.08 seconds
Started Jul 09 06:33:41 PM PDT 24
Finished Jul 09 06:44:47 PM PDT 24
Peak memory 201980 kb
Host smart-15771266-871e-4374-96ef-26d86b5c8a8d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801012162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.
adc_ctrl_filters_wakeup_fixed.801012162
Directory /workspace/13.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/13.adc_ctrl_fsm_reset.2164473633
Short name T787
Test name
Test status
Simulation time 105909116504 ps
CPU time 429.91 seconds
Started Jul 09 06:33:40 PM PDT 24
Finished Jul 09 06:40:52 PM PDT 24
Peak memory 202248 kb
Host smart-f750b86c-d6ad-4a31-84d9-3e153c570f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164473633 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_fsm_reset.2164473633
Directory /workspace/13.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/13.adc_ctrl_lowpower_counter.2658103480
Short name T756
Test name
Test status
Simulation time 32386526865 ps
CPU time 67.46 seconds
Started Jul 09 06:33:41 PM PDT 24
Finished Jul 09 06:34:51 PM PDT 24
Peak memory 201680 kb
Host smart-c73f5fdf-4215-4d79-a6c9-f7f0c950d479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658103480 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_lowpower_counter.2658103480
Directory /workspace/13.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_poweron_counter.3363347248
Short name T544
Test name
Test status
Simulation time 5282151985 ps
CPU time 11.64 seconds
Started Jul 09 06:33:42 PM PDT 24
Finished Jul 09 06:33:55 PM PDT 24
Peak memory 201720 kb
Host smart-b058251b-09c4-4e39-995e-ee677f125bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363347248 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_poweron_counter.3363347248
Directory /workspace/13.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/13.adc_ctrl_smoke.293596566
Short name T635
Test name
Test status
Simulation time 5942594061 ps
CPU time 4.42 seconds
Started Jul 09 06:33:37 PM PDT 24
Finished Jul 09 06:33:44 PM PDT 24
Peak memory 201724 kb
Host smart-9dbfe5e0-b3a8-4fe8-88a2-0e57fa8516c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293596566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_smoke.293596566
Directory /workspace/13.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all.2195276661
Short name T32
Test name
Test status
Simulation time 169128540635 ps
CPU time 364.17 seconds
Started Jul 09 06:33:41 PM PDT 24
Finished Jul 09 06:39:47 PM PDT 24
Peak memory 201960 kb
Host smart-98970a53-cada-45ba-ac9d-0c590d5c77dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195276661 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all
.2195276661
Directory /workspace/13.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.adc_ctrl_stress_all_with_rand_reset.2943376798
Short name T672
Test name
Test status
Simulation time 17114106504 ps
CPU time 39.13 seconds
Started Jul 09 06:33:39 PM PDT 24
Finished Jul 09 06:34:20 PM PDT 24
Peak memory 210248 kb
Host smart-2f15eaec-915e-4c90-b06d-8ccfe653960a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943376798 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 13.adc_ctrl_stress_all_with_rand_reset.2943376798
Directory /workspace/13.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_alert_test.2685740801
Short name T431
Test name
Test status
Simulation time 412742915 ps
CPU time 0.88 seconds
Started Jul 09 06:33:50 PM PDT 24
Finished Jul 09 06:33:52 PM PDT 24
Peak memory 201628 kb
Host smart-c54072ec-8422-4218-bbde-8872a8a2aa17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685740801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_alert_test.2685740801
Directory /workspace/14.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt.1556576148
Short name T212
Test name
Test status
Simulation time 162001953594 ps
CPU time 112.82 seconds
Started Jul 09 06:33:47 PM PDT 24
Finished Jul 09 06:35:42 PM PDT 24
Peak memory 201936 kb
Host smart-dfeb5653-2e53-4d5f-8890-0c4f8d5a6a1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556576148 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrupt.1556576148
Directory /workspace/14.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_interrupt_fixed.996356529
Short name T582
Test name
Test status
Simulation time 498940777562 ps
CPU time 578.02 seconds
Started Jul 09 06:33:46 PM PDT 24
Finished Jul 09 06:43:26 PM PDT 24
Peak memory 201884 kb
Host smart-0352a639-e6c9-440e-844c-943fcce61766
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=996356529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_interrup
t_fixed.996356529
Directory /workspace/14.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled.855261190
Short name T547
Test name
Test status
Simulation time 330041677723 ps
CPU time 204.36 seconds
Started Jul 09 06:33:45 PM PDT 24
Finished Jul 09 06:37:11 PM PDT 24
Peak memory 201892 kb
Host smart-06a1f01e-f9a7-4480-abf5-a906de9f7599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855261190 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled.855261190
Directory /workspace/14.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_polled_fixed.743931668
Short name T162
Test name
Test status
Simulation time 327410401337 ps
CPU time 695.37 seconds
Started Jul 09 06:33:46 PM PDT 24
Finished Jul 09 06:45:24 PM PDT 24
Peak memory 201884 kb
Host smart-5d0dab17-a436-456d-844d-41a8f3df64e2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=743931668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters_polled_fixe
d.743931668
Directory /workspace/14.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup.3817494280
Short name T290
Test name
Test status
Simulation time 550208447772 ps
CPU time 1209.8 seconds
Started Jul 09 06:33:46 PM PDT 24
Finished Jul 09 06:53:58 PM PDT 24
Peak memory 201948 kb
Host smart-2edce83b-955b-4c7a-a1a8-90372cf36563
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817494280 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_filters
_wakeup.3817494280
Directory /workspace/14.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/14.adc_ctrl_filters_wakeup_fixed.2993916117
Short name T621
Test name
Test status
Simulation time 594449418210 ps
CPU time 343.42 seconds
Started Jul 09 06:33:45 PM PDT 24
Finished Jul 09 06:39:31 PM PDT 24
Peak memory 201796 kb
Host smart-fda92552-5e63-4800-9356-0c2ce31d3dbd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993916117 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14
.adc_ctrl_filters_wakeup_fixed.2993916117
Directory /workspace/14.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/14.adc_ctrl_fsm_reset.139176585
Short name T433
Test name
Test status
Simulation time 106190162357 ps
CPU time 368.59 seconds
Started Jul 09 06:33:51 PM PDT 24
Finished Jul 09 06:40:02 PM PDT 24
Peak memory 202300 kb
Host smart-7828704c-1f5c-410c-9a5b-0bd5d4f3d298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139176585 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_fsm_reset.139176585
Directory /workspace/14.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/14.adc_ctrl_lowpower_counter.3423844683
Short name T505
Test name
Test status
Simulation time 34831703466 ps
CPU time 19.62 seconds
Started Jul 09 06:33:53 PM PDT 24
Finished Jul 09 06:34:14 PM PDT 24
Peak memory 201732 kb
Host smart-7dcc9b95-32f0-41d4-8d8f-f63fd3a56590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423844683 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_lowpower_counter.3423844683
Directory /workspace/14.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_poweron_counter.3389227029
Short name T653
Test name
Test status
Simulation time 4267067879 ps
CPU time 3.17 seconds
Started Jul 09 06:33:52 PM PDT 24
Finished Jul 09 06:33:57 PM PDT 24
Peak memory 201732 kb
Host smart-c3301e98-247e-4d5f-84f7-a24215719fc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389227029 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_poweron_counter.3389227029
Directory /workspace/14.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/14.adc_ctrl_smoke.3577575660
Short name T725
Test name
Test status
Simulation time 5900480151 ps
CPU time 15.32 seconds
Started Jul 09 06:33:45 PM PDT 24
Finished Jul 09 06:34:02 PM PDT 24
Peak memory 201640 kb
Host smart-ae7a7ae4-d064-421f-b780-28ad69b94c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577575660 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_smoke.3577575660
Directory /workspace/14.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/14.adc_ctrl_stress_all.1546235900
Short name T633
Test name
Test status
Simulation time 182333016763 ps
CPU time 66.01 seconds
Started Jul 09 06:33:51 PM PDT 24
Finished Jul 09 06:34:59 PM PDT 24
Peak memory 201984 kb
Host smart-8d0dba49-99d9-4fce-9d66-9d06b82f4b85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546235900 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.adc_ctrl_stress_all
.1546235900
Directory /workspace/14.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_alert_test.3231956344
Short name T717
Test name
Test status
Simulation time 520190243 ps
CPU time 1.26 seconds
Started Jul 09 06:33:58 PM PDT 24
Finished Jul 09 06:34:02 PM PDT 24
Peak memory 201592 kb
Host smart-ea663c48-f255-478a-a0bb-3459ae5a5b8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231956344 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_alert_test.3231956344
Directory /workspace/15.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.adc_ctrl_clock_gating.3509501375
Short name T158
Test name
Test status
Simulation time 360156160544 ps
CPU time 156.88 seconds
Started Jul 09 06:33:55 PM PDT 24
Finished Jul 09 06:36:35 PM PDT 24
Peak memory 201920 kb
Host smart-b2569574-56e3-48c7-9cc6-ed7cc70900bc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509501375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_clock_gat
ing.3509501375
Directory /workspace/15.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_both.2867050928
Short name T797
Test name
Test status
Simulation time 343721983298 ps
CPU time 217.6 seconds
Started Jul 09 06:33:55 PM PDT 24
Finished Jul 09 06:37:35 PM PDT 24
Peak memory 202136 kb
Host smart-9c8708f4-c6d6-4876-acd3-9240e1ddb6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867050928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_both.2867050928
Directory /workspace/15.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt.1066933981
Short name T306
Test name
Test status
Simulation time 162366595419 ps
CPU time 367.18 seconds
Started Jul 09 06:33:52 PM PDT 24
Finished Jul 09 06:40:01 PM PDT 24
Peak memory 201884 kb
Host smart-2cfa9c35-6b35-49af-a05d-d33eee998fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066933981 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interrupt.1066933981
Directory /workspace/15.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_interrupt_fixed.2265051186
Short name T731
Test name
Test status
Simulation time 485317033020 ps
CPU time 291.68 seconds
Started Jul 09 06:33:56 PM PDT 24
Finished Jul 09 06:38:50 PM PDT 24
Peak memory 201884 kb
Host smart-937fd1c0-1f0a-4c93-b032-440bd64e18c1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265051186 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_interru
pt_fixed.2265051186
Directory /workspace/15.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled.2211002769
Short name T666
Test name
Test status
Simulation time 329349702871 ps
CPU time 195.28 seconds
Started Jul 09 06:33:50 PM PDT 24
Finished Jul 09 06:37:07 PM PDT 24
Peak memory 201872 kb
Host smart-f2da6118-4e82-4b4c-8e28-b04fe04bd940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211002769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled.2211002769
Directory /workspace/15.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_polled_fixed.1388003439
Short name T94
Test name
Test status
Simulation time 323422707425 ps
CPU time 339.34 seconds
Started Jul 09 06:33:51 PM PDT 24
Finished Jul 09 06:39:33 PM PDT 24
Peak memory 201964 kb
Host smart-200874dc-861a-4cc0-a47c-65fdde3a2cff
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388003439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_filters_polled_fix
ed.1388003439
Directory /workspace/15.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_filters_wakeup_fixed.595913213
Short name T478
Test name
Test status
Simulation time 602547148700 ps
CPU time 352.49 seconds
Started Jul 09 06:33:56 PM PDT 24
Finished Jul 09 06:39:52 PM PDT 24
Peak memory 201872 kb
Host smart-0db329d8-b992-45e7-ada4-477234b13b9f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595913213 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.
adc_ctrl_filters_wakeup_fixed.595913213
Directory /workspace/15.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/15.adc_ctrl_lowpower_counter.1695354516
Short name T686
Test name
Test status
Simulation time 42064824952 ps
CPU time 22.57 seconds
Started Jul 09 06:33:55 PM PDT 24
Finished Jul 09 06:34:20 PM PDT 24
Peak memory 201720 kb
Host smart-d6ef4238-63bf-4b37-a4c0-c0a2bf781c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695354516 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_lowpower_counter.1695354516
Directory /workspace/15.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_poweron_counter.991705873
Short name T742
Test name
Test status
Simulation time 4440165683 ps
CPU time 3.37 seconds
Started Jul 09 06:33:57 PM PDT 24
Finished Jul 09 06:34:03 PM PDT 24
Peak memory 201704 kb
Host smart-a21b5129-43e6-416a-9374-bf75e67be6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991705873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_poweron_counter.991705873
Directory /workspace/15.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/15.adc_ctrl_smoke.3691266106
Short name T99
Test name
Test status
Simulation time 5880372619 ps
CPU time 14.43 seconds
Started Jul 09 06:33:50 PM PDT 24
Finished Jul 09 06:34:06 PM PDT 24
Peak memory 201736 kb
Host smart-2fa6dd03-b07a-4e93-ace7-d2dee6e618c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691266106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_smoke.3691266106
Directory /workspace/15.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all.1132848904
Short name T6
Test name
Test status
Simulation time 167726658182 ps
CPU time 112.36 seconds
Started Jul 09 06:33:57 PM PDT 24
Finished Jul 09 06:35:52 PM PDT 24
Peak memory 201896 kb
Host smart-13d6b59f-243d-4ce0-8ea3-a9d9fadbc2f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132848904 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all
.1132848904
Directory /workspace/15.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.adc_ctrl_stress_all_with_rand_reset.644893591
Short name T149
Test name
Test status
Simulation time 75845511721 ps
CPU time 195.95 seconds
Started Jul 09 06:33:57 PM PDT 24
Finished Jul 09 06:37:15 PM PDT 24
Peak memory 210572 kb
Host smart-ef644de6-ca21-49b4-8960-37e616066367
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644893591 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 15.adc_ctrl_stress_all_with_rand_reset.644893591
Directory /workspace/15.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_alert_test.1067964318
Short name T696
Test name
Test status
Simulation time 451952481 ps
CPU time 0.74 seconds
Started Jul 09 06:34:06 PM PDT 24
Finished Jul 09 06:34:08 PM PDT 24
Peak memory 201664 kb
Host smart-3417706b-0702-439b-ab7c-b22b5427885d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067964318 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_alert_test.1067964318
Directory /workspace/16.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_both.2283749737
Short name T303
Test name
Test status
Simulation time 211905183929 ps
CPU time 132.36 seconds
Started Jul 09 06:34:00 PM PDT 24
Finished Jul 09 06:36:15 PM PDT 24
Peak memory 201940 kb
Host smart-bafd2231-7758-4a92-9b97-67e83e46bedb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283749737 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_both.2283749737
Directory /workspace/16.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt.336320505
Short name T148
Test name
Test status
Simulation time 488417285044 ps
CPU time 247.32 seconds
Started Jul 09 06:34:01 PM PDT 24
Finished Jul 09 06:38:10 PM PDT 24
Peak memory 201880 kb
Host smart-99c4add5-cc7f-4341-8b80-ed97ed054f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336320505 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interrupt.336320505
Directory /workspace/16.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_interrupt_fixed.1372271863
Short name T462
Test name
Test status
Simulation time 159707476815 ps
CPU time 151.83 seconds
Started Jul 09 06:34:00 PM PDT 24
Finished Jul 09 06:36:34 PM PDT 24
Peak memory 201736 kb
Host smart-a97e49c4-57d0-41f7-a5ff-ac9d51f1ba98
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372271863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_interru
pt_fixed.1372271863
Directory /workspace/16.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled.2861008829
Short name T146
Test name
Test status
Simulation time 325512060632 ps
CPU time 704.52 seconds
Started Jul 09 06:33:58 PM PDT 24
Finished Jul 09 06:45:46 PM PDT 24
Peak memory 201960 kb
Host smart-88bd6345-8eed-4ab4-a7c1-5057dcda5f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861008829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled.2861008829
Directory /workspace/16.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_polled_fixed.1227641200
Short name T502
Test name
Test status
Simulation time 491933220865 ps
CPU time 1079 seconds
Started Jul 09 06:33:59 PM PDT 24
Finished Jul 09 06:52:01 PM PDT 24
Peak memory 201916 kb
Host smart-8aae9a07-48de-4708-ab40-e08c2198f0c1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227641200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_filters_polled_fix
ed.1227641200
Directory /workspace/16.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_filters_wakeup_fixed.3238247152
Short name T479
Test name
Test status
Simulation time 194688009450 ps
CPU time 455 seconds
Started Jul 09 06:34:00 PM PDT 24
Finished Jul 09 06:41:37 PM PDT 24
Peak memory 201892 kb
Host smart-c192312e-b029-4137-b27d-56e114c99ae8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238247152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16
.adc_ctrl_filters_wakeup_fixed.3238247152
Directory /workspace/16.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/16.adc_ctrl_fsm_reset.1579492471
Short name T716
Test name
Test status
Simulation time 71787657560 ps
CPU time 272.64 seconds
Started Jul 09 06:34:00 PM PDT 24
Finished Jul 09 06:38:35 PM PDT 24
Peak memory 202256 kb
Host smart-85f7eaca-8d6a-4897-b83c-4b4dbbefc35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579492471 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_fsm_reset.1579492471
Directory /workspace/16.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/16.adc_ctrl_lowpower_counter.2987574292
Short name T509
Test name
Test status
Simulation time 48024710090 ps
CPU time 114.73 seconds
Started Jul 09 06:34:02 PM PDT 24
Finished Jul 09 06:35:59 PM PDT 24
Peak memory 201700 kb
Host smart-c1523d8b-193b-417a-b687-eb3a0bee7519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987574292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_lowpower_counter.2987574292
Directory /workspace/16.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_poweron_counter.3092919504
Short name T526
Test name
Test status
Simulation time 3375400166 ps
CPU time 2.64 seconds
Started Jul 09 06:34:00 PM PDT 24
Finished Jul 09 06:34:05 PM PDT 24
Peak memory 201684 kb
Host smart-f51f79c6-f4b5-44de-b6c4-471c942e66ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092919504 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_poweron_counter.3092919504
Directory /workspace/16.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/16.adc_ctrl_smoke.4057248736
Short name T361
Test name
Test status
Simulation time 5895610019 ps
CPU time 2.16 seconds
Started Jul 09 06:33:57 PM PDT 24
Finished Jul 09 06:34:02 PM PDT 24
Peak memory 201724 kb
Host smart-b48b6321-e072-4da7-bfef-ee182423da43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4057248736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_smoke.4057248736
Directory /workspace/16.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/16.adc_ctrl_stress_all_with_rand_reset.625927835
Short name T20
Test name
Test status
Simulation time 89206221409 ps
CPU time 222.21 seconds
Started Jul 09 06:33:59 PM PDT 24
Finished Jul 09 06:37:44 PM PDT 24
Peak memory 218644 kb
Host smart-9f4af42f-7fb0-445d-b178-d8fd42ab3e92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625927835 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 16.adc_ctrl_stress_all_with_rand_reset.625927835
Directory /workspace/16.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_alert_test.462643065
Short name T753
Test name
Test status
Simulation time 381349528 ps
CPU time 1.49 seconds
Started Jul 09 06:34:09 PM PDT 24
Finished Jul 09 06:34:13 PM PDT 24
Peak memory 201880 kb
Host smart-d3fae8f4-492d-48b6-8b65-550b46b13ba9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462643065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_alert_test.462643065
Directory /workspace/17.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.adc_ctrl_clock_gating.1475477363
Short name T172
Test name
Test status
Simulation time 194312338415 ps
CPU time 152.56 seconds
Started Jul 09 06:34:10 PM PDT 24
Finished Jul 09 06:36:44 PM PDT 24
Peak memory 201988 kb
Host smart-cf53847a-e60a-4962-9907-ebcf34e4bde9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475477363 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_clock_gat
ing.1475477363
Directory /workspace/17.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt.2657454261
Short name T699
Test name
Test status
Simulation time 160876419605 ps
CPU time 200.69 seconds
Started Jul 09 06:34:04 PM PDT 24
Finished Jul 09 06:37:26 PM PDT 24
Peak memory 201940 kb
Host smart-d9c481ab-1653-4bf6-a4b4-93f31a6e4c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657454261 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interrupt.2657454261
Directory /workspace/17.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_interrupt_fixed.3135304340
Short name T388
Test name
Test status
Simulation time 160710503616 ps
CPU time 368.97 seconds
Started Jul 09 06:34:05 PM PDT 24
Finished Jul 09 06:40:16 PM PDT 24
Peak memory 201796 kb
Host smart-91012177-d3af-47ae-9ffe-8b0700c7cb2c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135304340 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_interru
pt_fixed.3135304340
Directory /workspace/17.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled.277855106
Short name T705
Test name
Test status
Simulation time 325432567025 ps
CPU time 193.52 seconds
Started Jul 09 06:34:07 PM PDT 24
Finished Jul 09 06:37:22 PM PDT 24
Peak memory 201944 kb
Host smart-9ec6b5fb-e83e-4ce6-b375-154ae3e64e33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277855106 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled.277855106
Directory /workspace/17.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_polled_fixed.4239013613
Short name T404
Test name
Test status
Simulation time 331288028556 ps
CPU time 196.18 seconds
Started Jul 09 06:34:06 PM PDT 24
Finished Jul 09 06:37:24 PM PDT 24
Peak memory 201876 kb
Host smart-ec21bd7e-cc87-4685-a7b9-3d3444897b13
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239013613 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters_polled_fix
ed.4239013613
Directory /workspace/17.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup.2435307887
Short name T760
Test name
Test status
Simulation time 361316607096 ps
CPU time 837.09 seconds
Started Jul 09 06:34:08 PM PDT 24
Finished Jul 09 06:48:06 PM PDT 24
Peak memory 201932 kb
Host smart-6e0a9b82-879a-4414-a286-19dd3775e608
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435307887 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_filters
_wakeup.2435307887
Directory /workspace/17.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/17.adc_ctrl_filters_wakeup_fixed.836429819
Short name T511
Test name
Test status
Simulation time 587446265088 ps
CPU time 343.77 seconds
Started Jul 09 06:34:05 PM PDT 24
Finished Jul 09 06:39:50 PM PDT 24
Peak memory 202096 kb
Host smart-fe11fb53-6260-41de-a0e9-ed26e2023b0f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836429819 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.
adc_ctrl_filters_wakeup_fixed.836429819
Directory /workspace/17.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/17.adc_ctrl_fsm_reset.1695717782
Short name T396
Test name
Test status
Simulation time 125289988399 ps
CPU time 445.17 seconds
Started Jul 09 06:34:09 PM PDT 24
Finished Jul 09 06:41:36 PM PDT 24
Peak memory 202248 kb
Host smart-91a48b91-f43e-4f3e-a1c8-249f3be8ce20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695717782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_fsm_reset.1695717782
Directory /workspace/17.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/17.adc_ctrl_lowpower_counter.3732378171
Short name T385
Test name
Test status
Simulation time 24181050051 ps
CPU time 58.1 seconds
Started Jul 09 06:34:09 PM PDT 24
Finished Jul 09 06:35:10 PM PDT 24
Peak memory 201672 kb
Host smart-c923d1b7-08f7-48bb-9804-d53883ad7358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3732378171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_lowpower_counter.3732378171
Directory /workspace/17.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_poweron_counter.1521291217
Short name T798
Test name
Test status
Simulation time 4192658526 ps
CPU time 5.1 seconds
Started Jul 09 06:34:11 PM PDT 24
Finished Jul 09 06:34:19 PM PDT 24
Peak memory 201744 kb
Host smart-10237e19-31a7-4602-ab8f-6a5f18aeff43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521291217 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_poweron_counter.1521291217
Directory /workspace/17.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/17.adc_ctrl_smoke.1722349111
Short name T45
Test name
Test status
Simulation time 5753330042 ps
CPU time 12.45 seconds
Started Jul 09 06:34:07 PM PDT 24
Finished Jul 09 06:34:21 PM PDT 24
Peak memory 201680 kb
Host smart-fc4d0fad-9e97-4da5-9008-114560c37524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722349111 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_smoke.1722349111
Directory /workspace/17.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all.2405473762
Short name T190
Test name
Test status
Simulation time 495156809878 ps
CPU time 294.64 seconds
Started Jul 09 06:34:11 PM PDT 24
Finished Jul 09 06:39:08 PM PDT 24
Peak memory 201916 kb
Host smart-f7e295d2-9b1e-4cc0-9429-9d14c6d8acf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405473762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all
.2405473762
Directory /workspace/17.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.adc_ctrl_stress_all_with_rand_reset.502305641
Short name T38
Test name
Test status
Simulation time 67154836082 ps
CPU time 40.34 seconds
Started Jul 09 06:34:09 PM PDT 24
Finished Jul 09 06:34:51 PM PDT 24
Peak memory 202052 kb
Host smart-2e9b3a10-7986-4194-8079-d772b6ca4514
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502305641 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 17.adc_ctrl_stress_all_with_rand_reset.502305641
Directory /workspace/17.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_alert_test.2322354152
Short name T611
Test name
Test status
Simulation time 299798592 ps
CPU time 1.22 seconds
Started Jul 09 06:34:12 PM PDT 24
Finished Jul 09 06:34:16 PM PDT 24
Peak memory 201656 kb
Host smart-65a82475-cd97-4832-a8db-edcc45e9b36b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322354152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_alert_test.2322354152
Directory /workspace/18.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.adc_ctrl_clock_gating.2809433069
Short name T281
Test name
Test status
Simulation time 326720856850 ps
CPU time 717.96 seconds
Started Jul 09 06:34:16 PM PDT 24
Finished Jul 09 06:46:15 PM PDT 24
Peak memory 201972 kb
Host smart-23cbd0e5-5d1e-4669-8813-bffd2d09fa4c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809433069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_clock_gat
ing.2809433069
Directory /workspace/18.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_both.3253865506
Short name T691
Test name
Test status
Simulation time 165908051045 ps
CPU time 392.21 seconds
Started Jul 09 06:34:18 PM PDT 24
Finished Jul 09 06:40:52 PM PDT 24
Peak memory 201928 kb
Host smart-865389e7-85e2-49a1-b3c0-9a51c1f27222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253865506 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_both.3253865506
Directory /workspace/18.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt.3291136594
Short name T183
Test name
Test status
Simulation time 488760387553 ps
CPU time 275.47 seconds
Started Jul 09 06:34:18 PM PDT 24
Finished Jul 09 06:38:56 PM PDT 24
Peak memory 201932 kb
Host smart-9b8141b0-b499-4af7-881d-5fa1c4d6e281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291136594 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interrupt.3291136594
Directory /workspace/18.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_interrupt_fixed.3036407818
Short name T607
Test name
Test status
Simulation time 160230329198 ps
CPU time 35.57 seconds
Started Jul 09 06:34:16 PM PDT 24
Finished Jul 09 06:34:54 PM PDT 24
Peak memory 201844 kb
Host smart-0935f564-ab83-43f7-8977-3f5d91548036
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036407818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_interru
pt_fixed.3036407818
Directory /workspace/18.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled.4055908966
Short name T4
Test name
Test status
Simulation time 498142501608 ps
CPU time 1069.82 seconds
Started Jul 09 06:34:11 PM PDT 24
Finished Jul 09 06:52:04 PM PDT 24
Peak memory 201912 kb
Host smart-ede2ed74-880c-4a42-b119-738ce2476576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055908966 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled.4055908966
Directory /workspace/18.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_polled_fixed.67979890
Short name T732
Test name
Test status
Simulation time 494768496599 ps
CPU time 1108.89 seconds
Started Jul 09 06:34:14 PM PDT 24
Finished Jul 09 06:52:45 PM PDT 24
Peak memory 201896 kb
Host smart-57293511-014f-429c-84b9-b281b660a6b2
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=67979890 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_polled_fixed
.67979890
Directory /workspace/18.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup.199701379
Short name T759
Test name
Test status
Simulation time 586747872296 ps
CPU time 634.77 seconds
Started Jul 09 06:34:18 PM PDT 24
Finished Jul 09 06:44:55 PM PDT 24
Peak memory 201840 kb
Host smart-c3b6fa27-f299-4dfa-bfbf-d3b4d1643ae2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199701379 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_filters_
wakeup.199701379
Directory /workspace/18.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/18.adc_ctrl_filters_wakeup_fixed.2740561154
Short name T530
Test name
Test status
Simulation time 617515405139 ps
CPU time 727.09 seconds
Started Jul 09 06:34:18 PM PDT 24
Finished Jul 09 06:46:28 PM PDT 24
Peak memory 201824 kb
Host smart-9733ad96-8cfc-4a61-9e90-f9a34902a3e5
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740561154 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18
.adc_ctrl_filters_wakeup_fixed.2740561154
Directory /workspace/18.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/18.adc_ctrl_fsm_reset.2734521055
Short name T727
Test name
Test status
Simulation time 73177413357 ps
CPU time 362.46 seconds
Started Jul 09 06:34:14 PM PDT 24
Finished Jul 09 06:40:18 PM PDT 24
Peak memory 202284 kb
Host smart-5277af68-446a-4ebd-847f-0896524b2a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734521055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_fsm_reset.2734521055
Directory /workspace/18.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/18.adc_ctrl_lowpower_counter.2828132435
Short name T596
Test name
Test status
Simulation time 30117979731 ps
CPU time 9.33 seconds
Started Jul 09 06:34:18 PM PDT 24
Finished Jul 09 06:34:30 PM PDT 24
Peak memory 201732 kb
Host smart-f95831c4-2934-484f-8200-6747aa9a115c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828132435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_lowpower_counter.2828132435
Directory /workspace/18.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_poweron_counter.3093351743
Short name T441
Test name
Test status
Simulation time 4946300169 ps
CPU time 11.95 seconds
Started Jul 09 06:34:16 PM PDT 24
Finished Jul 09 06:34:30 PM PDT 24
Peak memory 201704 kb
Host smart-b217eb41-24be-4dc3-96cd-e1be3e5ac830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093351743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_poweron_counter.3093351743
Directory /workspace/18.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/18.adc_ctrl_smoke.685420797
Short name T643
Test name
Test status
Simulation time 5918796163 ps
CPU time 4.35 seconds
Started Jul 09 06:34:12 PM PDT 24
Finished Jul 09 06:34:19 PM PDT 24
Peak memory 201712 kb
Host smart-6dba3767-b6c6-4e12-a81b-7e9ae3838862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685420797 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_smoke.685420797
Directory /workspace/18.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/18.adc_ctrl_stress_all.3187514420
Short name T662
Test name
Test status
Simulation time 189092698237 ps
CPU time 100.35 seconds
Started Jul 09 06:34:13 PM PDT 24
Finished Jul 09 06:35:56 PM PDT 24
Peak memory 201960 kb
Host smart-715b72fd-8cf5-4880-b0bb-f051c323cfbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187514420 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.adc_ctrl_stress_all
.3187514420
Directory /workspace/18.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_alert_test.4007545162
Short name T451
Test name
Test status
Simulation time 418583645 ps
CPU time 0.85 seconds
Started Jul 09 06:34:30 PM PDT 24
Finished Jul 09 06:34:32 PM PDT 24
Peak memory 201660 kb
Host smart-0f375b71-095b-4709-8107-c2c26e565127
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007545162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_alert_test.4007545162
Directory /workspace/19.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.adc_ctrl_clock_gating.3288880757
Short name T782
Test name
Test status
Simulation time 344899083221 ps
CPU time 379 seconds
Started Jul 09 06:34:19 PM PDT 24
Finished Jul 09 06:40:41 PM PDT 24
Peak memory 201900 kb
Host smart-d453e430-3070-4f42-b32e-eac676593d28
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3288880757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_clock_gat
ing.3288880757
Directory /workspace/19.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt.3724522801
Short name T271
Test name
Test status
Simulation time 165158112334 ps
CPU time 185.87 seconds
Started Jul 09 06:34:19 PM PDT 24
Finished Jul 09 06:37:28 PM PDT 24
Peak memory 201952 kb
Host smart-f8dc0af3-c437-4a46-9157-20439706a1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724522801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interrupt.3724522801
Directory /workspace/19.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_interrupt_fixed.2345384913
Short name T758
Test name
Test status
Simulation time 162692698683 ps
CPU time 199.35 seconds
Started Jul 09 06:34:20 PM PDT 24
Finished Jul 09 06:37:42 PM PDT 24
Peak memory 201896 kb
Host smart-1b143551-edad-4574-a1e1-48b3f40865b3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345384913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_interru
pt_fixed.2345384913
Directory /workspace/19.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled.1197799333
Short name T724
Test name
Test status
Simulation time 320893994960 ps
CPU time 775.65 seconds
Started Jul 09 06:34:18 PM PDT 24
Finished Jul 09 06:47:17 PM PDT 24
Peak memory 201936 kb
Host smart-fa6d489b-67d6-48cc-aeea-666c8fcb4718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197799333 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled.1197799333
Directory /workspace/19.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_polled_fixed.784511592
Short name T558
Test name
Test status
Simulation time 485130670821 ps
CPU time 570.42 seconds
Started Jul 09 06:34:20 PM PDT 24
Finished Jul 09 06:43:53 PM PDT 24
Peak memory 201908 kb
Host smart-92f5714e-a56e-4663-9202-61925c649564
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=784511592 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_polled_fixe
d.784511592
Directory /workspace/19.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup.241366338
Short name T302
Test name
Test status
Simulation time 167642395423 ps
CPU time 342.07 seconds
Started Jul 09 06:34:20 PM PDT 24
Finished Jul 09 06:40:05 PM PDT 24
Peak memory 201884 kb
Host smart-ee82a5b5-8750-4da1-bce1-0e8175ad9bd9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241366338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_filters_
wakeup.241366338
Directory /workspace/19.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/19.adc_ctrl_filters_wakeup_fixed.1617386118
Short name T584
Test name
Test status
Simulation time 408415916481 ps
CPU time 239.01 seconds
Started Jul 09 06:34:19 PM PDT 24
Finished Jul 09 06:38:21 PM PDT 24
Peak memory 201884 kb
Host smart-0f1d0406-4d91-4390-a8f6-d0002ce47417
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617386118 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19
.adc_ctrl_filters_wakeup_fixed.1617386118
Directory /workspace/19.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/19.adc_ctrl_fsm_reset.967780928
Short name T199
Test name
Test status
Simulation time 99303735149 ps
CPU time 495.57 seconds
Started Jul 09 06:34:23 PM PDT 24
Finished Jul 09 06:42:41 PM PDT 24
Peak memory 202252 kb
Host smart-8832ff2d-033e-4dca-b370-b0c1b4c62d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967780928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_fsm_reset.967780928
Directory /workspace/19.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/19.adc_ctrl_lowpower_counter.2635351476
Short name T423
Test name
Test status
Simulation time 36774984407 ps
CPU time 43.09 seconds
Started Jul 09 06:34:23 PM PDT 24
Finished Jul 09 06:35:08 PM PDT 24
Peak memory 201756 kb
Host smart-626d4a99-99c0-4206-884c-2757a62ccc97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635351476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_lowpower_counter.2635351476
Directory /workspace/19.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_poweron_counter.1220251476
Short name T442
Test name
Test status
Simulation time 4450218521 ps
CPU time 3.52 seconds
Started Jul 09 06:34:18 PM PDT 24
Finished Jul 09 06:34:24 PM PDT 24
Peak memory 201696 kb
Host smart-cbb4d8a6-615b-45d7-8f86-de8e74b474a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220251476 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_poweron_counter.1220251476
Directory /workspace/19.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/19.adc_ctrl_smoke.2732153860
Short name T591
Test name
Test status
Simulation time 5846708924 ps
CPU time 2.02 seconds
Started Jul 09 06:34:15 PM PDT 24
Finished Jul 09 06:34:19 PM PDT 24
Peak memory 201552 kb
Host smart-fa5d7458-3ba4-46cd-8907-1566cb5caf33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732153860 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_smoke.2732153860
Directory /workspace/19.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all.549895836
Short name T173
Test name
Test status
Simulation time 332887163341 ps
CPU time 234.17 seconds
Started Jul 09 06:34:28 PM PDT 24
Finished Jul 09 06:38:24 PM PDT 24
Peak memory 201900 kb
Host smart-6bff65e0-c7b5-4d33-a53e-55acf8d79860
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549895836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all.
549895836
Directory /workspace/19.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.adc_ctrl_stress_all_with_rand_reset.3823821111
Short name T670
Test name
Test status
Simulation time 792737462692 ps
CPU time 226.04 seconds
Started Jul 09 06:34:27 PM PDT 24
Finished Jul 09 06:38:15 PM PDT 24
Peak memory 218168 kb
Host smart-39dab472-fc85-4acd-b951-519795ea8922
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823821111 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 19.adc_ctrl_stress_all_with_rand_reset.3823821111
Directory /workspace/19.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_alert_test.3345642313
Short name T464
Test name
Test status
Simulation time 423131210 ps
CPU time 0.77 seconds
Started Jul 09 06:32:58 PM PDT 24
Finished Jul 09 06:33:15 PM PDT 24
Peak memory 201668 kb
Host smart-de195674-c53f-4ff3-bcdf-7a686cfa86bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345642313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_alert_test.3345642313
Directory /workspace/2.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_both.4037485192
Short name T265
Test name
Test status
Simulation time 552528354821 ps
CPU time 632.71 seconds
Started Jul 09 06:32:55 PM PDT 24
Finished Jul 09 06:43:44 PM PDT 24
Peak memory 201888 kb
Host smart-602beec3-32ec-4620-8cc4-bede21c107e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037485192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_both.4037485192
Directory /workspace/2.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt.2575313041
Short name T27
Test name
Test status
Simulation time 499321372397 ps
CPU time 552.56 seconds
Started Jul 09 06:32:55 PM PDT 24
Finished Jul 09 06:42:24 PM PDT 24
Peak memory 201892 kb
Host smart-3ac18bfd-c3e7-4a40-8661-4fa0a77ff649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575313041 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrupt.2575313041
Directory /workspace/2.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_interrupt_fixed.2083221403
Short name T381
Test name
Test status
Simulation time 328408211753 ps
CPU time 371.25 seconds
Started Jul 09 06:32:53 PM PDT 24
Finished Jul 09 06:39:21 PM PDT 24
Peak memory 201892 kb
Host smart-5e8c1e5d-e4d5-40c8-bb6a-eef8cee8eab1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083221403 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_interrup
t_fixed.2083221403
Directory /workspace/2.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled.269065879
Short name T506
Test name
Test status
Simulation time 162868598332 ps
CPU time 356.96 seconds
Started Jul 09 06:32:53 PM PDT 24
Finished Jul 09 06:39:07 PM PDT 24
Peak memory 201880 kb
Host smart-74a9fb8c-5168-4e78-a38a-82ef00dd579d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269065879 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled.269065879
Directory /workspace/2.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_polled_fixed.1868279815
Short name T469
Test name
Test status
Simulation time 159772687524 ps
CPU time 94.69 seconds
Started Jul 09 06:32:55 PM PDT 24
Finished Jul 09 06:34:46 PM PDT 24
Peak memory 201884 kb
Host smart-27a24820-8d71-4cd2-a5b0-e53fb7c96b55
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868279815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_polled_fixe
d.1868279815
Directory /workspace/2.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup.4059707362
Short name T251
Test name
Test status
Simulation time 344805004910 ps
CPU time 717.19 seconds
Started Jul 09 06:32:54 PM PDT 24
Finished Jul 09 06:45:08 PM PDT 24
Peak memory 201936 kb
Host smart-9171adc1-66e1-4e91-9d98-8af81b0f06f9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059707362 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_filters_
wakeup.4059707362
Directory /workspace/2.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/2.adc_ctrl_filters_wakeup_fixed.3725935763
Short name T733
Test name
Test status
Simulation time 206289849229 ps
CPU time 496.52 seconds
Started Jul 09 06:34:27 PM PDT 24
Finished Jul 09 06:42:46 PM PDT 24
Peak memory 201904 kb
Host smart-b452127e-fc10-4538-9b52-436d4191865f
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725935763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.
adc_ctrl_filters_wakeup_fixed.3725935763
Directory /workspace/2.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/2.adc_ctrl_fsm_reset.3678528126
Short name T456
Test name
Test status
Simulation time 110608530853 ps
CPU time 544.88 seconds
Started Jul 09 06:33:00 PM PDT 24
Finished Jul 09 06:42:20 PM PDT 24
Peak memory 202212 kb
Host smart-84e1af22-2bbf-4660-92c1-d7916c0360e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678528126 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_fsm_reset.3678528126
Directory /workspace/2.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/2.adc_ctrl_lowpower_counter.2021746545
Short name T598
Test name
Test status
Simulation time 25077883251 ps
CPU time 29.85 seconds
Started Jul 09 06:32:58 PM PDT 24
Finished Jul 09 06:33:44 PM PDT 24
Peak memory 201736 kb
Host smart-6883a9f4-13e0-4280-9c9e-264ca7372939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021746545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_lowpower_counter.2021746545
Directory /workspace/2.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_poweron_counter.3473791827
Short name T487
Test name
Test status
Simulation time 3681593863 ps
CPU time 2.74 seconds
Started Jul 09 06:33:00 PM PDT 24
Finished Jul 09 06:33:18 PM PDT 24
Peak memory 201716 kb
Host smart-30a4d19e-ff9b-4906-ba0c-cddacec2435f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473791827 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_poweron_counter.3473791827
Directory /workspace/2.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/2.adc_ctrl_sec_cm.2097389080
Short name T77
Test name
Test status
Simulation time 8091935905 ps
CPU time 4.47 seconds
Started Jul 09 06:32:58 PM PDT 24
Finished Jul 09 06:33:19 PM PDT 24
Peak memory 218292 kb
Host smart-6729a182-dafb-49e8-b8a7-0c58f2379d06
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097389080 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_sec_cm.2097389080
Directory /workspace/2.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.adc_ctrl_smoke.40489763
Short name T625
Test name
Test status
Simulation time 5936668352 ps
CPU time 14.72 seconds
Started Jul 09 06:32:56 PM PDT 24
Finished Jul 09 06:33:27 PM PDT 24
Peak memory 201724 kb
Host smart-026c0fda-f0e7-48e8-b0a2-5e57379ada4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40489763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_smoke.40489763
Directory /workspace/2.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/2.adc_ctrl_stress_all.1026460974
Short name T711
Test name
Test status
Simulation time 341890225984 ps
CPU time 195.93 seconds
Started Jul 09 06:32:57 PM PDT 24
Finished Jul 09 06:36:29 PM PDT 24
Peak memory 201940 kb
Host smart-1c4344ab-e9ee-45ba-a5a5-6e1306db3f55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026460974 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.adc_ctrl_stress_all.
1026460974
Directory /workspace/2.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_alert_test.3382237168
Short name T519
Test name
Test status
Simulation time 291715407 ps
CPU time 1.27 seconds
Started Jul 09 06:34:37 PM PDT 24
Finished Jul 09 06:34:40 PM PDT 24
Peak memory 201664 kb
Host smart-e382eb07-7c57-49f4-9c7b-00bec8103ba6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382237168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_alert_test.3382237168
Directory /workspace/20.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.adc_ctrl_clock_gating.723532599
Short name T29
Test name
Test status
Simulation time 180947645382 ps
CPU time 51.83 seconds
Started Jul 09 06:34:32 PM PDT 24
Finished Jul 09 06:35:25 PM PDT 24
Peak memory 201980 kb
Host smart-1b6981ae-eb72-444b-a945-95e3224b9833
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723532599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_clock_gati
ng.723532599
Directory /workspace/20.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_both.1482858719
Short name T279
Test name
Test status
Simulation time 179205112437 ps
CPU time 95.04 seconds
Started Jul 09 06:34:34 PM PDT 24
Finished Jul 09 06:36:10 PM PDT 24
Peak memory 201888 kb
Host smart-d7ec4f34-8747-42b8-a49a-ce7283e34e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482858719 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_both.1482858719
Directory /workspace/20.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_interrupt_fixed.2388264995
Short name T408
Test name
Test status
Simulation time 489927638582 ps
CPU time 282.3 seconds
Started Jul 09 06:34:31 PM PDT 24
Finished Jul 09 06:39:15 PM PDT 24
Peak memory 201896 kb
Host smart-99edad60-bc3e-4e90-a346-411890afe6a0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388264995 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_interru
pt_fixed.2388264995
Directory /workspace/20.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled.1654916681
Short name T341
Test name
Test status
Simulation time 484936584801 ps
CPU time 324.87 seconds
Started Jul 09 06:34:29 PM PDT 24
Finished Jul 09 06:39:55 PM PDT 24
Peak memory 201884 kb
Host smart-602371c5-038a-4122-9897-4cda813f7ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654916681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled.1654916681
Directory /workspace/20.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_polled_fixed.3414925824
Short name T777
Test name
Test status
Simulation time 169140061261 ps
CPU time 405.39 seconds
Started Jul 09 06:34:30 PM PDT 24
Finished Jul 09 06:41:17 PM PDT 24
Peak memory 202076 kb
Host smart-2ac37ac4-5dcb-41a3-ac44-7ea89ec43d2b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414925824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_filters_polled_fix
ed.3414925824
Directory /workspace/20.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_filters_wakeup_fixed.3670633655
Short name T720
Test name
Test status
Simulation time 601598680367 ps
CPU time 647.04 seconds
Started Jul 09 06:34:34 PM PDT 24
Finished Jul 09 06:45:22 PM PDT 24
Peak memory 201844 kb
Host smart-66a116c3-cd6a-478e-9e3f-2976a609e547
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670633655 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20
.adc_ctrl_filters_wakeup_fixed.3670633655
Directory /workspace/20.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/20.adc_ctrl_fsm_reset.4127442563
Short name T106
Test name
Test status
Simulation time 120760652037 ps
CPU time 393.55 seconds
Started Jul 09 06:34:35 PM PDT 24
Finished Jul 09 06:41:09 PM PDT 24
Peak memory 202232 kb
Host smart-755e8fcd-4493-435c-a2a9-1d8b3a22f3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127442563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_fsm_reset.4127442563
Directory /workspace/20.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/20.adc_ctrl_lowpower_counter.1641860934
Short name T654
Test name
Test status
Simulation time 40162423990 ps
CPU time 8.4 seconds
Started Jul 09 06:34:34 PM PDT 24
Finished Jul 09 06:34:43 PM PDT 24
Peak memory 201704 kb
Host smart-ee699dc7-8e3f-4fcf-ae8a-bf8925d8f7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641860934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_lowpower_counter.1641860934
Directory /workspace/20.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_poweron_counter.1175491266
Short name T467
Test name
Test status
Simulation time 3782662536 ps
CPU time 3 seconds
Started Jul 09 06:34:31 PM PDT 24
Finished Jul 09 06:34:36 PM PDT 24
Peak memory 201724 kb
Host smart-c5048f1e-7839-4dc4-bb16-822135e8d81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175491266 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_poweron_counter.1175491266
Directory /workspace/20.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/20.adc_ctrl_smoke.3104060317
Short name T704
Test name
Test status
Simulation time 6015447095 ps
CPU time 2.01 seconds
Started Jul 09 06:34:28 PM PDT 24
Finished Jul 09 06:34:32 PM PDT 24
Peak memory 201732 kb
Host smart-e73873ce-71e4-488c-99be-8c4672e556f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104060317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_smoke.3104060317
Directory /workspace/20.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all.2949106794
Short name T708
Test name
Test status
Simulation time 176799950947 ps
CPU time 266.47 seconds
Started Jul 09 06:34:33 PM PDT 24
Finished Jul 09 06:39:00 PM PDT 24
Peak memory 201908 kb
Host smart-306fe2da-c3d5-401b-8aa0-7dd79535b8ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949106794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all
.2949106794
Directory /workspace/20.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.adc_ctrl_stress_all_with_rand_reset.3245780363
Short name T332
Test name
Test status
Simulation time 24754451076 ps
CPU time 52.33 seconds
Started Jul 09 06:34:32 PM PDT 24
Finished Jul 09 06:35:26 PM PDT 24
Peak memory 210500 kb
Host smart-93500ee9-c7ce-4680-9ba9-a370c0ce6e0c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245780363 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 20.adc_ctrl_stress_all_with_rand_reset.3245780363
Directory /workspace/20.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_alert_test.401123529
Short name T762
Test name
Test status
Simulation time 361547435 ps
CPU time 1.38 seconds
Started Jul 09 06:34:46 PM PDT 24
Finished Jul 09 06:34:50 PM PDT 24
Peak memory 201684 kb
Host smart-1b3bc2a0-fe7c-45df-b10b-c702a2eeb14d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401123529 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_alert_test.401123529
Directory /workspace/21.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.adc_ctrl_clock_gating.2913356013
Short name T294
Test name
Test status
Simulation time 178071903471 ps
CPU time 197.68 seconds
Started Jul 09 06:34:41 PM PDT 24
Finished Jul 09 06:38:00 PM PDT 24
Peak memory 201932 kb
Host smart-3a636189-40b6-4951-8375-e583572a9e5d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913356013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_clock_gat
ing.2913356013
Directory /workspace/21.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt.2686388047
Short name T700
Test name
Test status
Simulation time 326848510258 ps
CPU time 776.17 seconds
Started Jul 09 06:34:38 PM PDT 24
Finished Jul 09 06:47:35 PM PDT 24
Peak memory 201924 kb
Host smart-b3f67a46-0497-4546-a783-bf4d0350891a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686388047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interrupt.2686388047
Directory /workspace/21.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_interrupt_fixed.2152386855
Short name T518
Test name
Test status
Simulation time 325179143158 ps
CPU time 768.66 seconds
Started Jul 09 06:34:38 PM PDT 24
Finished Jul 09 06:47:27 PM PDT 24
Peak memory 201904 kb
Host smart-5692dc02-24c1-437b-9093-777c1fff22c5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152386855 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_interru
pt_fixed.2152386855
Directory /workspace/21.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled.2114813329
Short name T159
Test name
Test status
Simulation time 330471465181 ps
CPU time 750.08 seconds
Started Jul 09 06:34:39 PM PDT 24
Finished Jul 09 06:47:10 PM PDT 24
Peak memory 201936 kb
Host smart-ce82ab70-cb53-4211-898c-c45c4039ee93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114813329 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled.2114813329
Directory /workspace/21.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_polled_fixed.1495557896
Short name T360
Test name
Test status
Simulation time 163496660853 ps
CPU time 35.21 seconds
Started Jul 09 06:34:37 PM PDT 24
Finished Jul 09 06:35:13 PM PDT 24
Peak memory 201900 kb
Host smart-8126da94-55e1-476c-ab94-3fd71b2acacf
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495557896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_polled_fix
ed.1495557896
Directory /workspace/21.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup.6261834
Short name T507
Test name
Test status
Simulation time 380087369935 ps
CPU time 223.16 seconds
Started Jul 09 06:34:36 PM PDT 24
Finished Jul 09 06:38:20 PM PDT 24
Peak memory 201952 kb
Host smart-2d505d23-e0b1-4571-abed-be2db6102ebb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6261834 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_w
akeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_filters_wa
keup.6261834
Directory /workspace/21.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/21.adc_ctrl_filters_wakeup_fixed.3456438685
Short name T713
Test name
Test status
Simulation time 191661801146 ps
CPU time 116.85 seconds
Started Jul 09 06:34:43 PM PDT 24
Finished Jul 09 06:36:41 PM PDT 24
Peak memory 201884 kb
Host smart-665dda1e-58a8-4e2c-8f34-2922f3b1a2cc
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456438685 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21
.adc_ctrl_filters_wakeup_fixed.3456438685
Directory /workspace/21.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/21.adc_ctrl_fsm_reset.1924233152
Short name T197
Test name
Test status
Simulation time 95777920378 ps
CPU time 496.64 seconds
Started Jul 09 06:34:48 PM PDT 24
Finished Jul 09 06:43:07 PM PDT 24
Peak memory 202296 kb
Host smart-25234ce6-7720-4777-8441-92b6a5e8c22c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924233152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_fsm_reset.1924233152
Directory /workspace/21.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/21.adc_ctrl_lowpower_counter.1449756670
Short name T618
Test name
Test status
Simulation time 22680866503 ps
CPU time 27.23 seconds
Started Jul 09 06:34:46 PM PDT 24
Finished Jul 09 06:35:16 PM PDT 24
Peak memory 201720 kb
Host smart-9f83ce2f-3082-4a03-a340-f6635c059747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449756670 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_lowpower_counter.1449756670
Directory /workspace/21.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_poweron_counter.2104941063
Short name T748
Test name
Test status
Simulation time 5096592845 ps
CPU time 6.75 seconds
Started Jul 09 06:34:46 PM PDT 24
Finished Jul 09 06:34:56 PM PDT 24
Peak memory 201948 kb
Host smart-1d2d8156-e3ec-438d-be6b-e4a818b4ab01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104941063 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_poweron_counter.2104941063
Directory /workspace/21.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/21.adc_ctrl_smoke.749803928
Short name T728
Test name
Test status
Simulation time 6071807789 ps
CPU time 15.86 seconds
Started Jul 09 06:34:37 PM PDT 24
Finished Jul 09 06:34:54 PM PDT 24
Peak memory 201724 kb
Host smart-ca6199b9-9603-4142-885d-fe55355201a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749803928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_smoke.749803928
Directory /workspace/21.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all.2493812194
Short name T285
Test name
Test status
Simulation time 190638095477 ps
CPU time 55.23 seconds
Started Jul 09 06:34:45 PM PDT 24
Finished Jul 09 06:35:43 PM PDT 24
Peak memory 201928 kb
Host smart-794ea640-693f-4721-b9c6-1c665ce6d6a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493812194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all
.2493812194
Directory /workspace/21.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/21.adc_ctrl_stress_all_with_rand_reset.1366952098
Short name T343
Test name
Test status
Simulation time 21723790778 ps
CPU time 36.29 seconds
Started Jul 09 06:34:46 PM PDT 24
Finished Jul 09 06:35:25 PM PDT 24
Peak memory 202124 kb
Host smart-6d82defa-426d-4cf7-8568-36c89734ca5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366952098 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 21.adc_ctrl_stress_all_with_rand_reset.1366952098
Directory /workspace/21.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_alert_test.2633566908
Short name T671
Test name
Test status
Simulation time 544772982 ps
CPU time 0.91 seconds
Started Jul 09 06:35:00 PM PDT 24
Finished Jul 09 06:35:02 PM PDT 24
Peak memory 201620 kb
Host smart-4d4a46ee-28d5-447b-94e6-d6ecef2c8688
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633566908 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_alert_test.2633566908
Directory /workspace/22.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.adc_ctrl_clock_gating.1217853657
Short name T652
Test name
Test status
Simulation time 349196621949 ps
CPU time 200.5 seconds
Started Jul 09 06:34:55 PM PDT 24
Finished Jul 09 06:38:18 PM PDT 24
Peak memory 201920 kb
Host smart-fa807b42-719e-4694-a973-20f166fecb01
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217853657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_clock_gat
ing.1217853657
Directory /workspace/22.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_both.3336581415
Short name T640
Test name
Test status
Simulation time 165202237397 ps
CPU time 163.12 seconds
Started Jul 09 06:34:55 PM PDT 24
Finished Jul 09 06:37:41 PM PDT 24
Peak memory 201940 kb
Host smart-99f4ecba-8ba4-4a0d-a643-32ae66e4a524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336581415 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_both.3336581415
Directory /workspace/22.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt.941269935
Short name T304
Test name
Test status
Simulation time 503403067334 ps
CPU time 1203.2 seconds
Started Jul 09 06:34:56 PM PDT 24
Finished Jul 09 06:55:02 PM PDT 24
Peak memory 201936 kb
Host smart-b2011d29-7d81-4962-8ff5-478bd86a1510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941269935 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrupt.941269935
Directory /workspace/22.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_interrupt_fixed.694594764
Short name T391
Test name
Test status
Simulation time 161980027982 ps
CPU time 93.8 seconds
Started Jul 09 06:34:55 PM PDT 24
Finished Jul 09 06:36:31 PM PDT 24
Peak memory 201932 kb
Host smart-e4916ebc-1f55-4bc6-8efa-1c4913669a4e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=694594764 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_interrup
t_fixed.694594764
Directory /workspace/22.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled.1034123573
Short name T257
Test name
Test status
Simulation time 166007719718 ps
CPU time 363.3 seconds
Started Jul 09 06:34:50 PM PDT 24
Finished Jul 09 06:40:56 PM PDT 24
Peak memory 201916 kb
Host smart-da759130-1106-4565-a4ef-7f93cd7c084b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034123573 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled.1034123573
Directory /workspace/22.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_polled_fixed.1555329300
Short name T144
Test name
Test status
Simulation time 330131843373 ps
CPU time 115.69 seconds
Started Jul 09 06:34:55 PM PDT 24
Finished Jul 09 06:36:54 PM PDT 24
Peak memory 201888 kb
Host smart-86e3c2b8-48c9-49bf-9955-b833e40e4161
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555329300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters_polled_fix
ed.1555329300
Directory /workspace/22.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup.1235626124
Short name T745
Test name
Test status
Simulation time 202982316776 ps
CPU time 110.84 seconds
Started Jul 09 06:34:54 PM PDT 24
Finished Jul 09 06:36:48 PM PDT 24
Peak memory 201928 kb
Host smart-a69f13e8-f9a0-4f80-a391-53ebc244ca0e
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235626124 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_filters
_wakeup.1235626124
Directory /workspace/22.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/22.adc_ctrl_filters_wakeup_fixed.1231979164
Short name T424
Test name
Test status
Simulation time 605219442968 ps
CPU time 367.93 seconds
Started Jul 09 06:35:32 PM PDT 24
Finished Jul 09 06:41:41 PM PDT 24
Peak memory 201920 kb
Host smart-624dbdd7-715a-44d8-9480-a865a2efc6c3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231979164 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22
.adc_ctrl_filters_wakeup_fixed.1231979164
Directory /workspace/22.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/22.adc_ctrl_fsm_reset.511639774
Short name T50
Test name
Test status
Simulation time 68953457148 ps
CPU time 241.54 seconds
Started Jul 09 06:35:00 PM PDT 24
Finished Jul 09 06:39:02 PM PDT 24
Peak memory 202260 kb
Host smart-861f409f-591a-46f1-b177-a71d43be7662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511639774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_fsm_reset.511639774
Directory /workspace/22.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/22.adc_ctrl_lowpower_counter.1953361621
Short name T26
Test name
Test status
Simulation time 45454624922 ps
CPU time 48.54 seconds
Started Jul 09 06:34:57 PM PDT 24
Finished Jul 09 06:35:48 PM PDT 24
Peak memory 201716 kb
Host smart-320710a2-08ca-437c-86e8-29f12c5e32fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953361621 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_lowpower_counter.1953361621
Directory /workspace/22.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_poweron_counter.3533174065
Short name T542
Test name
Test status
Simulation time 3173934574 ps
CPU time 8.03 seconds
Started Jul 09 06:34:55 PM PDT 24
Finished Jul 09 06:35:06 PM PDT 24
Peak memory 201668 kb
Host smart-fe9e6cf3-7b39-41c3-9cf1-5c755a0cbe41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533174065 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_poweron_counter.3533174065
Directory /workspace/22.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/22.adc_ctrl_smoke.3664163240
Short name T413
Test name
Test status
Simulation time 5796293738 ps
CPU time 12.86 seconds
Started Jul 09 06:34:52 PM PDT 24
Finished Jul 09 06:35:08 PM PDT 24
Peak memory 201616 kb
Host smart-1b67b491-6207-42f4-a6c4-04b174476d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664163240 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_smoke.3664163240
Directory /workspace/22.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all.2999556531
Short name T288
Test name
Test status
Simulation time 178408112905 ps
CPU time 56.28 seconds
Started Jul 09 06:35:02 PM PDT 24
Finished Jul 09 06:36:00 PM PDT 24
Peak memory 201900 kb
Host smart-9315b854-3e58-4955-ac7e-570581893152
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999556531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all
.2999556531
Directory /workspace/22.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.adc_ctrl_stress_all_with_rand_reset.3687479420
Short name T17
Test name
Test status
Simulation time 25398966181 ps
CPU time 59.44 seconds
Started Jul 09 06:35:00 PM PDT 24
Finished Jul 09 06:36:00 PM PDT 24
Peak memory 210280 kb
Host smart-da70adcc-9f6a-4022-ba88-4bdded151257
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687479420 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 22.adc_ctrl_stress_all_with_rand_reset.3687479420
Directory /workspace/22.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_alert_test.723232515
Short name T549
Test name
Test status
Simulation time 381109548 ps
CPU time 0.82 seconds
Started Jul 09 06:35:18 PM PDT 24
Finished Jul 09 06:35:21 PM PDT 24
Peak memory 201684 kb
Host smart-c5721dd3-7e28-4f61-a262-97822f22d1bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723232515 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_alert_test.723232515
Directory /workspace/23.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.adc_ctrl_clock_gating.1565247359
Short name T240
Test name
Test status
Simulation time 163334259873 ps
CPU time 370.06 seconds
Started Jul 09 06:35:17 PM PDT 24
Finished Jul 09 06:41:30 PM PDT 24
Peak memory 201832 kb
Host smart-6e9dd9cb-9fc7-4aa1-9ae1-9ff7b9acbdf6
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565247359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_clock_gat
ing.1565247359
Directory /workspace/23.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_both.3180347780
Short name T327
Test name
Test status
Simulation time 161403922500 ps
CPU time 172.49 seconds
Started Jul 09 06:35:16 PM PDT 24
Finished Jul 09 06:38:11 PM PDT 24
Peak memory 201928 kb
Host smart-c7614ef4-573b-4ecf-9219-4be27989aca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180347780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_both.3180347780
Directory /workspace/23.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt.3388242841
Short name T209
Test name
Test status
Simulation time 167191104385 ps
CPU time 349.98 seconds
Started Jul 09 06:35:06 PM PDT 24
Finished Jul 09 06:40:57 PM PDT 24
Peak memory 201900 kb
Host smart-1ca2eca1-8743-4fd4-9aff-84fd16240f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388242841 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interrupt.3388242841
Directory /workspace/23.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_interrupt_fixed.3115972844
Short name T457
Test name
Test status
Simulation time 333744658854 ps
CPU time 194.89 seconds
Started Jul 09 06:35:10 PM PDT 24
Finished Jul 09 06:38:26 PM PDT 24
Peak memory 201916 kb
Host smart-47f2e253-b09c-4239-9a15-3999aaa1130e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115972844 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_interru
pt_fixed.3115972844
Directory /workspace/23.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled.2089472307
Short name T266
Test name
Test status
Simulation time 161093061066 ps
CPU time 21.98 seconds
Started Jul 09 06:35:05 PM PDT 24
Finished Jul 09 06:35:28 PM PDT 24
Peak memory 201976 kb
Host smart-4d33eb32-6a42-469e-944d-39b281bcc51a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089472307 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled.2089472307
Directory /workspace/23.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_polled_fixed.207025878
Short name T22
Test name
Test status
Simulation time 162630652824 ps
CPU time 360.84 seconds
Started Jul 09 06:35:05 PM PDT 24
Finished Jul 09 06:41:07 PM PDT 24
Peak memory 201848 kb
Host smart-48e6166c-4c95-4593-a7ad-2315c5a5406e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=207025878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters_polled_fixe
d.207025878
Directory /workspace/23.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup.3824188576
Short name T764
Test name
Test status
Simulation time 381631764791 ps
CPU time 224.96 seconds
Started Jul 09 06:35:15 PM PDT 24
Finished Jul 09 06:39:03 PM PDT 24
Peak memory 201980 kb
Host smart-dc7d1f7a-59bf-43c7-b588-6734d9cd78aa
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824188576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_filters
_wakeup.3824188576
Directory /workspace/23.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/23.adc_ctrl_filters_wakeup_fixed.2843014408
Short name T541
Test name
Test status
Simulation time 411432576960 ps
CPU time 861.98 seconds
Started Jul 09 06:35:15 PM PDT 24
Finished Jul 09 06:49:40 PM PDT 24
Peak memory 201884 kb
Host smart-40267b78-7095-47c9-9db4-48ce9703755c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843014408 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23
.adc_ctrl_filters_wakeup_fixed.2843014408
Directory /workspace/23.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/23.adc_ctrl_fsm_reset.1468794926
Short name T604
Test name
Test status
Simulation time 97084799846 ps
CPU time 520.99 seconds
Started Jul 09 06:35:19 PM PDT 24
Finished Jul 09 06:44:02 PM PDT 24
Peak memory 202272 kb
Host smart-b912bf09-86e3-4e06-bdd8-aba4838970aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468794926 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_fsm_reset.1468794926
Directory /workspace/23.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/23.adc_ctrl_lowpower_counter.3172165878
Short name T545
Test name
Test status
Simulation time 30751682737 ps
CPU time 17.75 seconds
Started Jul 09 06:35:17 PM PDT 24
Finished Jul 09 06:35:38 PM PDT 24
Peak memory 201648 kb
Host smart-5af1336e-c0d7-462e-a65e-b28f72aeb6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172165878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_lowpower_counter.3172165878
Directory /workspace/23.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_poweron_counter.3247103591
Short name T796
Test name
Test status
Simulation time 5232725664 ps
CPU time 2.64 seconds
Started Jul 09 06:35:15 PM PDT 24
Finished Jul 09 06:35:20 PM PDT 24
Peak memory 201736 kb
Host smart-a664cf4f-c24c-4383-b895-7c9859cc91ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247103591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_poweron_counter.3247103591
Directory /workspace/23.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/23.adc_ctrl_smoke.1021735521
Short name T41
Test name
Test status
Simulation time 5743924718 ps
CPU time 7.61 seconds
Started Jul 09 06:35:07 PM PDT 24
Finished Jul 09 06:35:16 PM PDT 24
Peak memory 201708 kb
Host smart-2150a4d5-16ac-4ba5-a05b-74972f4cb2a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021735521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_smoke.1021735521
Directory /workspace/23.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/23.adc_ctrl_stress_all_with_rand_reset.1325497462
Short name T305
Test name
Test status
Simulation time 18135093980 ps
CPU time 14.59 seconds
Started Jul 09 06:35:21 PM PDT 24
Finished Jul 09 06:35:37 PM PDT 24
Peak memory 202640 kb
Host smart-8893a85f-cabe-4773-8db2-7e1356f95473
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325497462 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 23.adc_ctrl_stress_all_with_rand_reset.1325497462
Directory /workspace/23.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_alert_test.81250200
Short name T420
Test name
Test status
Simulation time 388695358 ps
CPU time 1.54 seconds
Started Jul 09 06:36:10 PM PDT 24
Finished Jul 09 06:36:12 PM PDT 24
Peak memory 201652 kb
Host smart-30f54ad7-1e3f-410e-b331-785dadda3ef0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81250200 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_alert_test.81250200
Directory /workspace/24.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_both.3819798731
Short name T729
Test name
Test status
Simulation time 198606787324 ps
CPU time 483.37 seconds
Started Jul 09 06:35:28 PM PDT 24
Finished Jul 09 06:43:33 PM PDT 24
Peak memory 201892 kb
Host smart-621ed229-882b-4ee3-b1dd-bac9ff65a316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819798731 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_both.3819798731
Directory /workspace/24.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt.2089079715
Short name T316
Test name
Test status
Simulation time 486522847485 ps
CPU time 1083.17 seconds
Started Jul 09 06:35:23 PM PDT 24
Finished Jul 09 06:53:27 PM PDT 24
Peak memory 201944 kb
Host smart-88499f53-bb13-48e2-9d6d-b022766a1af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089079715 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interrupt.2089079715
Directory /workspace/24.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_interrupt_fixed.4039486151
Short name T800
Test name
Test status
Simulation time 487829681217 ps
CPU time 1132.16 seconds
Started Jul 09 06:35:24 PM PDT 24
Finished Jul 09 06:54:18 PM PDT 24
Peak memory 201816 kb
Host smart-c8f681bb-4c16-426c-b0eb-119058178df5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039486151 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_interru
pt_fixed.4039486151
Directory /workspace/24.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled.2314899249
Short name T675
Test name
Test status
Simulation time 165453807380 ps
CPU time 217.64 seconds
Started Jul 09 06:35:22 PM PDT 24
Finished Jul 09 06:39:01 PM PDT 24
Peak memory 201944 kb
Host smart-6b4f75dc-25bf-45a8-82bd-a43907fa439f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314899249 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled.2314899249
Directory /workspace/24.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_polled_fixed.2958080706
Short name T446
Test name
Test status
Simulation time 161944687552 ps
CPU time 365.83 seconds
Started Jul 09 06:35:25 PM PDT 24
Finished Jul 09 06:41:32 PM PDT 24
Peak memory 201956 kb
Host smart-5a1437ce-7c34-4d9a-b166-b53299112011
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958080706 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_filters_polled_fix
ed.2958080706
Directory /workspace/24.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_filters_wakeup_fixed.534983210
Short name T701
Test name
Test status
Simulation time 628169818264 ps
CPU time 143.64 seconds
Started Jul 09 06:35:24 PM PDT 24
Finished Jul 09 06:37:50 PM PDT 24
Peak memory 201732 kb
Host smart-3ea3da47-9289-4c46-b874-16db1b14484a
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534983210 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.
adc_ctrl_filters_wakeup_fixed.534983210
Directory /workspace/24.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/24.adc_ctrl_fsm_reset.1004488264
Short name T357
Test name
Test status
Simulation time 102184547818 ps
CPU time 337.11 seconds
Started Jul 09 06:35:29 PM PDT 24
Finished Jul 09 06:41:07 PM PDT 24
Peak memory 202212 kb
Host smart-2c702e45-ea5d-4727-9110-041b6cb61e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004488264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_fsm_reset.1004488264
Directory /workspace/24.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/24.adc_ctrl_lowpower_counter.3175986825
Short name T480
Test name
Test status
Simulation time 22310014687 ps
CPU time 24.4 seconds
Started Jul 09 06:35:29 PM PDT 24
Finished Jul 09 06:35:54 PM PDT 24
Peak memory 201656 kb
Host smart-84bf2cf3-1741-45bd-8b79-dd83e5b2ffc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175986825 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_lowpower_counter.3175986825
Directory /workspace/24.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_poweron_counter.2982640559
Short name T750
Test name
Test status
Simulation time 5224737196 ps
CPU time 13.02 seconds
Started Jul 09 06:35:29 PM PDT 24
Finished Jul 09 06:35:44 PM PDT 24
Peak memory 201728 kb
Host smart-766d7781-84b2-49db-b74d-524eb304aa02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982640559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_poweron_counter.2982640559
Directory /workspace/24.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/24.adc_ctrl_smoke.2535933155
Short name T107
Test name
Test status
Simulation time 6110142514 ps
CPU time 5.2 seconds
Started Jul 09 06:35:19 PM PDT 24
Finished Jul 09 06:35:27 PM PDT 24
Peak memory 201676 kb
Host smart-b99ee04f-8d75-4fdc-9a7d-ea4886ee5d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535933155 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_smoke.2535933155
Directory /workspace/24.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all.1506500727
Short name T33
Test name
Test status
Simulation time 311483801717 ps
CPU time 414.12 seconds
Started Jul 09 06:35:28 PM PDT 24
Finished Jul 09 06:42:24 PM PDT 24
Peak memory 202212 kb
Host smart-5e882682-476c-4e6e-83e1-27ec67bba54a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506500727 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all
.1506500727
Directory /workspace/24.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.adc_ctrl_stress_all_with_rand_reset.4004757121
Short name T329
Test name
Test status
Simulation time 615622963487 ps
CPU time 182.6 seconds
Started Jul 09 06:35:29 PM PDT 24
Finished Jul 09 06:38:33 PM PDT 24
Peak memory 210252 kb
Host smart-0d0a8795-a87b-41b4-b830-8c010ea756eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004757121 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 24.adc_ctrl_stress_all_with_rand_reset.4004757121
Directory /workspace/24.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_alert_test.1677809763
Short name T499
Test name
Test status
Simulation time 429909789 ps
CPU time 1.65 seconds
Started Jul 09 06:35:42 PM PDT 24
Finished Jul 09 06:35:45 PM PDT 24
Peak memory 201604 kb
Host smart-ed1a6c8d-8083-4e44-bbae-78c567028835
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677809763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_alert_test.1677809763
Directory /workspace/25.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.adc_ctrl_clock_gating.2312305055
Short name T155
Test name
Test status
Simulation time 365474108828 ps
CPU time 115.19 seconds
Started Jul 09 06:35:36 PM PDT 24
Finished Jul 09 06:37:32 PM PDT 24
Peak memory 201864 kb
Host smart-65b3374d-f2d0-4628-8b91-0219044ac3b9
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312305055 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_clock_gat
ing.2312305055
Directory /workspace/25.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_both.3877217507
Short name T223
Test name
Test status
Simulation time 385134269596 ps
CPU time 708.97 seconds
Started Jul 09 06:35:36 PM PDT 24
Finished Jul 09 06:47:26 PM PDT 24
Peak memory 201760 kb
Host smart-3fc8d2c0-3ce7-45c1-bf5b-0b11326b77c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877217507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_both.3877217507
Directory /workspace/25.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt.565606308
Short name T187
Test name
Test status
Simulation time 325920091851 ps
CPU time 391.14 seconds
Started Jul 09 06:35:32 PM PDT 24
Finished Jul 09 06:42:05 PM PDT 24
Peak memory 201872 kb
Host smart-433854f4-c115-4f5d-890e-dcb8bf7a5d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565606308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interrupt.565606308
Directory /workspace/25.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_interrupt_fixed.2861607492
Short name T608
Test name
Test status
Simulation time 162751820572 ps
CPU time 100.49 seconds
Started Jul 09 06:35:34 PM PDT 24
Finished Jul 09 06:37:15 PM PDT 24
Peak memory 201924 kb
Host smart-535ffdf7-5181-46ea-8ad3-f666e734e098
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861607492 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_interru
pt_fixed.2861607492
Directory /workspace/25.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled.4218302576
Short name T337
Test name
Test status
Simulation time 492772564966 ps
CPU time 1043 seconds
Started Jul 09 06:35:34 PM PDT 24
Finished Jul 09 06:52:59 PM PDT 24
Peak memory 201928 kb
Host smart-de8a6839-5ca2-471a-826a-43ec6cda7da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218302576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled.4218302576
Directory /workspace/25.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_polled_fixed.4142041566
Short name T524
Test name
Test status
Simulation time 324503118817 ps
CPU time 558.18 seconds
Started Jul 09 06:35:32 PM PDT 24
Finished Jul 09 06:44:52 PM PDT 24
Peak memory 201948 kb
Host smart-b396dec3-2241-4c25-8d50-4848369a9a5b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142041566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters_polled_fix
ed.4142041566
Directory /workspace/25.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup.3639007523
Short name T255
Test name
Test status
Simulation time 195584600592 ps
CPU time 97.69 seconds
Started Jul 09 06:35:34 PM PDT 24
Finished Jul 09 06:37:12 PM PDT 24
Peak memory 201992 kb
Host smart-496961e9-756f-4a99-98e7-ace489c82eed
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639007523 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_filters
_wakeup.3639007523
Directory /workspace/25.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/25.adc_ctrl_filters_wakeup_fixed.1839969255
Short name T403
Test name
Test status
Simulation time 409730649050 ps
CPU time 969.59 seconds
Started Jul 09 06:35:31 PM PDT 24
Finished Jul 09 06:51:42 PM PDT 24
Peak memory 201884 kb
Host smart-0c4385a8-9b4f-4dd6-9cd8-e870383074a9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839969255 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25
.adc_ctrl_filters_wakeup_fixed.1839969255
Directory /workspace/25.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/25.adc_ctrl_fsm_reset.4237525595
Short name T414
Test name
Test status
Simulation time 63448270075 ps
CPU time 318.45 seconds
Started Jul 09 06:35:38 PM PDT 24
Finished Jul 09 06:40:57 PM PDT 24
Peak memory 202228 kb
Host smart-6bbd133c-4ae7-4238-911c-cb66f34eed27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237525595 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_fsm_reset.4237525595
Directory /workspace/25.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/25.adc_ctrl_lowpower_counter.2581855826
Short name T560
Test name
Test status
Simulation time 33972703856 ps
CPU time 24.09 seconds
Started Jul 09 06:35:38 PM PDT 24
Finished Jul 09 06:36:03 PM PDT 24
Peak memory 201680 kb
Host smart-7a5879a4-0bcc-4f71-89b9-21e6810cfc21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581855826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_lowpower_counter.2581855826
Directory /workspace/25.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_poweron_counter.2377035472
Short name T600
Test name
Test status
Simulation time 5491697693 ps
CPU time 3.79 seconds
Started Jul 09 06:35:35 PM PDT 24
Finished Jul 09 06:35:40 PM PDT 24
Peak memory 201724 kb
Host smart-92ad4f0c-3c24-45e9-9a40-265afb048579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377035472 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_poweron_counter.2377035472
Directory /workspace/25.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/25.adc_ctrl_smoke.788289166
Short name T412
Test name
Test status
Simulation time 5886824931 ps
CPU time 13.97 seconds
Started Jul 09 06:35:28 PM PDT 24
Finished Jul 09 06:35:43 PM PDT 24
Peak memory 201736 kb
Host smart-3db5b240-561e-4feb-8442-dc91156f6a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788289166 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_smoke.788289166
Directory /workspace/25.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all.961496723
Short name T678
Test name
Test status
Simulation time 511899643680 ps
CPU time 555.52 seconds
Started Jul 09 06:35:39 PM PDT 24
Finished Jul 09 06:44:56 PM PDT 24
Peak memory 201916 kb
Host smart-897be980-9272-4a32-acf5-22fc545526ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961496723 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all.
961496723
Directory /workspace/25.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.adc_ctrl_stress_all_with_rand_reset.2632123429
Short name T87
Test name
Test status
Simulation time 184523275429 ps
CPU time 362.85 seconds
Started Jul 09 06:35:38 PM PDT 24
Finished Jul 09 06:41:42 PM PDT 24
Peak memory 218272 kb
Host smart-01ec787a-3bdb-4521-ab45-2171627306d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632123429 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 25.adc_ctrl_stress_all_with_rand_reset.2632123429
Directory /workspace/25.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_alert_test.1176871980
Short name T440
Test name
Test status
Simulation time 363501474 ps
CPU time 1.53 seconds
Started Jul 09 06:35:55 PM PDT 24
Finished Jul 09 06:35:58 PM PDT 24
Peak memory 201676 kb
Host smart-20362fa4-558a-4403-8189-376dc833ec78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176871980 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_alert_test.1176871980
Directory /workspace/26.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.adc_ctrl_clock_gating.3702970052
Short name T9
Test name
Test status
Simulation time 162754678237 ps
CPU time 2.93 seconds
Started Jul 09 06:35:47 PM PDT 24
Finished Jul 09 06:35:51 PM PDT 24
Peak memory 201952 kb
Host smart-ae954fa3-e056-44a7-b63e-5debcad3dfe8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702970052 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_clock_gat
ing.3702970052
Directory /workspace/26.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt.2407577765
Short name T722
Test name
Test status
Simulation time 165385154921 ps
CPU time 352.96 seconds
Started Jul 09 06:35:41 PM PDT 24
Finished Jul 09 06:41:35 PM PDT 24
Peak memory 201936 kb
Host smart-f8e3cf4e-eb39-4dbc-9cc4-bf7878968ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407577765 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interrupt.2407577765
Directory /workspace/26.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_interrupt_fixed.1758978132
Short name T484
Test name
Test status
Simulation time 322047579341 ps
CPU time 776.63 seconds
Started Jul 09 06:35:42 PM PDT 24
Finished Jul 09 06:48:40 PM PDT 24
Peak memory 201952 kb
Host smart-28182d32-61dd-496c-860a-133f253b95ad
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758978132 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_interru
pt_fixed.1758978132
Directory /workspace/26.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled.3491124489
Short name T186
Test name
Test status
Simulation time 322380791390 ps
CPU time 106.93 seconds
Started Jul 09 06:35:41 PM PDT 24
Finished Jul 09 06:37:29 PM PDT 24
Peak memory 201868 kb
Host smart-a6454ab4-8068-417a-b03d-d6b24fc43796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491124489 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled.3491124489
Directory /workspace/26.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_polled_fixed.2437773972
Short name T656
Test name
Test status
Simulation time 502178724045 ps
CPU time 1081.07 seconds
Started Jul 09 06:35:42 PM PDT 24
Finished Jul 09 06:53:44 PM PDT 24
Peak memory 201904 kb
Host smart-ee1e8f93-ca82-404f-ae45-92ae4d5b9040
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437773972 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters_polled_fix
ed.2437773972
Directory /workspace/26.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup.3136115395
Short name T213
Test name
Test status
Simulation time 206845629527 ps
CPU time 205.36 seconds
Started Jul 09 06:35:46 PM PDT 24
Finished Jul 09 06:39:13 PM PDT 24
Peak memory 201756 kb
Host smart-b1767c72-25b6-423f-99b9-78ec68c3a911
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136115395 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_filters
_wakeup.3136115395
Directory /workspace/26.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/26.adc_ctrl_filters_wakeup_fixed.3338930180
Short name T492
Test name
Test status
Simulation time 423081540741 ps
CPU time 149.75 seconds
Started Jul 09 06:35:46 PM PDT 24
Finished Jul 09 06:38:17 PM PDT 24
Peak memory 201908 kb
Host smart-2fad255e-a235-42c9-9eee-c8699e0ef218
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338930180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26
.adc_ctrl_filters_wakeup_fixed.3338930180
Directory /workspace/26.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/26.adc_ctrl_fsm_reset.2068090311
Short name T540
Test name
Test status
Simulation time 59646165532 ps
CPU time 235.07 seconds
Started Jul 09 06:35:52 PM PDT 24
Finished Jul 09 06:39:49 PM PDT 24
Peak memory 202064 kb
Host smart-684c01ee-a5be-4442-8eae-5a40c7af940b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068090311 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_fsm_reset.2068090311
Directory /workspace/26.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/26.adc_ctrl_lowpower_counter.1457721923
Short name T497
Test name
Test status
Simulation time 27828635004 ps
CPU time 31.11 seconds
Started Jul 09 06:35:52 PM PDT 24
Finished Jul 09 06:36:25 PM PDT 24
Peak memory 201740 kb
Host smart-4452f1c2-1121-41f0-a3b2-0cba16d6902a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457721923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_lowpower_counter.1457721923
Directory /workspace/26.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_poweron_counter.4106681277
Short name T425
Test name
Test status
Simulation time 2852688708 ps
CPU time 2.38 seconds
Started Jul 09 06:35:45 PM PDT 24
Finished Jul 09 06:35:48 PM PDT 24
Peak memory 201672 kb
Host smart-f42e8b41-b423-44f8-a881-c2cf4ec80667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106681277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_poweron_counter.4106681277
Directory /workspace/26.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/26.adc_ctrl_smoke.2503956576
Short name T476
Test name
Test status
Simulation time 5775740831 ps
CPU time 13.05 seconds
Started Jul 09 06:35:42 PM PDT 24
Finished Jul 09 06:35:56 PM PDT 24
Peak memory 201708 kb
Host smart-edf08d6e-a6bb-4a4b-b619-bd472409623b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503956576 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_smoke.2503956576
Directory /workspace/26.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all.2208113520
Short name T215
Test name
Test status
Simulation time 507179341037 ps
CPU time 282.22 seconds
Started Jul 09 06:35:51 PM PDT 24
Finished Jul 09 06:40:34 PM PDT 24
Peak memory 201912 kb
Host smart-6f25c1bc-1119-44b2-8441-c04706cdfa97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208113520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all
.2208113520
Directory /workspace/26.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.adc_ctrl_stress_all_with_rand_reset.3930667524
Short name T13
Test name
Test status
Simulation time 19181120750 ps
CPU time 58.13 seconds
Started Jul 09 06:35:52 PM PDT 24
Finished Jul 09 06:36:51 PM PDT 24
Peak memory 210564 kb
Host smart-5c6b1ca2-4bea-4979-bb28-fe2efbd9e4f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930667524 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 26.adc_ctrl_stress_all_with_rand_reset.3930667524
Directory /workspace/26.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_alert_test.2547669730
Short name T416
Test name
Test status
Simulation time 489190848 ps
CPU time 0.72 seconds
Started Jul 09 06:36:01 PM PDT 24
Finished Jul 09 06:36:03 PM PDT 24
Peak memory 201672 kb
Host smart-c3db95ed-5478-4dd1-be17-6a14825dee88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547669730 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_alert_test.2547669730
Directory /workspace/27.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.adc_ctrl_clock_gating.1662040115
Short name T1
Test name
Test status
Simulation time 164667925471 ps
CPU time 345.32 seconds
Started Jul 09 06:36:02 PM PDT 24
Finished Jul 09 06:41:49 PM PDT 24
Peak memory 201796 kb
Host smart-b13b92a6-15f9-4eb0-aa35-f89e616fe567
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662040115 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_clock_gat
ing.1662040115
Directory /workspace/27.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_both.3187365442
Short name T160
Test name
Test status
Simulation time 347289393509 ps
CPU time 200.04 seconds
Started Jul 09 06:36:02 PM PDT 24
Finished Jul 09 06:39:23 PM PDT 24
Peak memory 201908 kb
Host smart-c3a6073e-20c8-449b-be73-9b62093a25a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3187365442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_both.3187365442
Directory /workspace/27.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt.2952390000
Short name T216
Test name
Test status
Simulation time 485697396521 ps
CPU time 172.45 seconds
Started Jul 09 06:35:54 PM PDT 24
Finished Jul 09 06:38:48 PM PDT 24
Peak memory 201964 kb
Host smart-7a56b5dd-40a0-4438-8d2a-6e9484ff36b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952390000 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interrupt.2952390000
Directory /workspace/27.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_interrupt_fixed.1654620198
Short name T692
Test name
Test status
Simulation time 159799661027 ps
CPU time 374.49 seconds
Started Jul 09 06:36:00 PM PDT 24
Finished Jul 09 06:42:15 PM PDT 24
Peak memory 201900 kb
Host smart-58c6307e-ed17-4dde-a1bf-af9d72428c7b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654620198 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_interru
pt_fixed.1654620198
Directory /workspace/27.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled.3800480484
Short name T569
Test name
Test status
Simulation time 324361061338 ps
CPU time 90.55 seconds
Started Jul 09 06:35:56 PM PDT 24
Finished Jul 09 06:37:28 PM PDT 24
Peak memory 201940 kb
Host smart-bcac4a34-2e12-46bc-8779-b35bb5dd9ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800480484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled.3800480484
Directory /workspace/27.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_polled_fixed.3357053131
Short name T550
Test name
Test status
Simulation time 496069374320 ps
CPU time 221.93 seconds
Started Jul 09 06:35:58 PM PDT 24
Finished Jul 09 06:39:41 PM PDT 24
Peak memory 201904 kb
Host smart-2d20e567-d4b8-4644-91e4-446c5266984e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357053131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters_polled_fix
ed.3357053131
Directory /workspace/27.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup.2190793838
Short name T227
Test name
Test status
Simulation time 376237515625 ps
CPU time 634.87 seconds
Started Jul 09 06:35:55 PM PDT 24
Finished Jul 09 06:46:31 PM PDT 24
Peak memory 201964 kb
Host smart-5a4b2da4-82e6-4fc8-b3bc-06ba17fbea57
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190793838 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_filters
_wakeup.2190793838
Directory /workspace/27.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/27.adc_ctrl_filters_wakeup_fixed.2624148743
Short name T629
Test name
Test status
Simulation time 615624611596 ps
CPU time 1285.82 seconds
Started Jul 09 06:36:03 PM PDT 24
Finished Jul 09 06:57:30 PM PDT 24
Peak memory 201860 kb
Host smart-86b3fc79-6b39-495f-bf33-bcd0e36f4dcb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624148743 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27
.adc_ctrl_filters_wakeup_fixed.2624148743
Directory /workspace/27.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/27.adc_ctrl_fsm_reset.1552750712
Short name T355
Test name
Test status
Simulation time 81024159244 ps
CPU time 279.39 seconds
Started Jul 09 06:36:03 PM PDT 24
Finished Jul 09 06:40:44 PM PDT 24
Peak memory 202308 kb
Host smart-92207bba-5077-49c6-9054-c11f4938d1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552750712 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_fsm_reset.1552750712
Directory /workspace/27.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/27.adc_ctrl_lowpower_counter.398905818
Short name T775
Test name
Test status
Simulation time 22347138095 ps
CPU time 26.49 seconds
Started Jul 09 06:36:03 PM PDT 24
Finished Jul 09 06:36:31 PM PDT 24
Peak memory 201896 kb
Host smart-02ee8af3-339d-45fe-a27e-983d9954ac57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398905818 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_lowpower_counter.398905818
Directory /workspace/27.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_poweron_counter.2743813105
Short name T570
Test name
Test status
Simulation time 4520593958 ps
CPU time 10.95 seconds
Started Jul 09 06:36:03 PM PDT 24
Finished Jul 09 06:36:15 PM PDT 24
Peak memory 201728 kb
Host smart-df3c0820-2468-4c23-abe5-271b5c96b93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743813105 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_poweron_counter.2743813105
Directory /workspace/27.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/27.adc_ctrl_smoke.1028985961
Short name T684
Test name
Test status
Simulation time 5835939880 ps
CPU time 7.98 seconds
Started Jul 09 06:35:55 PM PDT 24
Finished Jul 09 06:36:04 PM PDT 24
Peak memory 201708 kb
Host smart-a6d3969d-f03e-4799-ae2c-0da5ef260dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028985961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_smoke.1028985961
Directory /workspace/27.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all.2523914325
Short name T380
Test name
Test status
Simulation time 11076945975 ps
CPU time 25.8 seconds
Started Jul 09 06:36:02 PM PDT 24
Finished Jul 09 06:36:29 PM PDT 24
Peak memory 201708 kb
Host smart-cb4ee876-f034-41b8-95cc-e4baa11e3944
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523914325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all
.2523914325
Directory /workspace/27.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.adc_ctrl_stress_all_with_rand_reset.940271673
Short name T14
Test name
Test status
Simulation time 97032871345 ps
CPU time 153.48 seconds
Started Jul 09 06:36:07 PM PDT 24
Finished Jul 09 06:38:42 PM PDT 24
Peak memory 210632 kb
Host smart-6d9cef01-3179-4bad-8e51-dc8184c1a7be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940271673 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 27.adc_ctrl_stress_all_with_rand_reset.940271673
Directory /workspace/27.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_alert_test.4068758806
Short name T602
Test name
Test status
Simulation time 284359835 ps
CPU time 0.95 seconds
Started Jul 09 06:36:18 PM PDT 24
Finished Jul 09 06:36:21 PM PDT 24
Peak memory 201620 kb
Host smart-cd6df000-ad05-4ec3-9f6b-e3ac172c1e43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4068758806 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_alert_test.4068758806
Directory /workspace/28.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_both.1210301700
Short name T663
Test name
Test status
Simulation time 185225535169 ps
CPU time 106.89 seconds
Started Jul 09 06:36:12 PM PDT 24
Finished Jul 09 06:38:00 PM PDT 24
Peak memory 201836 kb
Host smart-ab86b6fa-64a7-4155-b26a-d1e66db7ed5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210301700 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_both.1210301700
Directory /workspace/28.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt.1031708365
Short name T46
Test name
Test status
Simulation time 322635876297 ps
CPU time 107.43 seconds
Started Jul 09 06:36:07 PM PDT 24
Finished Jul 09 06:37:56 PM PDT 24
Peak memory 201928 kb
Host smart-9ce992c1-5e6e-44f3-9ec9-266a6c933ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031708365 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interrupt.1031708365
Directory /workspace/28.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_interrupt_fixed.3072625215
Short name T616
Test name
Test status
Simulation time 323767979004 ps
CPU time 756.32 seconds
Started Jul 09 06:36:08 PM PDT 24
Finished Jul 09 06:48:46 PM PDT 24
Peak memory 201872 kb
Host smart-163a3cbb-a7ed-4493-b334-9bb5aaa70688
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072625215 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_interru
pt_fixed.3072625215
Directory /workspace/28.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled.514887568
Short name T312
Test name
Test status
Simulation time 320667014057 ps
CPU time 702.45 seconds
Started Jul 09 06:36:03 PM PDT 24
Finished Jul 09 06:47:46 PM PDT 24
Peak memory 201948 kb
Host smart-ceac3d59-3db7-4157-9d51-b98bf4d0a317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=514887568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled.514887568
Directory /workspace/28.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_polled_fixed.3443140923
Short name T2
Test name
Test status
Simulation time 492641178399 ps
CPU time 104.51 seconds
Started Jul 09 06:36:02 PM PDT 24
Finished Jul 09 06:37:48 PM PDT 24
Peak memory 201828 kb
Host smart-6b7be79a-b99d-43c5-9f7d-a64fc2e8e09f
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443140923 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_filters_polled_fix
ed.3443140923
Directory /workspace/28.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_filters_wakeup_fixed.4250674876
Short name T481
Test name
Test status
Simulation time 401078210898 ps
CPU time 299.31 seconds
Started Jul 09 06:36:09 PM PDT 24
Finished Jul 09 06:41:09 PM PDT 24
Peak memory 201960 kb
Host smart-54bcce23-c5c7-4904-a485-52c854233061
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250674876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28
.adc_ctrl_filters_wakeup_fixed.4250674876
Directory /workspace/28.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/28.adc_ctrl_fsm_reset.3259486546
Short name T641
Test name
Test status
Simulation time 102046114561 ps
CPU time 510.48 seconds
Started Jul 09 06:36:11 PM PDT 24
Finished Jul 09 06:44:43 PM PDT 24
Peak memory 202232 kb
Host smart-7e0e0f27-235e-4ad6-87f1-2800466b012f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259486546 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_fsm_reset.3259486546
Directory /workspace/28.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/28.adc_ctrl_lowpower_counter.3836772144
Short name T405
Test name
Test status
Simulation time 40667386507 ps
CPU time 46.9 seconds
Started Jul 09 06:36:12 PM PDT 24
Finished Jul 09 06:37:00 PM PDT 24
Peak memory 201736 kb
Host smart-020c65f3-d8fb-4b9a-ae15-f4d9c43e075a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836772144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_lowpower_counter.3836772144
Directory /workspace/28.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_poweron_counter.3730936194
Short name T574
Test name
Test status
Simulation time 4954928135 ps
CPU time 7.94 seconds
Started Jul 09 06:36:11 PM PDT 24
Finished Jul 09 06:36:20 PM PDT 24
Peak memory 201708 kb
Host smart-f6f6b553-5f29-408f-a0c1-edd063f10b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730936194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_poweron_counter.3730936194
Directory /workspace/28.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/28.adc_ctrl_smoke.1296025766
Short name T723
Test name
Test status
Simulation time 5987711788 ps
CPU time 7.23 seconds
Started Jul 09 06:36:07 PM PDT 24
Finished Jul 09 06:36:16 PM PDT 24
Peak memory 201724 kb
Host smart-9c293410-dc80-495d-a2d1-ad40eafb24a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296025766 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_smoke.1296025766
Directory /workspace/28.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all.2217250142
Short name T427
Test name
Test status
Simulation time 207854175664 ps
CPU time 475.57 seconds
Started Jul 09 06:36:22 PM PDT 24
Finished Jul 09 06:44:19 PM PDT 24
Peak memory 201980 kb
Host smart-5a4eb193-da4c-4d6e-99b7-2ee742d67bdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217250142 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all
.2217250142
Directory /workspace/28.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.adc_ctrl_stress_all_with_rand_reset.1769898180
Short name T694
Test name
Test status
Simulation time 32031046920 ps
CPU time 61.55 seconds
Started Jul 09 06:36:17 PM PDT 24
Finished Jul 09 06:37:20 PM PDT 24
Peak memory 210232 kb
Host smart-c3f2b00c-8516-4c36-a450-6f89cea328d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769898180 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 28.adc_ctrl_stress_all_with_rand_reset.1769898180
Directory /workspace/28.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_alert_test.4042770962
Short name T75
Test name
Test status
Simulation time 529563227 ps
CPU time 1.72 seconds
Started Jul 09 06:36:27 PM PDT 24
Finished Jul 09 06:36:30 PM PDT 24
Peak memory 201620 kb
Host smart-910c6963-80f4-415c-8da9-fa221ad90707
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042770962 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_alert_test.4042770962
Directory /workspace/29.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.adc_ctrl_clock_gating.1351724615
Short name T299
Test name
Test status
Simulation time 353214677686 ps
CPU time 183.48 seconds
Started Jul 09 06:36:22 PM PDT 24
Finished Jul 09 06:39:27 PM PDT 24
Peak memory 201920 kb
Host smart-8599f2a9-1094-448d-aefc-43add0a960cb
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351724615 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_clock_gat
ing.1351724615
Directory /workspace/29.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_both.3313882109
Short name T746
Test name
Test status
Simulation time 168889263251 ps
CPU time 118.47 seconds
Started Jul 09 06:36:22 PM PDT 24
Finished Jul 09 06:38:21 PM PDT 24
Peak memory 201948 kb
Host smart-41a34a7f-ff4f-444e-a284-5ffeda1e54de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313882109 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_both.3313882109
Directory /workspace/29.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt.3745181157
Short name T576
Test name
Test status
Simulation time 164584251993 ps
CPU time 406.76 seconds
Started Jul 09 06:36:17 PM PDT 24
Finished Jul 09 06:43:04 PM PDT 24
Peak memory 201968 kb
Host smart-dcb934aa-e1f9-491a-b16d-a6cec433661d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745181157 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interrupt.3745181157
Directory /workspace/29.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_interrupt_fixed.2846594392
Short name T781
Test name
Test status
Simulation time 169629680428 ps
CPU time 188.12 seconds
Started Jul 09 06:36:16 PM PDT 24
Finished Jul 09 06:39:25 PM PDT 24
Peak memory 201836 kb
Host smart-d548fc2d-eb74-4c7e-a758-c9875293c98b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846594392 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_interru
pt_fixed.2846594392
Directory /workspace/29.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled.3638667996
Short name T504
Test name
Test status
Simulation time 332803822963 ps
CPU time 757.47 seconds
Started Jul 09 06:36:16 PM PDT 24
Finished Jul 09 06:48:54 PM PDT 24
Peak memory 201944 kb
Host smart-c6644602-f671-4513-abf6-c0658edd9d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638667996 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled.3638667996
Directory /workspace/29.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_polled_fixed.2735394158
Short name T590
Test name
Test status
Simulation time 162211384938 ps
CPU time 359.87 seconds
Started Jul 09 06:36:15 PM PDT 24
Finished Jul 09 06:42:16 PM PDT 24
Peak memory 202080 kb
Host smart-47d0a4e0-1b07-48b7-b5cf-42755be3c247
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735394158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_filters_polled_fix
ed.2735394158
Directory /workspace/29.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_filters_wakeup_fixed.789088782
Short name T651
Test name
Test status
Simulation time 387025362290 ps
CPU time 440.77 seconds
Started Jul 09 06:36:16 PM PDT 24
Finished Jul 09 06:43:37 PM PDT 24
Peak memory 201904 kb
Host smart-d8335633-3b73-43eb-90f2-710572ed3d6d
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789088782 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.
adc_ctrl_filters_wakeup_fixed.789088782
Directory /workspace/29.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/29.adc_ctrl_fsm_reset.448115224
Short name T495
Test name
Test status
Simulation time 81412086668 ps
CPU time 306.83 seconds
Started Jul 09 06:36:26 PM PDT 24
Finished Jul 09 06:41:34 PM PDT 24
Peak memory 202224 kb
Host smart-dcaa3d3c-470b-4473-8633-0225701e129c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448115224 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_fsm_reset.448115224
Directory /workspace/29.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/29.adc_ctrl_lowpower_counter.995293188
Short name T417
Test name
Test status
Simulation time 41947867901 ps
CPU time 23.12 seconds
Started Jul 09 06:36:22 PM PDT 24
Finished Jul 09 06:36:46 PM PDT 24
Peak memory 201688 kb
Host smart-9b3a0672-92fc-4b61-b33f-395a252e60ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995293188 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_lowpower_counter.995293188
Directory /workspace/29.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_poweron_counter.2020665332
Short name T548
Test name
Test status
Simulation time 4951516491 ps
CPU time 12.23 seconds
Started Jul 09 06:36:22 PM PDT 24
Finished Jul 09 06:36:35 PM PDT 24
Peak memory 201656 kb
Host smart-4f431402-0bcb-4723-99bf-2b11369dd67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020665332 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_poweron_counter.2020665332
Directory /workspace/29.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/29.adc_ctrl_smoke.390775178
Short name T366
Test name
Test status
Simulation time 5547594173 ps
CPU time 13.35 seconds
Started Jul 09 06:36:19 PM PDT 24
Finished Jul 09 06:36:34 PM PDT 24
Peak memory 201700 kb
Host smart-8ad84c60-f060-4c37-963f-5db4c55254a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390775178 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_smoke.390775178
Directory /workspace/29.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all.3512698873
Short name T328
Test name
Test status
Simulation time 298343609546 ps
CPU time 703.45 seconds
Started Jul 09 06:36:26 PM PDT 24
Finished Jul 09 06:48:11 PM PDT 24
Peak memory 210420 kb
Host smart-35b533a1-673b-46b8-9271-ba3f92177f2d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512698873 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all
.3512698873
Directory /workspace/29.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.adc_ctrl_stress_all_with_rand_reset.4055716482
Short name T37
Test name
Test status
Simulation time 217603707764 ps
CPU time 162.75 seconds
Started Jul 09 06:36:26 PM PDT 24
Finished Jul 09 06:39:10 PM PDT 24
Peak memory 217936 kb
Host smart-2e2f8358-cea5-49fd-b45a-fdfe577396cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055716482 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 29.adc_ctrl_stress_all_with_rand_reset.4055716482
Directory /workspace/29.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_alert_test.203197692
Short name T473
Test name
Test status
Simulation time 537426069 ps
CPU time 0.71 seconds
Started Jul 09 06:33:02 PM PDT 24
Finished Jul 09 06:33:17 PM PDT 24
Peak memory 201672 kb
Host smart-54542ca6-a73f-4c84-aa9f-cf4719f68f1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203197692 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_alert_test.203197692
Directory /workspace/3.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.adc_ctrl_clock_gating.122807756
Short name T284
Test name
Test status
Simulation time 540501348026 ps
CPU time 456.54 seconds
Started Jul 09 06:32:57 PM PDT 24
Finished Jul 09 06:40:51 PM PDT 24
Peak memory 201900 kb
Host smart-495114b8-9066-455c-98e2-7b42d5edfb1f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=122807756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_clock_gatin
g.122807756
Directory /workspace/3.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt.114791559
Short name T170
Test name
Test status
Simulation time 319795825493 ps
CPU time 605.16 seconds
Started Jul 09 06:32:59 PM PDT 24
Finished Jul 09 06:43:20 PM PDT 24
Peak memory 201912 kb
Host smart-4f6d1fc2-baeb-45d8-8ef1-942f0e6fbfe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114791559 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrupt.114791559
Directory /workspace/3.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_interrupt_fixed.3109948189
Short name T378
Test name
Test status
Simulation time 499686189328 ps
CPU time 1145.53 seconds
Started Jul 09 06:32:57 PM PDT 24
Finished Jul 09 06:52:19 PM PDT 24
Peak memory 201924 kb
Host smart-4ed1b865-5529-43f4-aa7a-95820911cafe
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109948189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_interrup
t_fixed.3109948189
Directory /workspace/3.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled.3888374747
Short name T472
Test name
Test status
Simulation time 334276055959 ps
CPU time 751.63 seconds
Started Jul 09 06:32:57 PM PDT 24
Finished Jul 09 06:45:46 PM PDT 24
Peak memory 202024 kb
Host smart-e735d11a-fd5b-4fd9-b189-d0bc6b771b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888374747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled.3888374747
Directory /workspace/3.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_polled_fixed.755285914
Short name T710
Test name
Test status
Simulation time 325212495751 ps
CPU time 94.02 seconds
Started Jul 09 06:32:57 PM PDT 24
Finished Jul 09 06:34:47 PM PDT 24
Peak memory 201880 kb
Host smart-7ac6cf6c-4f83-4d4d-990d-a16734bb8001
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=755285914 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_polled_fixed
.755285914
Directory /workspace/3.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup.692549886
Short name T47
Test name
Test status
Simulation time 185423829371 ps
CPU time 399.02 seconds
Started Jul 09 06:32:57 PM PDT 24
Finished Jul 09 06:39:53 PM PDT 24
Peak memory 202096 kb
Host smart-5ddf1614-2073-4346-b0cf-9d164a609830
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692549886 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_filters_w
akeup.692549886
Directory /workspace/3.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/3.adc_ctrl_filters_wakeup_fixed.3676342829
Short name T771
Test name
Test status
Simulation time 622846675497 ps
CPU time 331.07 seconds
Started Jul 09 06:32:58 PM PDT 24
Finished Jul 09 06:38:45 PM PDT 24
Peak memory 201940 kb
Host smart-7cca7765-5490-4ceb-87fe-3efa0462c856
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676342829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.
adc_ctrl_filters_wakeup_fixed.3676342829
Directory /workspace/3.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/3.adc_ctrl_fsm_reset.3146709779
Short name T566
Test name
Test status
Simulation time 96619712537 ps
CPU time 334.26 seconds
Started Jul 09 06:33:03 PM PDT 24
Finished Jul 09 06:38:52 PM PDT 24
Peak memory 202180 kb
Host smart-3d217399-cb53-4a79-a3de-f9067d5d7a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146709779 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_fsm_reset.3146709779
Directory /workspace/3.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/3.adc_ctrl_lowpower_counter.2133821264
Short name T677
Test name
Test status
Simulation time 48330259916 ps
CPU time 102.45 seconds
Started Jul 09 06:33:03 PM PDT 24
Finished Jul 09 06:35:00 PM PDT 24
Peak memory 201656 kb
Host smart-b6822353-66c5-481b-9b6c-72ded74eaa1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133821264 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_lowpower_counter.2133821264
Directory /workspace/3.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_poweron_counter.1789557848
Short name T407
Test name
Test status
Simulation time 4284175024 ps
CPU time 2.81 seconds
Started Jul 09 06:32:59 PM PDT 24
Finished Jul 09 06:33:17 PM PDT 24
Peak memory 201736 kb
Host smart-373c122c-895e-4a97-af4c-d7fe5a7662ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789557848 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_poweron_counter.1789557848
Directory /workspace/3.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/3.adc_ctrl_sec_cm.3071314854
Short name T64
Test name
Test status
Simulation time 8696525758 ps
CPU time 5.66 seconds
Started Jul 09 06:33:01 PM PDT 24
Finished Jul 09 06:33:21 PM PDT 24
Peak memory 218180 kb
Host smart-a6fe17e4-daaa-45f9-bb3a-397bcd8ff72e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071314854 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_sec_cm.3071314854
Directory /workspace/3.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/3.adc_ctrl_smoke.1857784709
Short name T767
Test name
Test status
Simulation time 5865427366 ps
CPU time 7.6 seconds
Started Jul 09 06:32:57 PM PDT 24
Finished Jul 09 06:33:21 PM PDT 24
Peak memory 201744 kb
Host smart-65f8f391-d685-4410-a169-6950d9890158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857784709 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_smoke.1857784709
Directory /workspace/3.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/3.adc_ctrl_stress_all_with_rand_reset.1458811490
Short name T719
Test name
Test status
Simulation time 169347667999 ps
CPU time 405.31 seconds
Started Jul 09 06:33:06 PM PDT 24
Finished Jul 09 06:40:04 PM PDT 24
Peak memory 210624 kb
Host smart-d77283b2-60b2-41d5-a206-1267284ca64a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458811490 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 3.adc_ctrl_stress_all_with_rand_reset.1458811490
Directory /workspace/3.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_alert_test.3870895066
Short name T482
Test name
Test status
Simulation time 326059375 ps
CPU time 0.72 seconds
Started Jul 09 06:36:40 PM PDT 24
Finished Jul 09 06:36:42 PM PDT 24
Peak memory 201672 kb
Host smart-d7f47430-c460-4c11-b717-e1c6d1b37df7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870895066 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_alert_test.3870895066
Directory /workspace/30.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.adc_ctrl_clock_gating.2818230481
Short name T773
Test name
Test status
Simulation time 181054317388 ps
CPU time 159.68 seconds
Started Jul 09 06:36:36 PM PDT 24
Finished Jul 09 06:39:17 PM PDT 24
Peak memory 201908 kb
Host smart-faf70f82-dd53-499e-a2f0-adbaed5d8591
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818230481 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_clock_gat
ing.2818230481
Directory /workspace/30.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt.2996427756
Short name T579
Test name
Test status
Simulation time 327364406115 ps
CPU time 368.05 seconds
Started Jul 09 06:36:30 PM PDT 24
Finished Jul 09 06:42:39 PM PDT 24
Peak memory 201808 kb
Host smart-28faa0ea-f8c4-4898-8132-7405f70a62f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996427756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interrupt.2996427756
Directory /workspace/30.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_interrupt_fixed.3253319131
Short name T557
Test name
Test status
Simulation time 332761619719 ps
CPU time 393.88 seconds
Started Jul 09 06:36:31 PM PDT 24
Finished Jul 09 06:43:06 PM PDT 24
Peak memory 201920 kb
Host smart-a34d092f-2044-481c-94ba-78bbc48598df
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253319131 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_interru
pt_fixed.3253319131
Directory /workspace/30.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled.2969381911
Short name T789
Test name
Test status
Simulation time 331877193665 ps
CPU time 204.27 seconds
Started Jul 09 06:36:31 PM PDT 24
Finished Jul 09 06:39:57 PM PDT 24
Peak memory 201916 kb
Host smart-c446998d-f5ef-4b92-96ec-2674948c2471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2969381911 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled.2969381911
Directory /workspace/30.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_polled_fixed.239996898
Short name T658
Test name
Test status
Simulation time 168863340092 ps
CPU time 100.22 seconds
Started Jul 09 06:36:31 PM PDT 24
Finished Jul 09 06:38:12 PM PDT 24
Peak memory 201924 kb
Host smart-7de6ce4e-2f31-4327-a7c2-0ad2f4f37f0d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=239996898 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters_polled_fixe
d.239996898
Directory /workspace/30.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup.1523042884
Short name T145
Test name
Test status
Simulation time 583495480955 ps
CPU time 343.94 seconds
Started Jul 09 06:36:30 PM PDT 24
Finished Jul 09 06:42:15 PM PDT 24
Peak memory 201948 kb
Host smart-a45beda2-b9f3-4783-9311-49513f312c60
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523042884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_filters
_wakeup.1523042884
Directory /workspace/30.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/30.adc_ctrl_filters_wakeup_fixed.3977979262
Short name T30
Test name
Test status
Simulation time 210304467052 ps
CPU time 242.08 seconds
Started Jul 09 06:36:30 PM PDT 24
Finished Jul 09 06:40:33 PM PDT 24
Peak memory 201836 kb
Host smart-88bf510a-3e19-4025-83d4-c0319d73eedd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977979262 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30
.adc_ctrl_filters_wakeup_fixed.3977979262
Directory /workspace/30.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/30.adc_ctrl_fsm_reset.3314137521
Short name T51
Test name
Test status
Simulation time 104018516127 ps
CPU time 410.83 seconds
Started Jul 09 06:36:36 PM PDT 24
Finished Jul 09 06:43:29 PM PDT 24
Peak memory 202224 kb
Host smart-17c061aa-b775-47d2-807a-648f4a22ce7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314137521 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_fsm_reset.3314137521
Directory /workspace/30.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/30.adc_ctrl_lowpower_counter.2172510192
Short name T432
Test name
Test status
Simulation time 42041471523 ps
CPU time 92.24 seconds
Started Jul 09 06:36:35 PM PDT 24
Finished Jul 09 06:38:08 PM PDT 24
Peak memory 201716 kb
Host smart-bdbd55e2-13ed-4612-8a47-72b8ab42bb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172510192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_lowpower_counter.2172510192
Directory /workspace/30.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_poweron_counter.296226665
Short name T369
Test name
Test status
Simulation time 3462209008 ps
CPU time 8.19 seconds
Started Jul 09 06:36:37 PM PDT 24
Finished Jul 09 06:36:46 PM PDT 24
Peak memory 201720 kb
Host smart-2279d39a-2731-4b7d-be21-0901b48aa7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296226665 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_poweron_counter.296226665
Directory /workspace/30.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/30.adc_ctrl_smoke.1445432988
Short name T514
Test name
Test status
Simulation time 6000279143 ps
CPU time 4.1 seconds
Started Jul 09 06:36:31 PM PDT 24
Finished Jul 09 06:36:37 PM PDT 24
Peak memory 201640 kb
Host smart-ec522681-b94e-4a4c-b7d1-ab0b0e39341d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445432988 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_smoke.1445432988
Directory /workspace/30.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/30.adc_ctrl_stress_all_with_rand_reset.1042913527
Short name T19
Test name
Test status
Simulation time 113220437119 ps
CPU time 115.58 seconds
Started Jul 09 06:36:35 PM PDT 24
Finished Jul 09 06:38:32 PM PDT 24
Peak memory 210308 kb
Host smart-45c2481b-98d8-4db8-a493-af7bd31b2c34
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042913527 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 30.adc_ctrl_stress_all_with_rand_reset.1042913527
Directory /workspace/30.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_alert_test.3446911604
Short name T695
Test name
Test status
Simulation time 480418198 ps
CPU time 1.58 seconds
Started Jul 09 06:36:48 PM PDT 24
Finished Jul 09 06:36:51 PM PDT 24
Peak memory 201648 kb
Host smart-1c41e211-e783-4132-8799-47b16a73657f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446911604 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_alert_test.3446911604
Directory /workspace/31.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.adc_ctrl_clock_gating.911275893
Short name T140
Test name
Test status
Simulation time 539709019896 ps
CPU time 300.02 seconds
Started Jul 09 06:36:47 PM PDT 24
Finished Jul 09 06:41:48 PM PDT 24
Peak memory 201904 kb
Host smart-22b48375-0628-415d-a2a5-fa38881764a8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911275893 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_clock_gati
ng.911275893
Directory /workspace/31.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_both.1316993010
Short name T48
Test name
Test status
Simulation time 333116633943 ps
CPU time 135.69 seconds
Started Jul 09 06:36:47 PM PDT 24
Finished Jul 09 06:39:03 PM PDT 24
Peak memory 202192 kb
Host smart-9d59e659-ae07-478a-9cb9-e5392537ec99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316993010 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_both.1316993010
Directory /workspace/31.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt.3140842652
Short name T645
Test name
Test status
Simulation time 332692663153 ps
CPU time 190.43 seconds
Started Jul 09 06:36:40 PM PDT 24
Finished Jul 09 06:39:51 PM PDT 24
Peak memory 201880 kb
Host smart-6a5e726d-018d-4648-b02c-ef485bc9c43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140842652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrupt.3140842652
Directory /workspace/31.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_interrupt_fixed.139532150
Short name T382
Test name
Test status
Simulation time 160760879465 ps
CPU time 384.61 seconds
Started Jul 09 06:36:45 PM PDT 24
Finished Jul 09 06:43:11 PM PDT 24
Peak memory 201896 kb
Host smart-0452cf45-5e7b-4afe-aa8d-2938f9a58b20
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=139532150 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_interrup
t_fixed.139532150
Directory /workspace/31.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled.2253067069
Short name T738
Test name
Test status
Simulation time 164876959897 ps
CPU time 94.31 seconds
Started Jul 09 06:36:40 PM PDT 24
Finished Jul 09 06:38:16 PM PDT 24
Peak memory 201932 kb
Host smart-24999bb8-e83b-4619-b6dd-00e94c4ca6d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253067069 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled.2253067069
Directory /workspace/31.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_polled_fixed.3544668094
Short name T389
Test name
Test status
Simulation time 163106047637 ps
CPU time 196.61 seconds
Started Jul 09 06:36:42 PM PDT 24
Finished Jul 09 06:40:00 PM PDT 24
Peak memory 201868 kb
Host smart-2b8c3fc9-85e5-448d-a835-2853fa830d08
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544668094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_filters_polled_fix
ed.3544668094
Directory /workspace/31.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_filters_wakeup_fixed.136224351
Short name T377
Test name
Test status
Simulation time 198109897130 ps
CPU time 119.66 seconds
Started Jul 09 06:36:45 PM PDT 24
Finished Jul 09 06:38:46 PM PDT 24
Peak memory 201892 kb
Host smart-c4b5cd48-4b71-4fa0-b3e3-e83369ab2170
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136224351 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.
adc_ctrl_filters_wakeup_fixed.136224351
Directory /workspace/31.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/31.adc_ctrl_fsm_reset.565182284
Short name T449
Test name
Test status
Simulation time 70872235746 ps
CPU time 388.97 seconds
Started Jul 09 06:36:50 PM PDT 24
Finished Jul 09 06:43:21 PM PDT 24
Peak memory 202220 kb
Host smart-c4649af5-f134-46a0-9f7b-4841f7e25245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565182284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_fsm_reset.565182284
Directory /workspace/31.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/31.adc_ctrl_lowpower_counter.3823132668
Short name T455
Test name
Test status
Simulation time 34768347905 ps
CPU time 48.8 seconds
Started Jul 09 06:36:45 PM PDT 24
Finished Jul 09 06:37:36 PM PDT 24
Peak memory 201708 kb
Host smart-3f0ab6df-20fc-4b2d-927d-e6f746f94c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823132668 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_lowpower_counter.3823132668
Directory /workspace/31.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_poweron_counter.707425023
Short name T546
Test name
Test status
Simulation time 2665889354 ps
CPU time 6.99 seconds
Started Jul 09 06:36:46 PM PDT 24
Finished Jul 09 06:36:54 PM PDT 24
Peak memory 201728 kb
Host smart-47213f72-ac9d-4c66-8a03-1bd371c59c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707425023 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_poweron_counter.707425023
Directory /workspace/31.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/31.adc_ctrl_smoke.171967310
Short name T398
Test name
Test status
Simulation time 5766351489 ps
CPU time 6.96 seconds
Started Jul 09 06:36:42 PM PDT 24
Finished Jul 09 06:36:50 PM PDT 24
Peak memory 201724 kb
Host smart-ef99c5f6-5ee2-409c-aee0-d329651904f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171967310 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_smoke.171967310
Directory /workspace/31.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/31.adc_ctrl_stress_all_with_rand_reset.3866368608
Short name T270
Test name
Test status
Simulation time 66275429231 ps
CPU time 141.99 seconds
Started Jul 09 06:36:50 PM PDT 24
Finished Jul 09 06:39:13 PM PDT 24
Peak memory 210520 kb
Host smart-7d02ceaf-cace-4420-84f2-975f8a84622a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866368608 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 31.adc_ctrl_stress_all_with_rand_reset.3866368608
Directory /workspace/31.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_alert_test.4104248767
Short name T780
Test name
Test status
Simulation time 466225186 ps
CPU time 1.46 seconds
Started Jul 09 06:37:07 PM PDT 24
Finished Jul 09 06:37:09 PM PDT 24
Peak memory 201672 kb
Host smart-4a7fe052-dfd1-4795-a317-a14de0cadbfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104248767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_alert_test.4104248767
Directory /workspace/32.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.adc_ctrl_clock_gating.465602368
Short name T740
Test name
Test status
Simulation time 193781339464 ps
CPU time 174.87 seconds
Started Jul 09 06:36:53 PM PDT 24
Finished Jul 09 06:39:50 PM PDT 24
Peak memory 201860 kb
Host smart-d1eca076-509a-4426-a1d3-fe9db72a409d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465602368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_clock_gati
ng.465602368
Directory /workspace/32.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_both.626947531
Short name T224
Test name
Test status
Simulation time 166848877105 ps
CPU time 397.73 seconds
Started Jul 09 06:36:56 PM PDT 24
Finished Jul 09 06:43:34 PM PDT 24
Peak memory 201916 kb
Host smart-6332af11-391d-4bbe-89c5-ac2d64203f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626947531 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_both.626947531
Directory /workspace/32.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt.1509123267
Short name T342
Test name
Test status
Simulation time 502313425967 ps
CPU time 298.41 seconds
Started Jul 09 06:36:56 PM PDT 24
Finished Jul 09 06:41:55 PM PDT 24
Peak memory 201932 kb
Host smart-d3c95bd3-04c5-4496-bf32-1d71c07d9c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509123267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrupt.1509123267
Directory /workspace/32.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_interrupt_fixed.149317870
Short name T571
Test name
Test status
Simulation time 329015613548 ps
CPU time 404.12 seconds
Started Jul 09 06:36:54 PM PDT 24
Finished Jul 09 06:43:39 PM PDT 24
Peak memory 201884 kb
Host smart-a0739562-d69c-4ad5-ad8d-ced1b82b861e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=149317870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_interrup
t_fixed.149317870
Directory /workspace/32.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled.3443130270
Short name T247
Test name
Test status
Simulation time 320141579133 ps
CPU time 106.4 seconds
Started Jul 09 06:36:50 PM PDT 24
Finished Jul 09 06:38:37 PM PDT 24
Peak memory 201824 kb
Host smart-239edcca-ef6e-40b3-80d9-7516c992fe54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443130270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled.3443130270
Directory /workspace/32.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_polled_fixed.2490659674
Short name T82
Test name
Test status
Simulation time 170387544963 ps
CPU time 188.09 seconds
Started Jul 09 06:36:55 PM PDT 24
Finished Jul 09 06:40:04 PM PDT 24
Peak memory 201964 kb
Host smart-c9316165-37fe-45c9-8109-1561c12788e0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490659674 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters_polled_fix
ed.2490659674
Directory /workspace/32.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup.3339954892
Short name T752
Test name
Test status
Simulation time 183774746250 ps
CPU time 109.88 seconds
Started Jul 09 06:36:56 PM PDT 24
Finished Jul 09 06:38:47 PM PDT 24
Peak memory 202204 kb
Host smart-3587e9c6-8c84-4a7a-89aa-e1a26a31c58d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339954892 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_filters
_wakeup.3339954892
Directory /workspace/32.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/32.adc_ctrl_filters_wakeup_fixed.2787449836
Short name T580
Test name
Test status
Simulation time 187426954198 ps
CPU time 407.62 seconds
Started Jul 09 06:36:55 PM PDT 24
Finished Jul 09 06:43:43 PM PDT 24
Peak memory 201912 kb
Host smart-33a27cce-dbeb-4262-ba74-daa5db9ab5fd
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787449836 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32
.adc_ctrl_filters_wakeup_fixed.2787449836
Directory /workspace/32.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/32.adc_ctrl_fsm_reset.4035827623
Short name T676
Test name
Test status
Simulation time 101624629920 ps
CPU time 480.76 seconds
Started Jul 09 06:36:57 PM PDT 24
Finished Jul 09 06:45:00 PM PDT 24
Peak memory 202456 kb
Host smart-f9c831af-01b2-44a7-8499-618e7080cd59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035827623 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_fsm_reset.4035827623
Directory /workspace/32.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/32.adc_ctrl_lowpower_counter.1634032163
Short name T494
Test name
Test status
Simulation time 22585596899 ps
CPU time 48.59 seconds
Started Jul 09 06:36:59 PM PDT 24
Finished Jul 09 06:37:49 PM PDT 24
Peak memory 201708 kb
Host smart-cb57cdd2-dc6b-4372-994a-60aac05141bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634032163 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_lowpower_counter.1634032163
Directory /workspace/32.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_poweron_counter.1369639572
Short name T496
Test name
Test status
Simulation time 3267645513 ps
CPU time 4.48 seconds
Started Jul 09 06:37:01 PM PDT 24
Finished Jul 09 06:37:07 PM PDT 24
Peak memory 201676 kb
Host smart-a5fc44c2-c7c6-454e-bae9-642e5d052865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369639572 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_poweron_counter.1369639572
Directory /workspace/32.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/32.adc_ctrl_smoke.1261427130
Short name T393
Test name
Test status
Simulation time 6001117439 ps
CPU time 3.86 seconds
Started Jul 09 06:36:49 PM PDT 24
Finished Jul 09 06:36:54 PM PDT 24
Peak memory 201708 kb
Host smart-f2b37841-9f1d-4756-a1e8-88abb975f9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261427130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_smoke.1261427130
Directory /workspace/32.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all.3773988951
Short name T161
Test name
Test status
Simulation time 364913562811 ps
CPU time 212.95 seconds
Started Jul 09 06:37:06 PM PDT 24
Finished Jul 09 06:40:40 PM PDT 24
Peak memory 202140 kb
Host smart-985e8094-f785-45c3-a82a-5cbee6aa18e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773988951 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all
.3773988951
Directory /workspace/32.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.adc_ctrl_stress_all_with_rand_reset.1621919044
Short name T668
Test name
Test status
Simulation time 36109557724 ps
CPU time 85.51 seconds
Started Jul 09 06:36:59 PM PDT 24
Finished Jul 09 06:38:26 PM PDT 24
Peak memory 211708 kb
Host smart-627b9d04-e398-415a-8acd-583a6d81bbd6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621919044 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 32.adc_ctrl_stress_all_with_rand_reset.1621919044
Directory /workspace/32.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_alert_test.4142612143
Short name T468
Test name
Test status
Simulation time 533130573 ps
CPU time 0.9 seconds
Started Jul 09 06:37:12 PM PDT 24
Finished Jul 09 06:37:14 PM PDT 24
Peak memory 201680 kb
Host smart-0aa90b56-a352-4a7c-b10d-a187ed75f647
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142612143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_alert_test.4142612143
Directory /workspace/33.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt.2040173940
Short name T165
Test name
Test status
Simulation time 163850739547 ps
CPU time 192.75 seconds
Started Jul 09 06:37:05 PM PDT 24
Finished Jul 09 06:40:18 PM PDT 24
Peak memory 201932 kb
Host smart-f32bc3f0-3d29-4abf-9a6e-911babc22a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040173940 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrupt.2040173940
Directory /workspace/33.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_interrupt_fixed.462221294
Short name T219
Test name
Test status
Simulation time 161136538529 ps
CPU time 50.16 seconds
Started Jul 09 06:37:05 PM PDT 24
Finished Jul 09 06:37:56 PM PDT 24
Peak memory 201856 kb
Host smart-a2f2b716-bb01-40d5-8f8f-c4f1221d9476
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=462221294 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_interrup
t_fixed.462221294
Directory /workspace/33.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled.3397034507
Short name T485
Test name
Test status
Simulation time 497022055193 ps
CPU time 1085.21 seconds
Started Jul 09 06:37:06 PM PDT 24
Finished Jul 09 06:55:12 PM PDT 24
Peak memory 201928 kb
Host smart-fb7eeabd-b920-432d-b8c2-ab43fd29a87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397034507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled.3397034507
Directory /workspace/33.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_polled_fixed.2263936134
Short name T181
Test name
Test status
Simulation time 483434165609 ps
CPU time 236.72 seconds
Started Jul 09 06:37:04 PM PDT 24
Finished Jul 09 06:41:01 PM PDT 24
Peak memory 201888 kb
Host smart-d59b8dd9-5bb2-4412-ac85-c977720326fa
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263936134 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters_polled_fix
ed.2263936134
Directory /workspace/33.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup.2624576622
Short name T277
Test name
Test status
Simulation time 176272201994 ps
CPU time 109.54 seconds
Started Jul 09 06:37:06 PM PDT 24
Finished Jul 09 06:38:57 PM PDT 24
Peak memory 201912 kb
Host smart-336947ad-2d78-421e-b5a3-dcebc671dcb2
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624576622 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_filters
_wakeup.2624576622
Directory /workspace/33.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/33.adc_ctrl_filters_wakeup_fixed.13223989
Short name T522
Test name
Test status
Simulation time 604026102117 ps
CPU time 1413.97 seconds
Started Jul 09 06:37:03 PM PDT 24
Finished Jul 09 07:00:38 PM PDT 24
Peak memory 201912 kb
Host smart-52a3ade4-504c-4285-a4c8-8ac51fc41982
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13223989 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=
adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.a
dc_ctrl_filters_wakeup_fixed.13223989
Directory /workspace/33.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/33.adc_ctrl_fsm_reset.392113502
Short name T697
Test name
Test status
Simulation time 99988187152 ps
CPU time 433.43 seconds
Started Jul 09 06:37:09 PM PDT 24
Finished Jul 09 06:44:23 PM PDT 24
Peak memory 202432 kb
Host smart-34ba39f1-8bd2-41c1-ab80-2e66ed134082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392113502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_fsm_reset.392113502
Directory /workspace/33.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/33.adc_ctrl_lowpower_counter.1067804005
Short name T163
Test name
Test status
Simulation time 30332529928 ps
CPU time 9.66 seconds
Started Jul 09 06:37:10 PM PDT 24
Finished Jul 09 06:37:21 PM PDT 24
Peak memory 201716 kb
Host smart-43de5b52-9d29-4272-9e80-9580930b3112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067804005 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_lowpower_counter.1067804005
Directory /workspace/33.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_poweron_counter.2145519355
Short name T714
Test name
Test status
Simulation time 3912881970 ps
CPU time 8.96 seconds
Started Jul 09 06:37:09 PM PDT 24
Finished Jul 09 06:37:19 PM PDT 24
Peak memory 201664 kb
Host smart-ef22a278-b8d2-4f56-b1d9-4b8fdec97bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145519355 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_poweron_counter.2145519355
Directory /workspace/33.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/33.adc_ctrl_smoke.2961454439
Short name T573
Test name
Test status
Simulation time 6052091192 ps
CPU time 13.86 seconds
Started Jul 09 06:37:06 PM PDT 24
Finished Jul 09 06:37:21 PM PDT 24
Peak memory 201732 kb
Host smart-fb0aa8b2-6783-4205-9d0f-fc0b7ee5d907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961454439 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_smoke.2961454439
Directory /workspace/33.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/33.adc_ctrl_stress_all_with_rand_reset.2200639510
Short name T88
Test name
Test status
Simulation time 181574955822 ps
CPU time 97.15 seconds
Started Jul 09 06:37:08 PM PDT 24
Finished Jul 09 06:38:46 PM PDT 24
Peak memory 210640 kb
Host smart-bfc9bd95-027c-4834-8dfa-fe43b2fe19df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200639510 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 33.adc_ctrl_stress_all_with_rand_reset.2200639510
Directory /workspace/33.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_alert_test.1377307870
Short name T785
Test name
Test status
Simulation time 404564133 ps
CPU time 1.08 seconds
Started Jul 09 06:37:18 PM PDT 24
Finished Jul 09 06:37:22 PM PDT 24
Peak memory 201504 kb
Host smart-0ddee73c-6592-4b46-91f5-b064e4a0e066
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377307870 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_alert_test.1377307870
Directory /workspace/34.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt.686288648
Short name T176
Test name
Test status
Simulation time 487718859538 ps
CPU time 280.8 seconds
Started Jul 09 06:37:18 PM PDT 24
Finished Jul 09 06:42:02 PM PDT 24
Peak memory 201904 kb
Host smart-e3633d3b-74f1-4d28-90cf-ba496c2ab628
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686288648 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interrupt.686288648
Directory /workspace/34.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_interrupt_fixed.1573321638
Short name T434
Test name
Test status
Simulation time 333059836320 ps
CPU time 733.27 seconds
Started Jul 09 06:37:13 PM PDT 24
Finished Jul 09 06:49:28 PM PDT 24
Peak memory 201828 kb
Host smart-d87a02a7-eaa0-4c0c-b6ea-c720d0f4dd51
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573321638 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_interru
pt_fixed.1573321638
Directory /workspace/34.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled.4034343605
Short name T501
Test name
Test status
Simulation time 166114526743 ps
CPU time 364.96 seconds
Started Jul 09 06:37:12 PM PDT 24
Finished Jul 09 06:43:18 PM PDT 24
Peak memory 201944 kb
Host smart-23e3e5ab-2995-4c3e-87cf-df11e8238b08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034343605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled.4034343605
Directory /workspace/34.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_polled_fixed.119086680
Short name T164
Test name
Test status
Simulation time 496983182345 ps
CPU time 1096.85 seconds
Started Jul 09 06:37:14 PM PDT 24
Finished Jul 09 06:55:33 PM PDT 24
Peak memory 201776 kb
Host smart-3aebe5ad-51f9-4267-ad32-7046267d1e30
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=119086680 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_polled_fixe
d.119086680
Directory /workspace/34.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup.51265317
Short name T326
Test name
Test status
Simulation time 172122146519 ps
CPU time 378.94 seconds
Started Jul 09 06:37:18 PM PDT 24
Finished Jul 09 06:43:39 PM PDT 24
Peak memory 201920 kb
Host smart-766a25d6-3f53-4251-8ae8-f95fc26973b4
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51265317 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_
wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_filters_w
akeup.51265317
Directory /workspace/34.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/34.adc_ctrl_filters_wakeup_fixed.2058749292
Short name T429
Test name
Test status
Simulation time 610553139195 ps
CPU time 674.17 seconds
Started Jul 09 06:37:19 PM PDT 24
Finished Jul 09 06:48:36 PM PDT 24
Peak memory 201960 kb
Host smart-afddde6a-f10b-4f58-a562-5c9527ab90ce
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058749292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34
.adc_ctrl_filters_wakeup_fixed.2058749292
Directory /workspace/34.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/34.adc_ctrl_fsm_reset.1069212876
Short name T610
Test name
Test status
Simulation time 132348928898 ps
CPU time 560.49 seconds
Started Jul 09 06:37:18 PM PDT 24
Finished Jul 09 06:46:41 PM PDT 24
Peak memory 202292 kb
Host smart-fa4e549c-a117-429a-aa79-73354636ebd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069212876 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_fsm_reset.1069212876
Directory /workspace/34.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/34.adc_ctrl_lowpower_counter.294274372
Short name T450
Test name
Test status
Simulation time 26152042173 ps
CPU time 14.44 seconds
Started Jul 09 06:37:22 PM PDT 24
Finished Jul 09 06:37:39 PM PDT 24
Peak memory 201720 kb
Host smart-3aaba483-ca11-4d57-b07b-e8d1ad2b6974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=294274372 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_lowpower_counter.294274372
Directory /workspace/34.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_poweron_counter.3416770180
Short name T592
Test name
Test status
Simulation time 4607700398 ps
CPU time 3.34 seconds
Started Jul 09 06:37:19 PM PDT 24
Finished Jul 09 06:37:25 PM PDT 24
Peak memory 201732 kb
Host smart-f569b477-07ab-46c6-bdc5-0cae7b0e4484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416770180 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_poweron_counter.3416770180
Directory /workspace/34.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/34.adc_ctrl_smoke.2113663038
Short name T109
Test name
Test status
Simulation time 5941305957 ps
CPU time 4.06 seconds
Started Jul 09 06:37:12 PM PDT 24
Finished Jul 09 06:37:17 PM PDT 24
Peak memory 201668 kb
Host smart-81c118ae-fca9-4d2b-a9bd-d609bb9fe90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113663038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_smoke.2113663038
Directory /workspace/34.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/34.adc_ctrl_stress_all.3122994570
Short name T693
Test name
Test status
Simulation time 489719303159 ps
CPU time 274.78 seconds
Started Jul 09 06:37:19 PM PDT 24
Finished Jul 09 06:41:57 PM PDT 24
Peak memory 201924 kb
Host smart-f871ea3f-8df9-4bb2-a6b8-2bd9ac9c136a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122994570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.adc_ctrl_stress_all
.3122994570
Directory /workspace/34.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.adc_ctrl_alert_test.1391432470
Short name T490
Test name
Test status
Simulation time 436774477 ps
CPU time 1 seconds
Started Jul 09 06:37:27 PM PDT 24
Finished Jul 09 06:37:30 PM PDT 24
Peak memory 201656 kb
Host smart-a9952b9c-933c-4449-b03b-75d87775f6a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391432470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_alert_test.1391432470
Directory /workspace/35.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.adc_ctrl_clock_gating.3575489763
Short name T282
Test name
Test status
Simulation time 357398072836 ps
CPU time 398.86 seconds
Started Jul 09 06:37:24 PM PDT 24
Finished Jul 09 06:44:04 PM PDT 24
Peak memory 201864 kb
Host smart-c78a234c-cab1-454a-946e-e28623b4dc23
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575489763 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_clock_gat
ing.3575489763
Directory /workspace/35.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_both.1968803640
Short name T179
Test name
Test status
Simulation time 344460522912 ps
CPU time 218.84 seconds
Started Jul 09 06:37:31 PM PDT 24
Finished Jul 09 06:41:11 PM PDT 24
Peak memory 201988 kb
Host smart-fca1e32e-61b9-4dcf-97f9-066618f2ec53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968803640 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_both.1968803640
Directory /workspace/35.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt.1274294863
Short name T763
Test name
Test status
Simulation time 163900817377 ps
CPU time 84.73 seconds
Started Jul 09 06:37:26 PM PDT 24
Finished Jul 09 06:38:52 PM PDT 24
Peak memory 201928 kb
Host smart-f953b13e-7c2d-40a9-bc45-989dbed0e7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274294863 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interrupt.1274294863
Directory /workspace/35.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_interrupt_fixed.2476333078
Short name T435
Test name
Test status
Simulation time 328160072859 ps
CPU time 802.18 seconds
Started Jul 09 06:37:26 PM PDT 24
Finished Jul 09 06:50:49 PM PDT 24
Peak memory 201816 kb
Host smart-fbb9c3ea-7617-43a2-9df7-d893a03489d8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476333078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_interru
pt_fixed.2476333078
Directory /workspace/35.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled.2361977425
Short name T258
Test name
Test status
Simulation time 163900762060 ps
CPU time 205.32 seconds
Started Jul 09 06:37:23 PM PDT 24
Finished Jul 09 06:40:50 PM PDT 24
Peak memory 201988 kb
Host smart-a2759c93-9663-4158-ada5-a92879ea51e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361977425 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled.2361977425
Directory /workspace/35.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_polled_fixed.1640473230
Short name T715
Test name
Test status
Simulation time 503846740518 ps
CPU time 561.59 seconds
Started Jul 09 06:37:24 PM PDT 24
Finished Jul 09 06:46:47 PM PDT 24
Peak memory 201876 kb
Host smart-13b5a57e-9037-4b0c-96e2-3af1898d8686
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640473230 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters_polled_fix
ed.1640473230
Directory /workspace/35.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup.3924944016
Short name T93
Test name
Test status
Simulation time 376177291460 ps
CPU time 915.92 seconds
Started Jul 09 06:37:23 PM PDT 24
Finished Jul 09 06:52:41 PM PDT 24
Peak memory 201908 kb
Host smart-1063682d-97d9-4f54-9fbb-17ae2e3c3741
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924944016 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_filters
_wakeup.3924944016
Directory /workspace/35.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/35.adc_ctrl_filters_wakeup_fixed.1357421657
Short name T706
Test name
Test status
Simulation time 194672062314 ps
CPU time 402.07 seconds
Started Jul 09 06:37:24 PM PDT 24
Finished Jul 09 06:44:07 PM PDT 24
Peak memory 201908 kb
Host smart-54ac8623-db76-452d-8876-48aeb8196a04
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357421657 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35
.adc_ctrl_filters_wakeup_fixed.1357421657
Directory /workspace/35.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/35.adc_ctrl_fsm_reset.2358712652
Short name T685
Test name
Test status
Simulation time 91840082390 ps
CPU time 511.14 seconds
Started Jul 09 06:37:30 PM PDT 24
Finished Jul 09 06:46:02 PM PDT 24
Peak memory 202304 kb
Host smart-1b7c62d4-1db3-4e3d-bdec-b4848c562c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358712652 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_fsm_reset.2358712652
Directory /workspace/35.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/35.adc_ctrl_lowpower_counter.793544144
Short name T537
Test name
Test status
Simulation time 22839264868 ps
CPU time 13.62 seconds
Started Jul 09 06:37:29 PM PDT 24
Finished Jul 09 06:37:44 PM PDT 24
Peak memory 201736 kb
Host smart-a6f19544-a048-41e6-8918-f721c1374ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793544144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_lowpower_counter.793544144
Directory /workspace/35.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_poweron_counter.951962459
Short name T538
Test name
Test status
Simulation time 3611700868 ps
CPU time 5.11 seconds
Started Jul 09 06:37:31 PM PDT 24
Finished Jul 09 06:37:38 PM PDT 24
Peak memory 201736 kb
Host smart-2d41012f-9c0b-4f3d-8d0d-40894a821fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951962459 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_poweron_counter.951962459
Directory /workspace/35.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/35.adc_ctrl_smoke.1808120338
Short name T525
Test name
Test status
Simulation time 5775490404 ps
CPU time 7.39 seconds
Started Jul 09 06:37:27 PM PDT 24
Finished Jul 09 06:37:35 PM PDT 24
Peak memory 201732 kb
Host smart-fbda4522-3ae7-4601-bead-2530a602b379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808120338 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_smoke.1808120338
Directory /workspace/35.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/35.adc_ctrl_stress_all.3881117745
Short name T168
Test name
Test status
Simulation time 381215993039 ps
CPU time 687.44 seconds
Started Jul 09 06:37:31 PM PDT 24
Finished Jul 09 06:48:59 PM PDT 24
Peak memory 201968 kb
Host smart-6d0ab3e4-7948-4deb-921c-5ef025f40242
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881117745 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.adc_ctrl_stress_all
.3881117745
Directory /workspace/35.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_alert_test.2152159687
Short name T587
Test name
Test status
Simulation time 535994726 ps
CPU time 0.82 seconds
Started Jul 09 06:37:50 PM PDT 24
Finished Jul 09 06:37:52 PM PDT 24
Peak memory 201852 kb
Host smart-173d69c1-499e-4718-b5ff-fbf1e4e8eb23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152159687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_alert_test.2152159687
Directory /workspace/36.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.adc_ctrl_clock_gating.1064054776
Short name T286
Test name
Test status
Simulation time 161292147440 ps
CPU time 51.12 seconds
Started Jul 09 06:37:43 PM PDT 24
Finished Jul 09 06:38:35 PM PDT 24
Peak memory 201904 kb
Host smart-6b40a846-cd38-4eec-bd9a-c497caa69b6d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064054776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_clock_gat
ing.1064054776
Directory /workspace/36.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_both.2049164377
Short name T567
Test name
Test status
Simulation time 361690537607 ps
CPU time 812.08 seconds
Started Jul 09 06:37:43 PM PDT 24
Finished Jul 09 06:51:17 PM PDT 24
Peak memory 201948 kb
Host smart-bce7ab49-691a-41f7-9df9-31c04a4179a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049164377 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_both.2049164377
Directory /workspace/36.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt.3381454780
Short name T665
Test name
Test status
Simulation time 170667446745 ps
CPU time 369.58 seconds
Started Jul 09 06:37:39 PM PDT 24
Finished Jul 09 06:43:49 PM PDT 24
Peak memory 201952 kb
Host smart-08daad26-3c0d-4d08-81d0-7a6a7f98760b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381454780 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interrupt.3381454780
Directory /workspace/36.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_interrupt_fixed.2567673308
Short name T461
Test name
Test status
Simulation time 160747761768 ps
CPU time 102.48 seconds
Started Jul 09 06:37:38 PM PDT 24
Finished Jul 09 06:39:21 PM PDT 24
Peak memory 201880 kb
Host smart-a5cefae7-8fb8-4ece-aa11-7ca0db963448
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567673308 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_interru
pt_fixed.2567673308
Directory /workspace/36.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled.1706094232
Short name T617
Test name
Test status
Simulation time 161833784794 ps
CPU time 175.02 seconds
Started Jul 09 06:37:35 PM PDT 24
Finished Jul 09 06:40:31 PM PDT 24
Peak memory 201924 kb
Host smart-f55d966c-84c5-4f08-9cd2-b1b1a2a572c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706094232 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled.1706094232
Directory /workspace/36.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_polled_fixed.3529214976
Short name T683
Test name
Test status
Simulation time 496071666946 ps
CPU time 1040.77 seconds
Started Jul 09 06:37:34 PM PDT 24
Finished Jul 09 06:54:56 PM PDT 24
Peak memory 201956 kb
Host smart-ecd92107-5f9e-488f-a9c9-472b6e5d199d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529214976 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_filters_polled_fix
ed.3529214976
Directory /workspace/36.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_filters_wakeup_fixed.2416538258
Short name T510
Test name
Test status
Simulation time 616456535684 ps
CPU time 375.76 seconds
Started Jul 09 06:37:43 PM PDT 24
Finished Jul 09 06:44:01 PM PDT 24
Peak memory 201944 kb
Host smart-e4e691c8-5e6f-42ed-a6bd-8e4aeac8ba81
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416538258 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36
.adc_ctrl_filters_wakeup_fixed.2416538258
Directory /workspace/36.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/36.adc_ctrl_fsm_reset.1683706112
Short name T202
Test name
Test status
Simulation time 88236955930 ps
CPU time 386.69 seconds
Started Jul 09 06:37:44 PM PDT 24
Finished Jul 09 06:44:13 PM PDT 24
Peak memory 202300 kb
Host smart-6223a601-d8d5-4645-895a-0abc3436b608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683706112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_fsm_reset.1683706112
Directory /workspace/36.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/36.adc_ctrl_lowpower_counter.2714456761
Short name T682
Test name
Test status
Simulation time 25800950399 ps
CPU time 46.96 seconds
Started Jul 09 06:37:44 PM PDT 24
Finished Jul 09 06:38:33 PM PDT 24
Peak memory 201696 kb
Host smart-4a309eb1-866a-44d8-844d-3348981ab4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714456761 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_lowpower_counter.2714456761
Directory /workspace/36.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_poweron_counter.3600653936
Short name T575
Test name
Test status
Simulation time 3340050087 ps
CPU time 1.05 seconds
Started Jul 09 06:37:44 PM PDT 24
Finished Jul 09 06:37:48 PM PDT 24
Peak memory 201672 kb
Host smart-4624a195-61fe-49c4-8994-5d0c9b99e358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600653936 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_poweron_counter.3600653936
Directory /workspace/36.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/36.adc_ctrl_smoke.2061707525
Short name T743
Test name
Test status
Simulation time 5885784704 ps
CPU time 13.67 seconds
Started Jul 09 06:37:33 PM PDT 24
Finished Jul 09 06:37:48 PM PDT 24
Peak memory 201732 kb
Host smart-8ec8ae59-f0cf-49a7-ac8b-6b609706b2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061707525 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_smoke.2061707525
Directory /workspace/36.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all.529621829
Short name T605
Test name
Test status
Simulation time 293805243652 ps
CPU time 615.02 seconds
Started Jul 09 06:37:47 PM PDT 24
Finished Jul 09 06:48:03 PM PDT 24
Peak memory 210312 kb
Host smart-05ae62dc-57cb-4b51-81af-68b88a71ec9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529621829 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all.
529621829
Directory /workspace/36.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.adc_ctrl_stress_all_with_rand_reset.3413350339
Short name T192
Test name
Test status
Simulation time 71788964286 ps
CPU time 162.11 seconds
Started Jul 09 06:37:46 PM PDT 24
Finished Jul 09 06:40:30 PM PDT 24
Peak memory 210552 kb
Host smart-9c00ffae-c784-4139-98ad-c7a699bf6bc8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413350339 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 36.adc_ctrl_stress_all_with_rand_reset.3413350339
Directory /workspace/36.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_alert_test.320866776
Short name T486
Test name
Test status
Simulation time 287218153 ps
CPU time 0.95 seconds
Started Jul 09 06:38:04 PM PDT 24
Finished Jul 09 06:38:06 PM PDT 24
Peak memory 201688 kb
Host smart-3b75bf5b-8108-4815-8412-400bed44d776
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320866776 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_alert_test.320866776
Directory /workspace/37.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.adc_ctrl_clock_gating.1124166701
Short name T323
Test name
Test status
Simulation time 179376660864 ps
CPU time 385.85 seconds
Started Jul 09 06:37:57 PM PDT 24
Finished Jul 09 06:44:24 PM PDT 24
Peak memory 201872 kb
Host smart-05f61ab6-9ac0-4ec4-87ac-7f1514b949d8
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124166701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_clock_gat
ing.1124166701
Directory /workspace/37.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_both.1839216884
Short name T673
Test name
Test status
Simulation time 187797491294 ps
CPU time 419.21 seconds
Started Jul 09 06:37:55 PM PDT 24
Finished Jul 09 06:44:56 PM PDT 24
Peak memory 201872 kb
Host smart-7ea36728-0093-4839-ac65-a1c4382395c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839216884 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_both.1839216884
Directory /workspace/37.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt.912164514
Short name T792
Test name
Test status
Simulation time 495435714351 ps
CPU time 1102.32 seconds
Started Jul 09 06:37:54 PM PDT 24
Finished Jul 09 06:56:17 PM PDT 24
Peak memory 201920 kb
Host smart-4ce91b78-ff0d-4af8-be0c-1ae77e508f1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912164514 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interrupt.912164514
Directory /workspace/37.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_interrupt_fixed.2662547141
Short name T489
Test name
Test status
Simulation time 489774377373 ps
CPU time 1062.2 seconds
Started Jul 09 06:37:55 PM PDT 24
Finished Jul 09 06:55:39 PM PDT 24
Peak memory 202076 kb
Host smart-fecb9151-696a-4e32-978e-ffc1004ca662
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662547141 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_interru
pt_fixed.2662547141
Directory /workspace/37.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled.1395679878
Short name T529
Test name
Test status
Simulation time 328926798270 ps
CPU time 396.82 seconds
Started Jul 09 06:37:49 PM PDT 24
Finished Jul 09 06:44:28 PM PDT 24
Peak memory 202152 kb
Host smart-5c138f4e-3146-40bd-8146-3ac5ae654931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395679878 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled.1395679878
Directory /workspace/37.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_polled_fixed.1638399245
Short name T105
Test name
Test status
Simulation time 166152992438 ps
CPU time 327.66 seconds
Started Jul 09 06:37:49 PM PDT 24
Finished Jul 09 06:43:19 PM PDT 24
Peak memory 201908 kb
Host smart-b08f9c7e-c85d-4411-b8a5-b4005b3ceb30
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638399245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters_polled_fix
ed.1638399245
Directory /workspace/37.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup.3635871915
Short name T769
Test name
Test status
Simulation time 196646101389 ps
CPU time 443.53 seconds
Started Jul 09 06:37:53 PM PDT 24
Finished Jul 09 06:45:17 PM PDT 24
Peak memory 202000 kb
Host smart-9a2773d9-5c5d-4a04-9976-ed83a617adaf
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635871915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_filters
_wakeup.3635871915
Directory /workspace/37.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/37.adc_ctrl_filters_wakeup_fixed.923419194
Short name T24
Test name
Test status
Simulation time 207987738211 ps
CPU time 469.52 seconds
Started Jul 09 06:38:03 PM PDT 24
Finished Jul 09 06:45:53 PM PDT 24
Peak memory 201884 kb
Host smart-f56f9e42-a050-4b47-a8f2-112f9b15ab29
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923419194 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.
adc_ctrl_filters_wakeup_fixed.923419194
Directory /workspace/37.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/37.adc_ctrl_fsm_reset.895784270
Short name T555
Test name
Test status
Simulation time 93756907337 ps
CPU time 330.82 seconds
Started Jul 09 06:38:02 PM PDT 24
Finished Jul 09 06:43:34 PM PDT 24
Peak memory 202212 kb
Host smart-6fbf5e97-89fc-4b7e-a8dc-68b844ae9e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895784270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_fsm_reset.895784270
Directory /workspace/37.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/37.adc_ctrl_lowpower_counter.1723983619
Short name T532
Test name
Test status
Simulation time 42303146164 ps
CPU time 97.66 seconds
Started Jul 09 06:38:03 PM PDT 24
Finished Jul 09 06:39:42 PM PDT 24
Peak memory 201736 kb
Host smart-0e59b063-21fd-44cb-b551-50a05c314f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723983619 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_lowpower_counter.1723983619
Directory /workspace/37.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_poweron_counter.1527739570
Short name T448
Test name
Test status
Simulation time 3417689695 ps
CPU time 4.2 seconds
Started Jul 09 06:37:56 PM PDT 24
Finished Jul 09 06:38:02 PM PDT 24
Peak memory 201728 kb
Host smart-e03ab3c4-1c09-4bb5-9cd6-af6dfcb916eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527739570 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_poweron_counter.1527739570
Directory /workspace/37.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/37.adc_ctrl_smoke.2313202301
Short name T597
Test name
Test status
Simulation time 5869877193 ps
CPU time 4.5 seconds
Started Jul 09 06:37:48 PM PDT 24
Finished Jul 09 06:37:55 PM PDT 24
Peak memory 201732 kb
Host smart-0a16a103-74a3-47f1-8fa6-e4ead99450af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313202301 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_smoke.2313202301
Directory /workspace/37.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/37.adc_ctrl_stress_all.2464886568
Short name T141
Test name
Test status
Simulation time 489984638823 ps
CPU time 1101.36 seconds
Started Jul 09 06:37:57 PM PDT 24
Finished Jul 09 06:56:20 PM PDT 24
Peak memory 201952 kb
Host smart-e103d78b-0388-4066-8f1f-98a2163b0036
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464886568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.adc_ctrl_stress_all
.2464886568
Directory /workspace/37.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_alert_test.2925480534
Short name T585
Test name
Test status
Simulation time 451106347 ps
CPU time 0.91 seconds
Started Jul 09 06:38:14 PM PDT 24
Finished Jul 09 06:38:17 PM PDT 24
Peak memory 201672 kb
Host smart-71a03522-d80a-42ec-8e1d-ca6178724130
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925480534 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_alert_test.2925480534
Directory /workspace/38.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.adc_ctrl_clock_gating.1401801088
Short name T657
Test name
Test status
Simulation time 326591506523 ps
CPU time 151.18 seconds
Started Jul 09 06:38:09 PM PDT 24
Finished Jul 09 06:40:41 PM PDT 24
Peak memory 201980 kb
Host smart-2ab85678-6def-47f9-b41f-eb1415e010dd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401801088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_clock_gat
ing.1401801088
Directory /workspace/38.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt.2538465089
Short name T347
Test name
Test status
Simulation time 332888279236 ps
CPU time 806.61 seconds
Started Jul 09 06:38:03 PM PDT 24
Finished Jul 09 06:51:31 PM PDT 24
Peak memory 201896 kb
Host smart-6a942c26-eb2a-465b-ae4d-7267f7cfc9ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2538465089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrupt.2538465089
Directory /workspace/38.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_interrupt_fixed.510145221
Short name T520
Test name
Test status
Simulation time 499845582570 ps
CPU time 608.85 seconds
Started Jul 09 06:38:03 PM PDT 24
Finished Jul 09 06:48:13 PM PDT 24
Peak memory 201892 kb
Host smart-fe9b4650-815d-4ef0-b808-66ab6403f0ab
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=510145221 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_interrup
t_fixed.510145221
Directory /workspace/38.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled.784607033
Short name T287
Test name
Test status
Simulation time 330442433791 ps
CPU time 190.86 seconds
Started Jul 09 06:38:05 PM PDT 24
Finished Jul 09 06:41:17 PM PDT 24
Peak memory 201916 kb
Host smart-dd6ff7f0-d5af-4f74-aa3e-21ce4e9bc3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784607033 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled.784607033
Directory /workspace/38.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_polled_fixed.1583055162
Short name T376
Test name
Test status
Simulation time 323317714707 ps
CPU time 703.14 seconds
Started Jul 09 06:38:01 PM PDT 24
Finished Jul 09 06:49:46 PM PDT 24
Peak memory 201724 kb
Host smart-12f51507-8ff2-44a6-9e62-6a4fe68c508a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583055162 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters_polled_fix
ed.1583055162
Directory /workspace/38.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup.3161713160
Short name T348
Test name
Test status
Simulation time 418873068329 ps
CPU time 906.38 seconds
Started Jul 09 06:38:04 PM PDT 24
Finished Jul 09 06:53:11 PM PDT 24
Peak memory 201936 kb
Host smart-d2b0e476-e987-4768-90e2-fc13d434b9ae
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161713160 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_filters
_wakeup.3161713160
Directory /workspace/38.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/38.adc_ctrl_filters_wakeup_fixed.3083340306
Short name T642
Test name
Test status
Simulation time 203601884789 ps
CPU time 309.1 seconds
Started Jul 09 06:38:09 PM PDT 24
Finished Jul 09 06:43:20 PM PDT 24
Peak memory 201908 kb
Host smart-675f1c02-a8b8-435a-ab6a-e2db8791a972
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083340306 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38
.adc_ctrl_filters_wakeup_fixed.3083340306
Directory /workspace/38.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/38.adc_ctrl_fsm_reset.1735465273
Short name T356
Test name
Test status
Simulation time 133992096881 ps
CPU time 720.65 seconds
Started Jul 09 06:38:38 PM PDT 24
Finished Jul 09 06:50:40 PM PDT 24
Peak memory 202204 kb
Host smart-9a416507-8330-4d60-8126-367c0d6061c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735465273 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_fsm_reset.1735465273
Directory /workspace/38.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/38.adc_ctrl_lowpower_counter.703818277
Short name T735
Test name
Test status
Simulation time 38617225000 ps
CPU time 21.48 seconds
Started Jul 09 06:38:14 PM PDT 24
Finished Jul 09 06:38:38 PM PDT 24
Peak memory 201736 kb
Host smart-63f39ae5-621c-4f7e-a765-1534472cfc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703818277 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_lowpower_counter.703818277
Directory /workspace/38.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_poweron_counter.954477826
Short name T447
Test name
Test status
Simulation time 2890866439 ps
CPU time 7.33 seconds
Started Jul 09 06:38:13 PM PDT 24
Finished Jul 09 06:38:23 PM PDT 24
Peak memory 201940 kb
Host smart-b6e07c55-afd2-4fdc-a1fc-5dca6d1003be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954477826 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_poweron_counter.954477826
Directory /workspace/38.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/38.adc_ctrl_smoke.4077698088
Short name T397
Test name
Test status
Simulation time 5672697376 ps
CPU time 7.57 seconds
Started Jul 09 06:38:04 PM PDT 24
Finished Jul 09 06:38:13 PM PDT 24
Peak memory 201732 kb
Host smart-5e03aafe-4f60-4c59-8ef4-c95da870becf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077698088 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_smoke.4077698088
Directory /workspace/38.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all.3217112833
Short name T521
Test name
Test status
Simulation time 184790505235 ps
CPU time 116.13 seconds
Started Jul 09 06:38:12 PM PDT 24
Finished Jul 09 06:40:10 PM PDT 24
Peak memory 201948 kb
Host smart-21b07b3e-0215-47b9-b0e8-0f14ddc79191
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217112833 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all
.3217112833
Directory /workspace/38.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.adc_ctrl_stress_all_with_rand_reset.1400088732
Short name T214
Test name
Test status
Simulation time 214433476680 ps
CPU time 510.52 seconds
Started Jul 09 06:38:13 PM PDT 24
Finished Jul 09 06:46:45 PM PDT 24
Peak memory 210560 kb
Host smart-20338f7b-b96b-4818-a4be-10b1247dac90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400088732 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 38.adc_ctrl_stress_all_with_rand_reset.1400088732
Directory /workspace/38.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_alert_test.2223669138
Short name T631
Test name
Test status
Simulation time 479220853 ps
CPU time 1.5 seconds
Started Jul 09 06:38:28 PM PDT 24
Finished Jul 09 06:38:30 PM PDT 24
Peak memory 201652 kb
Host smart-063f7c34-eafd-4f9d-ace9-d9bc4d0a9ebb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223669138 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_alert_test.2223669138
Directory /workspace/39.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.adc_ctrl_clock_gating.485969794
Short name T734
Test name
Test status
Simulation time 164137628111 ps
CPU time 33.08 seconds
Started Jul 09 06:38:24 PM PDT 24
Finished Jul 09 06:38:59 PM PDT 24
Peak memory 201868 kb
Host smart-2f2319bb-895f-4319-b588-6dc841af91dc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485969794 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_clock_gati
ng.485969794
Directory /workspace/39.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_both.1513214433
Short name T241
Test name
Test status
Simulation time 486831313758 ps
CPU time 1138.12 seconds
Started Jul 09 06:38:23 PM PDT 24
Finished Jul 09 06:57:23 PM PDT 24
Peak memory 201996 kb
Host smart-a97a1712-de2d-402c-ba15-35f4f77b1809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513214433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_both.1513214433
Directory /workspace/39.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt.1355816191
Short name T563
Test name
Test status
Simulation time 324261222920 ps
CPU time 156.7 seconds
Started Jul 09 06:38:18 PM PDT 24
Finished Jul 09 06:40:57 PM PDT 24
Peak memory 201996 kb
Host smart-fd907f55-52be-4587-abac-c99c8032ca82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355816191 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrupt.1355816191
Directory /workspace/39.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_interrupt_fixed.433413176
Short name T528
Test name
Test status
Simulation time 320815709152 ps
CPU time 704.39 seconds
Started Jul 09 06:38:18 PM PDT 24
Finished Jul 09 06:50:06 PM PDT 24
Peak memory 201852 kb
Host smart-a8f79ad8-b5db-40dc-88ab-744944da3b92
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=433413176 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_interrup
t_fixed.433413176
Directory /workspace/39.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled.657283319
Short name T91
Test name
Test status
Simulation time 164509614621 ps
CPU time 357.94 seconds
Started Jul 09 06:38:17 PM PDT 24
Finished Jul 09 06:44:18 PM PDT 24
Peak memory 201980 kb
Host smart-7897cbf0-99ee-4d7c-811d-bf6622fa4033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657283319 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled.657283319
Directory /workspace/39.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_polled_fixed.1116620079
Short name T108
Test name
Test status
Simulation time 495661477299 ps
CPU time 268.48 seconds
Started Jul 09 06:38:17 PM PDT 24
Finished Jul 09 06:42:48 PM PDT 24
Peak memory 201940 kb
Host smart-1cbdac81-9a71-45b9-b176-fe6a4258106d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116620079 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_filters_polled_fix
ed.1116620079
Directory /workspace/39.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_filters_wakeup_fixed.1117002204
Short name T25
Test name
Test status
Simulation time 592661163865 ps
CPU time 1224.27 seconds
Started Jul 09 06:38:24 PM PDT 24
Finished Jul 09 06:58:50 PM PDT 24
Peak memory 201924 kb
Host smart-c1254c8a-9aee-49ff-9e1f-e1eacaad5bff
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117002204 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39
.adc_ctrl_filters_wakeup_fixed.1117002204
Directory /workspace/39.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/39.adc_ctrl_fsm_reset.3419145279
Short name T690
Test name
Test status
Simulation time 91605323297 ps
CPU time 416.37 seconds
Started Jul 09 06:38:23 PM PDT 24
Finished Jul 09 06:45:21 PM PDT 24
Peak memory 202220 kb
Host smart-5d974dff-04e4-40f0-aa89-9aebb89e04b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419145279 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_fsm_reset.3419145279
Directory /workspace/39.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/39.adc_ctrl_lowpower_counter.2242028747
Short name T552
Test name
Test status
Simulation time 39410323135 ps
CPU time 46.05 seconds
Started Jul 09 06:38:24 PM PDT 24
Finished Jul 09 06:39:11 PM PDT 24
Peak memory 201648 kb
Host smart-56efb9b2-584e-4b37-8fc1-320c556b264f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242028747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_lowpower_counter.2242028747
Directory /workspace/39.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_poweron_counter.2021828930
Short name T439
Test name
Test status
Simulation time 3888697595 ps
CPU time 9.48 seconds
Started Jul 09 06:38:24 PM PDT 24
Finished Jul 09 06:38:34 PM PDT 24
Peak memory 201700 kb
Host smart-56d637cb-9eff-4635-858d-7a0df872b6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021828930 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_poweron_counter.2021828930
Directory /workspace/39.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/39.adc_ctrl_smoke.3594643502
Short name T606
Test name
Test status
Simulation time 5584966907 ps
CPU time 4.2 seconds
Started Jul 09 06:38:17 PM PDT 24
Finished Jul 09 06:38:24 PM PDT 24
Peak memory 201712 kb
Host smart-ecd70b94-c50d-4735-b8d4-0618c4ba5448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594643502 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_smoke.3594643502
Directory /workspace/39.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all.2474647094
Short name T709
Test name
Test status
Simulation time 141704325998 ps
CPU time 555.31 seconds
Started Jul 09 06:38:29 PM PDT 24
Finished Jul 09 06:47:45 PM PDT 24
Peak memory 202300 kb
Host smart-2d01f027-210e-4024-aad3-1a5d33438d20
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474647094 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all
.2474647094
Directory /workspace/39.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.adc_ctrl_stress_all_with_rand_reset.4153877166
Short name T754
Test name
Test status
Simulation time 70893900597 ps
CPU time 41.42 seconds
Started Jul 09 06:38:24 PM PDT 24
Finished Jul 09 06:39:06 PM PDT 24
Peak memory 210244 kb
Host smart-aaf81279-2421-470b-8a04-2a0c83ef832d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153877166 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 39.adc_ctrl_stress_all_with_rand_reset.4153877166
Directory /workspace/39.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_alert_test.3756533327
Short name T554
Test name
Test status
Simulation time 308592625 ps
CPU time 0.81 seconds
Started Jul 09 06:33:08 PM PDT 24
Finished Jul 09 06:33:20 PM PDT 24
Peak memory 201632 kb
Host smart-44918099-a014-4472-8eea-0b841bed83cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756533327 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_alert_test.3756533327
Directory /workspace/4.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.adc_ctrl_clock_gating.2857031077
Short name T774
Test name
Test status
Simulation time 390750443177 ps
CPU time 111.34 seconds
Started Jul 09 06:33:07 PM PDT 24
Finished Jul 09 06:35:10 PM PDT 24
Peak memory 201980 kb
Host smart-ab1d9981-223d-4474-9791-7b160e8ceb27
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857031077 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_clock_gati
ng.2857031077
Directory /workspace/4.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_both.269021582
Short name T84
Test name
Test status
Simulation time 174653635791 ps
CPU time 109.83 seconds
Started Jul 09 06:33:08 PM PDT 24
Finished Jul 09 06:35:09 PM PDT 24
Peak memory 201948 kb
Host smart-29a402c1-ea6a-4e86-bcd0-812f2ba1e793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269021582 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_both.269021582
Directory /workspace/4.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt.4234281696
Short name T171
Test name
Test status
Simulation time 162300142230 ps
CPU time 95.13 seconds
Started Jul 09 06:33:06 PM PDT 24
Finished Jul 09 06:34:54 PM PDT 24
Peak memory 201924 kb
Host smart-965d22a7-9058-425a-9c01-56eeac9746e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234281696 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrupt.4234281696
Directory /workspace/4.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_interrupt_fixed.3990078091
Short name T531
Test name
Test status
Simulation time 497638434182 ps
CPU time 1183.93 seconds
Started Jul 09 06:33:04 PM PDT 24
Finished Jul 09 06:53:01 PM PDT 24
Peak memory 201912 kb
Host smart-86626868-b6a7-47bc-a300-a67dbf737283
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990078091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_interrup
t_fixed.3990078091
Directory /workspace/4.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled.3673270013
Short name T175
Test name
Test status
Simulation time 326469233464 ps
CPU time 121.69 seconds
Started Jul 09 06:33:07 PM PDT 24
Finished Jul 09 06:35:21 PM PDT 24
Peak memory 201904 kb
Host smart-9b1ac625-a3ad-4902-b887-f9d5ab9d6383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673270013 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled.3673270013
Directory /workspace/4.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_polled_fixed.697453090
Short name T460
Test name
Test status
Simulation time 168456263081 ps
CPU time 183.34 seconds
Started Jul 09 06:33:07 PM PDT 24
Finished Jul 09 06:36:22 PM PDT 24
Peak memory 201884 kb
Host smart-ffb2b737-6ce7-4a0c-a32a-8e3ded7a4651
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=697453090 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_polled_fixed
.697453090
Directory /workspace/4.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup.1626676269
Short name T238
Test name
Test status
Simulation time 412920813201 ps
CPU time 864.31 seconds
Started Jul 09 06:33:06 PM PDT 24
Finished Jul 09 06:47:43 PM PDT 24
Peak memory 202008 kb
Host smart-e963dd24-64fa-4ba0-8ca4-647461fe0342
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626676269 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_filters_
wakeup.1626676269
Directory /workspace/4.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/4.adc_ctrl_filters_wakeup_fixed.2412158673
Short name T470
Test name
Test status
Simulation time 404310875111 ps
CPU time 972.75 seconds
Started Jul 09 06:33:07 PM PDT 24
Finished Jul 09 06:49:32 PM PDT 24
Peak memory 201868 kb
Host smart-c9f3ccac-ee59-438c-aa30-bf153b46d1f3
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412158673 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.
adc_ctrl_filters_wakeup_fixed.2412158673
Directory /workspace/4.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/4.adc_ctrl_fsm_reset.1247597632
Short name T488
Test name
Test status
Simulation time 96844525098 ps
CPU time 338.95 seconds
Started Jul 09 06:33:07 PM PDT 24
Finished Jul 09 06:38:58 PM PDT 24
Peak memory 202232 kb
Host smart-017d0028-e1bc-4114-a858-5b58b22af54a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247597632 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_fsm_reset.1247597632
Directory /workspace/4.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/4.adc_ctrl_lowpower_counter.2404495073
Short name T516
Test name
Test status
Simulation time 42695671661 ps
CPU time 92.68 seconds
Started Jul 09 06:33:08 PM PDT 24
Finished Jul 09 06:34:52 PM PDT 24
Peak memory 201724 kb
Host smart-70eb1e1b-5269-4e43-8c0e-6b3476c58b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404495073 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_lowpower_counter.2404495073
Directory /workspace/4.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_poweron_counter.3668215934
Short name T491
Test name
Test status
Simulation time 3315634893 ps
CPU time 7.5 seconds
Started Jul 09 06:33:15 PM PDT 24
Finished Jul 09 06:33:30 PM PDT 24
Peak memory 201716 kb
Host smart-d0c10c41-6abd-4d60-8b5a-8f32b74b5921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668215934 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_poweron_counter.3668215934
Directory /workspace/4.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/4.adc_ctrl_sec_cm.2433596601
Short name T76
Test name
Test status
Simulation time 8142189401 ps
CPU time 10.25 seconds
Started Jul 09 06:33:08 PM PDT 24
Finished Jul 09 06:33:30 PM PDT 24
Peak memory 218144 kb
Host smart-5af69f65-dcef-4da8-9156-8215a95481df
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433596601 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_sec_cm.2433596601
Directory /workspace/4.adc_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.adc_ctrl_smoke.3128621536
Short name T443
Test name
Test status
Simulation time 6052014875 ps
CPU time 15.71 seconds
Started Jul 09 06:33:05 PM PDT 24
Finished Jul 09 06:33:34 PM PDT 24
Peak memory 201720 kb
Host smart-3ed7da76-1cd6-420b-8574-bbeb46c1ee5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128621536 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_smoke.3128621536
Directory /workspace/4.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/4.adc_ctrl_stress_all.755387631
Short name T474
Test name
Test status
Simulation time 333979011419 ps
CPU time 340.04 seconds
Started Jul 09 06:33:05 PM PDT 24
Finished Jul 09 06:38:59 PM PDT 24
Peak memory 201988 kb
Host smart-f1363473-19e3-42df-b247-d6ba0dcc7e0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755387631 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress
_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.adc_ctrl_stress_all.755387631
Directory /workspace/4.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_alert_test.272928038
Short name T688
Test name
Test status
Simulation time 340819025 ps
CPU time 0.81 seconds
Started Jul 09 06:38:51 PM PDT 24
Finished Jul 09 06:38:53 PM PDT 24
Peak memory 201648 kb
Host smart-f3c31fa2-9472-4e3e-b664-1d4aa779b114
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272928038 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_alert_test.272928038
Directory /workspace/40.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.adc_ctrl_clock_gating.3479659687
Short name T184
Test name
Test status
Simulation time 347339126844 ps
CPU time 126.52 seconds
Started Jul 09 06:38:38 PM PDT 24
Finished Jul 09 06:40:45 PM PDT 24
Peak memory 202148 kb
Host smart-4b9d8c56-9fde-45a9-998e-595dc9d063bd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479659687 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_clock_gat
ing.3479659687
Directory /workspace/40.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_both.4230623762
Short name T749
Test name
Test status
Simulation time 402310613539 ps
CPU time 923.56 seconds
Started Jul 09 06:38:44 PM PDT 24
Finished Jul 09 06:54:09 PM PDT 24
Peak memory 201768 kb
Host smart-b75701ad-c89d-4a6e-8df5-993820600b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230623762 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_both.4230623762
Directory /workspace/40.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt.2642923975
Short name T280
Test name
Test status
Simulation time 493787323455 ps
CPU time 552.83 seconds
Started Jul 09 06:38:32 PM PDT 24
Finished Jul 09 06:47:46 PM PDT 24
Peak memory 201856 kb
Host smart-72c752a6-7615-4145-a304-d51ff33cf843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642923975 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interrupt.2642923975
Directory /workspace/40.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_interrupt_fixed.1812323299
Short name T493
Test name
Test status
Simulation time 485592843102 ps
CPU time 264.48 seconds
Started Jul 09 06:38:38 PM PDT 24
Finished Jul 09 06:43:03 PM PDT 24
Peak memory 201888 kb
Host smart-a68545c0-012c-497a-9481-b04f2284bc52
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812323299 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_interru
pt_fixed.1812323299
Directory /workspace/40.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled.929358143
Short name T23
Test name
Test status
Simulation time 494493381221 ps
CPU time 1043.03 seconds
Started Jul 09 06:38:32 PM PDT 24
Finished Jul 09 06:55:57 PM PDT 24
Peak memory 202012 kb
Host smart-c6afbf44-35b4-4ee3-a9fe-77cafbef3d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929358143 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled.929358143
Directory /workspace/40.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_polled_fixed.2777188736
Short name T384
Test name
Test status
Simulation time 164498147902 ps
CPU time 38.58 seconds
Started Jul 09 06:38:33 PM PDT 24
Finished Jul 09 06:39:13 PM PDT 24
Peak memory 201908 kb
Host smart-4dcadacc-c34b-46a9-b9f2-d33c4fb23e64
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777188736 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters_polled_fix
ed.2777188736
Directory /workspace/40.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup.1105947707
Short name T556
Test name
Test status
Simulation time 405408510372 ps
CPU time 236.59 seconds
Started Jul 09 06:38:40 PM PDT 24
Finished Jul 09 06:42:38 PM PDT 24
Peak memory 201992 kb
Host smart-d6b79c34-6db9-4427-938a-a5a2bf319f2d
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105947707 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_filters
_wakeup.1105947707
Directory /workspace/40.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/40.adc_ctrl_filters_wakeup_fixed.4177512220
Short name T578
Test name
Test status
Simulation time 201658372782 ps
CPU time 420.62 seconds
Started Jul 09 06:38:39 PM PDT 24
Finished Jul 09 06:45:40 PM PDT 24
Peak memory 201912 kb
Host smart-9a478b39-aa08-4ef6-897e-b9c1bfe93192
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177512220 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40
.adc_ctrl_filters_wakeup_fixed.4177512220
Directory /workspace/40.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/40.adc_ctrl_fsm_reset.1070418356
Short name T359
Test name
Test status
Simulation time 89319501150 ps
CPU time 456.24 seconds
Started Jul 09 06:38:44 PM PDT 24
Finished Jul 09 06:46:21 PM PDT 24
Peak memory 202076 kb
Host smart-b4992a33-c5a8-4b7c-8bb6-368b0039376c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070418356 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_fsm_reset.1070418356
Directory /workspace/40.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/40.adc_ctrl_lowpower_counter.1599107627
Short name T453
Test name
Test status
Simulation time 33324373175 ps
CPU time 69.46 seconds
Started Jul 09 06:38:42 PM PDT 24
Finished Jul 09 06:39:53 PM PDT 24
Peak memory 201724 kb
Host smart-ef5930f6-bfb9-40af-ab5f-ab08cde961cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599107627 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_lowpower_counter.1599107627
Directory /workspace/40.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_poweron_counter.3198727718
Short name T386
Test name
Test status
Simulation time 4159037654 ps
CPU time 7.15 seconds
Started Jul 09 06:38:46 PM PDT 24
Finished Jul 09 06:38:54 PM PDT 24
Peak memory 201700 kb
Host smart-8a3cb1b9-c8c7-4b0c-a086-f396ee94aa58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198727718 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_poweron_counter.3198727718
Directory /workspace/40.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/40.adc_ctrl_smoke.310666435
Short name T363
Test name
Test status
Simulation time 5986962571 ps
CPU time 13.56 seconds
Started Jul 09 06:38:33 PM PDT 24
Finished Jul 09 06:38:48 PM PDT 24
Peak memory 201688 kb
Host smart-bbbf18a4-ed2d-4568-a102-b68b0c01bacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310666435 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_smoke.310666435
Directory /workspace/40.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all.3136625494
Short name T799
Test name
Test status
Simulation time 365612227940 ps
CPU time 730.13 seconds
Started Jul 09 06:38:48 PM PDT 24
Finished Jul 09 06:50:59 PM PDT 24
Peak memory 201960 kb
Host smart-df4f8a88-ac50-4396-a81b-e398c4dbc65a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136625494 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all
.3136625494
Directory /workspace/40.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.adc_ctrl_stress_all_with_rand_reset.2909874368
Short name T59
Test name
Test status
Simulation time 157799725545 ps
CPU time 92.13 seconds
Started Jul 09 06:38:43 PM PDT 24
Finished Jul 09 06:40:17 PM PDT 24
Peak memory 211372 kb
Host smart-759910f8-ca58-49d0-81e1-9e6175e50b7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909874368 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 40.adc_ctrl_stress_all_with_rand_reset.2909874368
Directory /workspace/40.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_alert_test.2303218192
Short name T402
Test name
Test status
Simulation time 354890400 ps
CPU time 0.74 seconds
Started Jul 09 06:39:02 PM PDT 24
Finished Jul 09 06:39:04 PM PDT 24
Peak memory 201656 kb
Host smart-0b2bf7de-d44f-4fbb-a3d4-865ec12e67fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303218192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_alert_test.2303218192
Directory /workspace/41.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.adc_ctrl_clock_gating.1765200474
Short name T619
Test name
Test status
Simulation time 161019119738 ps
CPU time 76.48 seconds
Started Jul 09 06:38:54 PM PDT 24
Finished Jul 09 06:40:12 PM PDT 24
Peak memory 201896 kb
Host smart-f8f40839-75cd-49fc-b6a8-6e4e84bcd45b
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765200474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_clock_gat
ing.1765200474
Directory /workspace/41.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_interrupt_fixed.4064524313
Short name T80
Test name
Test status
Simulation time 485096391960 ps
CPU time 518.54 seconds
Started Jul 09 06:38:54 PM PDT 24
Finished Jul 09 06:47:34 PM PDT 24
Peak memory 201856 kb
Host smart-81a61b5f-a81d-47ef-9958-b7a7c81cb31a
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064524313 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_interru
pt_fixed.4064524313
Directory /workspace/41.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled.2252668450
Short name T246
Test name
Test status
Simulation time 496933260783 ps
CPU time 304.74 seconds
Started Jul 09 06:38:49 PM PDT 24
Finished Jul 09 06:43:55 PM PDT 24
Peak memory 201832 kb
Host smart-a6e78f25-a434-4b3d-bd76-48b6e8d7c3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252668450 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled.2252668450
Directory /workspace/41.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_polled_fixed.2140683583
Short name T599
Test name
Test status
Simulation time 486197719547 ps
CPU time 848.58 seconds
Started Jul 09 06:38:54 PM PDT 24
Finished Jul 09 06:53:04 PM PDT 24
Peak memory 201876 kb
Host smart-1a06d4f7-a575-4bd8-8474-bcf925a48532
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140683583 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_filters_polled_fix
ed.2140683583
Directory /workspace/41.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_filters_wakeup_fixed.1000676702
Short name T390
Test name
Test status
Simulation time 397779176935 ps
CPU time 954.43 seconds
Started Jul 09 06:38:52 PM PDT 24
Finished Jul 09 06:54:48 PM PDT 24
Peak memory 201888 kb
Host smart-91137dc4-d78e-45d5-b94e-83de0fbfbc1b
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000676702 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41
.adc_ctrl_filters_wakeup_fixed.1000676702
Directory /workspace/41.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/41.adc_ctrl_fsm_reset.832183414
Short name T103
Test name
Test status
Simulation time 124235723705 ps
CPU time 412.32 seconds
Started Jul 09 06:38:59 PM PDT 24
Finished Jul 09 06:45:52 PM PDT 24
Peak memory 202216 kb
Host smart-cef90cb1-1e50-4301-bb82-b4c4983acb10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832183414 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_fsm_reset.832183414
Directory /workspace/41.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/41.adc_ctrl_lowpower_counter.1861940145
Short name T364
Test name
Test status
Simulation time 33765377469 ps
CPU time 76.13 seconds
Started Jul 09 06:38:57 PM PDT 24
Finished Jul 09 06:40:14 PM PDT 24
Peak memory 201744 kb
Host smart-af590227-6b2d-4352-b6d6-f9e21ebe1033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861940145 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_lowpower_counter.1861940145
Directory /workspace/41.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_poweron_counter.1871865267
Short name T768
Test name
Test status
Simulation time 5432912470 ps
CPU time 12.85 seconds
Started Jul 09 06:38:53 PM PDT 24
Finished Jul 09 06:39:07 PM PDT 24
Peak memory 201728 kb
Host smart-3bae3154-2a34-466e-bd5b-036c5c6e6f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871865267 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_poweron_counter.1871865267
Directory /workspace/41.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/41.adc_ctrl_smoke.1052003928
Short name T707
Test name
Test status
Simulation time 5823297718 ps
CPU time 7.83 seconds
Started Jul 09 06:38:51 PM PDT 24
Finished Jul 09 06:39:00 PM PDT 24
Peak memory 201696 kb
Host smart-a1a66893-ccdd-4a3b-b620-27ad05741c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052003928 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_smoke.1052003928
Directory /workspace/41.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all.3081570089
Short name T536
Test name
Test status
Simulation time 329807681724 ps
CPU time 187.13 seconds
Started Jul 09 06:39:02 PM PDT 24
Finished Jul 09 06:42:10 PM PDT 24
Peak memory 201928 kb
Host smart-04655394-db57-40de-8959-f2f5103385f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081570089 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all
.3081570089
Directory /workspace/41.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.adc_ctrl_stress_all_with_rand_reset.244573222
Short name T340
Test name
Test status
Simulation time 96965062701 ps
CPU time 163.21 seconds
Started Jul 09 06:39:01 PM PDT 24
Finished Jul 09 06:41:45 PM PDT 24
Peak memory 210560 kb
Host smart-22cb4b82-9879-40cc-809c-1229b248eab4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244573222 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 41.adc_ctrl_stress_all_with_rand_reset.244573222
Directory /workspace/41.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_alert_test.3589645824
Short name T394
Test name
Test status
Simulation time 532875727 ps
CPU time 0.89 seconds
Started Jul 09 06:39:13 PM PDT 24
Finished Jul 09 06:39:15 PM PDT 24
Peak memory 201636 kb
Host smart-05e62236-a176-432c-9ef0-ceb7195337a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589645824 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_alert_test.3589645824
Directory /workspace/42.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_both.3554094635
Short name T322
Test name
Test status
Simulation time 540897782768 ps
CPU time 1179.54 seconds
Started Jul 09 06:39:06 PM PDT 24
Finished Jul 09 06:58:46 PM PDT 24
Peak memory 201952 kb
Host smart-694e0a83-3fc4-4a48-950d-6620d5615262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554094635 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_both.3554094635
Directory /workspace/42.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt.910284085
Short name T262
Test name
Test status
Simulation time 501414537108 ps
CPU time 1130.8 seconds
Started Jul 09 06:38:58 PM PDT 24
Finished Jul 09 06:57:50 PM PDT 24
Peak memory 201984 kb
Host smart-5118d353-af44-4174-8743-00e15fff242c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910284085 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interrupt.910284085
Directory /workspace/42.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_interrupt_fixed.2036157774
Short name T452
Test name
Test status
Simulation time 483594597417 ps
CPU time 1098.46 seconds
Started Jul 09 06:38:59 PM PDT 24
Finished Jul 09 06:57:18 PM PDT 24
Peak memory 201864 kb
Host smart-00207aef-56f3-4a37-8ef2-a20c9fe953e3
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036157774 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_interru
pt_fixed.2036157774
Directory /workspace/42.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled.2763614775
Short name T475
Test name
Test status
Simulation time 160502796134 ps
CPU time 192.86 seconds
Started Jul 09 06:39:01 PM PDT 24
Finished Jul 09 06:42:15 PM PDT 24
Peak memory 201996 kb
Host smart-e653c2e7-3a13-4916-8b4f-ba8b1a54e971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763614775 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled.2763614775
Directory /workspace/42.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_polled_fixed.339615078
Short name T615
Test name
Test status
Simulation time 496914442883 ps
CPU time 1168.3 seconds
Started Jul 09 06:38:58 PM PDT 24
Finished Jul 09 06:58:27 PM PDT 24
Peak memory 201804 kb
Host smart-52f60266-1bfd-4566-b7e8-ba60b01ac823
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=339615078 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_polled_fixe
d.339615078
Directory /workspace/42.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup.182206185
Short name T565
Test name
Test status
Simulation time 166933499727 ps
CPU time 39.03 seconds
Started Jul 09 06:39:02 PM PDT 24
Finished Jul 09 06:39:42 PM PDT 24
Peak memory 201984 kb
Host smart-76ab646a-8392-4056-9a05-c8dda9250fdd
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182206185 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters
_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_filters_
wakeup.182206185
Directory /workspace/42.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/42.adc_ctrl_filters_wakeup_fixed.3439186883
Short name T10
Test name
Test status
Simulation time 597668632844 ps
CPU time 1286.33 seconds
Started Jul 09 06:39:01 PM PDT 24
Finished Jul 09 07:00:29 PM PDT 24
Peak memory 201860 kb
Host smart-0ad73202-c270-473f-b3a6-7db2ddd235b8
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439186883 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42
.adc_ctrl_filters_wakeup_fixed.3439186883
Directory /workspace/42.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/42.adc_ctrl_fsm_reset.2114858891
Short name T200
Test name
Test status
Simulation time 74416449958 ps
CPU time 243.72 seconds
Started Jul 09 06:39:06 PM PDT 24
Finished Jul 09 06:43:10 PM PDT 24
Peak memory 202264 kb
Host smart-3dde8398-ef26-4249-acb2-3624c004dc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114858891 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_fsm_reset.2114858891
Directory /workspace/42.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/42.adc_ctrl_lowpower_counter.382184916
Short name T667
Test name
Test status
Simulation time 23404218149 ps
CPU time 13.58 seconds
Started Jul 09 06:39:08 PM PDT 24
Finished Jul 09 06:39:22 PM PDT 24
Peak memory 201752 kb
Host smart-5f05187d-d9c3-438a-91bc-28601afbf494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382184916 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_lowpower_counter.382184916
Directory /workspace/42.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_poweron_counter.560257440
Short name T430
Test name
Test status
Simulation time 4866091480 ps
CPU time 3.51 seconds
Started Jul 09 06:39:10 PM PDT 24
Finished Jul 09 06:39:14 PM PDT 24
Peak memory 201684 kb
Host smart-03e4da45-edd5-4144-9151-8b9994cc82c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560257440 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_poweron_counter.560257440
Directory /workspace/42.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/42.adc_ctrl_smoke.2842038500
Short name T419
Test name
Test status
Simulation time 5786670967 ps
CPU time 13.03 seconds
Started Jul 09 06:39:02 PM PDT 24
Finished Jul 09 06:39:16 PM PDT 24
Peak memory 201724 kb
Host smart-81cc6372-0f54-423f-88a1-e4897a9e015b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842038500 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_smoke.2842038500
Directory /workspace/42.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all.3276895039
Short name T297
Test name
Test status
Simulation time 247710319826 ps
CPU time 147.2 seconds
Started Jul 09 06:39:07 PM PDT 24
Finished Jul 09 06:41:35 PM PDT 24
Peak memory 201864 kb
Host smart-639a19ce-4d1b-46c5-9532-aa9adeca4b1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276895039 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all
.3276895039
Directory /workspace/42.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.adc_ctrl_stress_all_with_rand_reset.2103842734
Short name T595
Test name
Test status
Simulation time 73639464680 ps
CPU time 168.66 seconds
Started Jul 09 06:39:06 PM PDT 24
Finished Jul 09 06:41:56 PM PDT 24
Peak memory 210272 kb
Host smart-ea0f4010-ae56-4031-a264-172b0cf01da7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103842734 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 42.adc_ctrl_stress_all_with_rand_reset.2103842734
Directory /workspace/42.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_alert_test.4185903563
Short name T373
Test name
Test status
Simulation time 329995557 ps
CPU time 0.76 seconds
Started Jul 09 06:39:28 PM PDT 24
Finished Jul 09 06:39:30 PM PDT 24
Peak memory 201636 kb
Host smart-3d860cb4-a1e8-467a-bfca-22d552be0ee8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185903563 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_alert_test.4185903563
Directory /workspace/43.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.adc_ctrl_clock_gating.3068539853
Short name T275
Test name
Test status
Simulation time 338518915374 ps
CPU time 377.1 seconds
Started Jul 09 06:39:21 PM PDT 24
Finished Jul 09 06:45:40 PM PDT 24
Peak memory 201920 kb
Host smart-c1980f4a-884d-4dc4-999c-d4190573f327
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068539853 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_clock_gat
ing.3068539853
Directory /workspace/43.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_both.3355158624
Short name T324
Test name
Test status
Simulation time 534445784703 ps
CPU time 1309.58 seconds
Started Jul 09 06:39:21 PM PDT 24
Finished Jul 09 07:01:12 PM PDT 24
Peak memory 201896 kb
Host smart-8a9e20b2-e200-4bd7-85ad-d6f82dda957a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355158624 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_both.3355158624
Directory /workspace/43.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt.3001259087
Short name T137
Test name
Test status
Simulation time 163351542337 ps
CPU time 369.8 seconds
Started Jul 09 06:39:19 PM PDT 24
Finished Jul 09 06:45:30 PM PDT 24
Peak memory 201924 kb
Host smart-2ab93b89-0367-41c1-928f-3981f62a0770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001259087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interrupt.3001259087
Directory /workspace/43.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_interrupt_fixed.1167992566
Short name T483
Test name
Test status
Simulation time 167348101039 ps
CPU time 97.78 seconds
Started Jul 09 06:39:22 PM PDT 24
Finished Jul 09 06:41:01 PM PDT 24
Peak memory 201884 kb
Host smart-8ad4857c-d103-4670-b7bf-5d4605c6fbb5
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167992566 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_interru
pt_fixed.1167992566
Directory /workspace/43.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled.415648535
Short name T339
Test name
Test status
Simulation time 334559556660 ps
CPU time 236.21 seconds
Started Jul 09 06:39:12 PM PDT 24
Finished Jul 09 06:43:10 PM PDT 24
Peak memory 201936 kb
Host smart-442cd818-e8ba-490b-816f-ce6cffebec25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415648535 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled.415648535
Directory /workspace/43.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_polled_fixed.457066040
Short name T622
Test name
Test status
Simulation time 160782279663 ps
CPU time 95.63 seconds
Started Jul 09 06:39:14 PM PDT 24
Finished Jul 09 06:40:51 PM PDT 24
Peak memory 201964 kb
Host smart-c5178f06-bf97-484e-8dbf-d558b0d146e8
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=457066040 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters_polled_fixe
d.457066040
Directory /workspace/43.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup.4246878447
Short name T543
Test name
Test status
Simulation time 207202113517 ps
CPU time 243.24 seconds
Started Jul 09 06:39:22 PM PDT 24
Finished Jul 09 06:43:27 PM PDT 24
Peak memory 201984 kb
Host smart-e86a8873-aedf-4003-8895-7216a659c96c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246878447 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_filters
_wakeup.4246878447
Directory /workspace/43.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/43.adc_ctrl_filters_wakeup_fixed.714195135
Short name T784
Test name
Test status
Simulation time 198591272614 ps
CPU time 33.37 seconds
Started Jul 09 06:39:22 PM PDT 24
Finished Jul 09 06:39:57 PM PDT 24
Peak memory 201956 kb
Host smart-9dd89226-b660-4a00-aef0-35eb1d5c2e81
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714195135 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.
adc_ctrl_filters_wakeup_fixed.714195135
Directory /workspace/43.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/43.adc_ctrl_fsm_reset.2753332336
Short name T193
Test name
Test status
Simulation time 73862704326 ps
CPU time 365.02 seconds
Started Jul 09 06:39:22 PM PDT 24
Finished Jul 09 06:45:28 PM PDT 24
Peak memory 202256 kb
Host smart-d1cb909c-49fd-4261-ab05-178b30639ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753332336 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_fsm_reset.2753332336
Directory /workspace/43.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/43.adc_ctrl_lowpower_counter.3670716945
Short name T620
Test name
Test status
Simulation time 46693443077 ps
CPU time 28.08 seconds
Started Jul 09 06:39:23 PM PDT 24
Finished Jul 09 06:39:52 PM PDT 24
Peak memory 201624 kb
Host smart-6d02b38b-092b-4d7e-a61f-a3c146fd1398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670716945 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_lowpower_counter.3670716945
Directory /workspace/43.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_poweron_counter.3200643007
Short name T739
Test name
Test status
Simulation time 3210463848 ps
CPU time 4.22 seconds
Started Jul 09 06:39:23 PM PDT 24
Finished Jul 09 06:39:28 PM PDT 24
Peak memory 201692 kb
Host smart-763eb2f4-8564-44b0-a4d9-08e5a26346bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200643007 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_poweron_counter.3200643007
Directory /workspace/43.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/43.adc_ctrl_smoke.78877008
Short name T383
Test name
Test status
Simulation time 6168141302 ps
CPU time 8.48 seconds
Started Jul 09 06:39:14 PM PDT 24
Finished Jul 09 06:39:24 PM PDT 24
Peak memory 201692 kb
Host smart-659ddabd-c19a-47b2-9035-98e9195411ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78877008 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_smoke.78877008
Directory /workspace/43.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all.2687514325
Short name T237
Test name
Test status
Simulation time 339402161305 ps
CPU time 126.23 seconds
Started Jul 09 06:39:21 PM PDT 24
Finished Jul 09 06:41:29 PM PDT 24
Peak memory 201976 kb
Host smart-da872a82-8edc-469e-a7da-8137bb6bc4be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687514325 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all
.2687514325
Directory /workspace/43.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.adc_ctrl_stress_all_with_rand_reset.2552259592
Short name T21
Test name
Test status
Simulation time 196289098470 ps
CPU time 37.41 seconds
Started Jul 09 06:39:23 PM PDT 24
Finished Jul 09 06:40:02 PM PDT 24
Peak memory 210172 kb
Host smart-10f5b40f-edb7-49bc-a621-1cfb2b5bd343
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552259592 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 43.adc_ctrl_stress_all_with_rand_reset.2552259592
Directory /workspace/43.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_alert_test.1467510495
Short name T11
Test name
Test status
Simulation time 337434254 ps
CPU time 1.33 seconds
Started Jul 09 06:39:31 PM PDT 24
Finished Jul 09 06:39:34 PM PDT 24
Peak memory 201592 kb
Host smart-fd5f763b-cb5a-4797-be45-8d239a9aca6a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467510495 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_alert_test.1467510495
Directory /workspace/44.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt.897508416
Short name T261
Test name
Test status
Simulation time 334520080100 ps
CPU time 96.12 seconds
Started Jul 09 06:39:28 PM PDT 24
Finished Jul 09 06:41:06 PM PDT 24
Peak memory 201956 kb
Host smart-254a3247-219c-4fb8-ba23-3e33f5f2037d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897508416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrupt.897508416
Directory /workspace/44.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_interrupt_fixed.240527757
Short name T444
Test name
Test status
Simulation time 330504001134 ps
CPU time 376.49 seconds
Started Jul 09 06:39:31 PM PDT 24
Finished Jul 09 06:45:49 PM PDT 24
Peak memory 201856 kb
Host smart-65df65ec-e5f6-4742-bfd2-0a9753b916b7
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=240527757 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_interrup
t_fixed.240527757
Directory /workspace/44.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled.597656484
Short name T551
Test name
Test status
Simulation time 166210949174 ps
CPU time 75.75 seconds
Started Jul 09 06:39:27 PM PDT 24
Finished Jul 09 06:40:43 PM PDT 24
Peak memory 201976 kb
Host smart-01e6b2b4-ad1c-4cde-a7a1-452d31d7dc4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597656484 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled.597656484
Directory /workspace/44.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_polled_fixed.2280769751
Short name T445
Test name
Test status
Simulation time 323573793023 ps
CPU time 355.38 seconds
Started Jul 09 06:39:25 PM PDT 24
Finished Jul 09 06:45:21 PM PDT 24
Peak memory 201876 kb
Host smart-234d1557-eb5b-48bb-890a-c1215bed012b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280769751 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_filters_polled_fix
ed.2280769751
Directory /workspace/44.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_filters_wakeup_fixed.2217240165
Short name T648
Test name
Test status
Simulation time 425475953429 ps
CPU time 281.14 seconds
Started Jul 09 06:39:27 PM PDT 24
Finished Jul 09 06:44:09 PM PDT 24
Peak memory 201876 kb
Host smart-1eb8563c-cb8a-4b8b-8ade-244e9f58877c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217240165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44
.adc_ctrl_filters_wakeup_fixed.2217240165
Directory /workspace/44.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/44.adc_ctrl_fsm_reset.4118305804
Short name T358
Test name
Test status
Simulation time 88604235916 ps
CPU time 344.57 seconds
Started Jul 09 06:39:32 PM PDT 24
Finished Jul 09 06:45:18 PM PDT 24
Peak memory 202308 kb
Host smart-8b9c75b2-24e0-4d9a-8a1d-34716e0c8cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118305804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_fsm_reset.4118305804
Directory /workspace/44.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/44.adc_ctrl_lowpower_counter.4202418591
Short name T471
Test name
Test status
Simulation time 45293515296 ps
CPU time 67.02 seconds
Started Jul 09 06:39:31 PM PDT 24
Finished Jul 09 06:40:39 PM PDT 24
Peak memory 201728 kb
Host smart-8d881442-054c-4862-9eb3-efc84e17b7ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202418591 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_lowpower_counter.4202418591
Directory /workspace/44.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_poweron_counter.283241629
Short name T86
Test name
Test status
Simulation time 3316665240 ps
CPU time 1.78 seconds
Started Jul 09 06:39:35 PM PDT 24
Finished Jul 09 06:39:38 PM PDT 24
Peak memory 201736 kb
Host smart-a1f7c0e1-7980-4984-b830-9f8adf761b4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283241629 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_poweron_counter.283241629
Directory /workspace/44.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/44.adc_ctrl_smoke.2838471423
Short name T737
Test name
Test status
Simulation time 6115061260 ps
CPU time 4.09 seconds
Started Jul 09 06:39:28 PM PDT 24
Finished Jul 09 06:39:33 PM PDT 24
Peak memory 201704 kb
Host smart-02829755-cbdf-443b-8a50-ed6c033299f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838471423 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_smoke.2838471423
Directory /workspace/44.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all.1550444416
Short name T221
Test name
Test status
Simulation time 209104579303 ps
CPU time 121.57 seconds
Started Jul 09 06:39:32 PM PDT 24
Finished Jul 09 06:41:35 PM PDT 24
Peak memory 201880 kb
Host smart-5fa5daa2-de7d-4513-bd40-da6916bbb49f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550444416 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all
.1550444416
Directory /workspace/44.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.adc_ctrl_stress_all_with_rand_reset.511946098
Short name T778
Test name
Test status
Simulation time 77292782141 ps
CPU time 23.64 seconds
Started Jul 09 06:39:30 PM PDT 24
Finished Jul 09 06:39:55 PM PDT 24
Peak memory 211160 kb
Host smart-f0b5041a-5f2f-4e01-a0b3-26223aff436f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511946098 -assert nopo
stproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera
ge/default.vdb -cm_log /dev/null -cm_name 44.adc_ctrl_stress_all_with_rand_reset.511946098
Directory /workspace/44.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_alert_test.3329703043
Short name T637
Test name
Test status
Simulation time 356515005 ps
CPU time 1.34 seconds
Started Jul 09 06:39:50 PM PDT 24
Finished Jul 09 06:39:52 PM PDT 24
Peak memory 201684 kb
Host smart-e18cb2ed-0b22-42e9-9d2b-5d42ec4dccaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329703043 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_alert_test.3329703043
Directory /workspace/45.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.adc_ctrl_clock_gating.2816751769
Short name T755
Test name
Test status
Simulation time 546203239792 ps
CPU time 119.59 seconds
Started Jul 09 06:39:38 PM PDT 24
Finished Jul 09 06:41:39 PM PDT 24
Peak memory 201984 kb
Host smart-9af322d1-0995-41f4-b105-61dbd03e1d4c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816751769 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_clock_gat
ing.2816751769
Directory /workspace/45.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_both.1993762171
Short name T292
Test name
Test status
Simulation time 496861400201 ps
CPU time 233.71 seconds
Started Jul 09 06:39:41 PM PDT 24
Finished Jul 09 06:43:35 PM PDT 24
Peak memory 201992 kb
Host smart-b6643bd9-b602-4a55-9bd8-23c3a81ddfe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993762171 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_both.1993762171
Directory /workspace/45.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt.754622216
Short name T459
Test name
Test status
Simulation time 160862854438 ps
CPU time 355 seconds
Started Jul 09 06:39:37 PM PDT 24
Finished Jul 09 06:45:34 PM PDT 24
Peak memory 201940 kb
Host smart-9d0acec1-9c22-40b6-9b9a-9d631da525e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754622216 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interrupt.754622216
Directory /workspace/45.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_interrupt_fixed.3780223470
Short name T703
Test name
Test status
Simulation time 162443671879 ps
CPU time 57.69 seconds
Started Jul 09 06:39:37 PM PDT 24
Finished Jul 09 06:40:37 PM PDT 24
Peak memory 201924 kb
Host smart-7de7c848-dfe3-4549-ab18-58d8f1dcbe1c
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780223470 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_interru
pt_fixed.3780223470
Directory /workspace/45.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled.1809213933
Short name T315
Test name
Test status
Simulation time 160976108901 ps
CPU time 89.71 seconds
Started Jul 09 06:39:36 PM PDT 24
Finished Jul 09 06:41:07 PM PDT 24
Peak memory 201928 kb
Host smart-226ae12c-b135-47fd-89db-2f2dafb56260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809213933 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled.1809213933
Directory /workspace/45.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_polled_fixed.1192062979
Short name T726
Test name
Test status
Simulation time 498182682029 ps
CPU time 102.49 seconds
Started Jul 09 06:39:38 PM PDT 24
Finished Jul 09 06:41:22 PM PDT 24
Peak memory 201828 kb
Host smart-7bf70784-67e6-4567-bb48-0a3d0d67f0af
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192062979 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters_polled_fix
ed.1192062979
Directory /workspace/45.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup.1350031161
Short name T345
Test name
Test status
Simulation time 173187360352 ps
CPU time 396.57 seconds
Started Jul 09 06:39:39 PM PDT 24
Finished Jul 09 06:46:17 PM PDT 24
Peak memory 201884 kb
Host smart-f9330c9c-e834-4ff8-9beb-f76237c958ec
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350031161 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_filters
_wakeup.1350031161
Directory /workspace/45.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/45.adc_ctrl_filters_wakeup_fixed.3265983815
Short name T406
Test name
Test status
Simulation time 205584066545 ps
CPU time 460.79 seconds
Started Jul 09 06:39:38 PM PDT 24
Finished Jul 09 06:47:21 PM PDT 24
Peak memory 201900 kb
Host smart-cb8ac80d-6bea-43d1-be29-c56d6202e03e
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265983815 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45
.adc_ctrl_filters_wakeup_fixed.3265983815
Directory /workspace/45.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/45.adc_ctrl_fsm_reset.4171113915
Short name T679
Test name
Test status
Simulation time 127099043943 ps
CPU time 507.85 seconds
Started Jul 09 06:39:42 PM PDT 24
Finished Jul 09 06:48:11 PM PDT 24
Peak memory 202232 kb
Host smart-f776af9b-7e6b-4676-b3a8-7d009fe02f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171113915 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_fsm_reset.4171113915
Directory /workspace/45.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/45.adc_ctrl_lowpower_counter.464395801
Short name T508
Test name
Test status
Simulation time 30669471968 ps
CPU time 62.83 seconds
Started Jul 09 06:39:41 PM PDT 24
Finished Jul 09 06:40:45 PM PDT 24
Peak memory 201676 kb
Host smart-7494d8c2-8f2e-4dfd-8a11-2f29cdae9183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464395801 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_lowpower_counter.464395801
Directory /workspace/45.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_poweron_counter.1186817047
Short name T438
Test name
Test status
Simulation time 3451665642 ps
CPU time 4.72 seconds
Started Jul 09 06:39:42 PM PDT 24
Finished Jul 09 06:39:48 PM PDT 24
Peak memory 201624 kb
Host smart-45485036-635b-44c8-8cb0-dc182f42d276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186817047 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_poweron_counter.1186817047
Directory /workspace/45.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/45.adc_ctrl_smoke.3902130378
Short name T736
Test name
Test status
Simulation time 5625077707 ps
CPU time 7.25 seconds
Started Jul 09 06:39:37 PM PDT 24
Finished Jul 09 06:39:46 PM PDT 24
Peak memory 201732 kb
Host smart-ec847a00-38af-418a-b976-728eec77c622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902130378 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_smoke.3902130378
Directory /workspace/45.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all.1687020868
Short name T283
Test name
Test status
Simulation time 332054228237 ps
CPU time 759.12 seconds
Started Jul 09 06:39:47 PM PDT 24
Finished Jul 09 06:52:27 PM PDT 24
Peak memory 201928 kb
Host smart-3598988b-539c-47b2-ac99-0f26c564f4ad
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687020868 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all
.1687020868
Directory /workspace/45.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.adc_ctrl_stress_all_with_rand_reset.3472234
Short name T39
Test name
Test status
Simulation time 54021245487 ps
CPU time 104.42 seconds
Started Jul 09 06:39:42 PM PDT 24
Finished Jul 09 06:41:28 PM PDT 24
Peak memory 210204 kb
Host smart-dababb1a-5317-45c6-8a87-3f80e6dea3de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472234 -assert nopost
proc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage
/default.vdb -cm_log /dev/null -cm_name 45.adc_ctrl_stress_all_with_rand_reset.3472234
Directory /workspace/45.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_alert_test.1959768568
Short name T426
Test name
Test status
Simulation time 533042912 ps
CPU time 0.96 seconds
Started Jul 09 06:39:57 PM PDT 24
Finished Jul 09 06:40:00 PM PDT 24
Peak memory 201628 kb
Host smart-72168889-1eab-4665-a612-100c8df6941b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959768568 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_alert_test.1959768568
Directory /workspace/46.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt.1845308805
Short name T40
Test name
Test status
Simulation time 322702596119 ps
CPU time 375.4 seconds
Started Jul 09 06:39:47 PM PDT 24
Finished Jul 09 06:46:03 PM PDT 24
Peak memory 201988 kb
Host smart-c91ceba1-4487-4f75-bba2-e594f125e428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845308805 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interrupt.1845308805
Directory /workspace/46.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_interrupt_fixed.1906305998
Short name T623
Test name
Test status
Simulation time 163036337376 ps
CPU time 341.12 seconds
Started Jul 09 06:39:51 PM PDT 24
Finished Jul 09 06:45:33 PM PDT 24
Peak memory 201928 kb
Host smart-1132ba13-f6fd-4bb6-88a1-f70cb8adf99d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906305998 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_interru
pt_fixed.1906305998
Directory /workspace/46.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled.221952545
Short name T169
Test name
Test status
Simulation time 488566626737 ps
CPU time 1070.81 seconds
Started Jul 09 06:39:48 PM PDT 24
Finished Jul 09 06:57:39 PM PDT 24
Peak memory 201952 kb
Host smart-33a03293-c4d6-40e5-be31-2693a6f8dbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221952545 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled.221952545
Directory /workspace/46.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_polled_fixed.1593796384
Short name T761
Test name
Test status
Simulation time 493009996229 ps
CPU time 266.16 seconds
Started Jul 09 06:39:46 PM PDT 24
Finished Jul 09 06:44:13 PM PDT 24
Peak memory 201896 kb
Host smart-8662e1f5-bc68-4095-92bd-99fc03e46a45
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593796384 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters_polled_fix
ed.1593796384
Directory /workspace/46.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup.3134974510
Short name T349
Test name
Test status
Simulation time 559252674004 ps
CPU time 672.38 seconds
Started Jul 09 06:39:53 PM PDT 24
Finished Jul 09 06:51:07 PM PDT 24
Peak memory 201892 kb
Host smart-c6cc87f4-5db5-41e4-8998-77eedb164e75
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134974510 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_filters
_wakeup.3134974510
Directory /workspace/46.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/46.adc_ctrl_filters_wakeup_fixed.646804284
Short name T392
Test name
Test status
Simulation time 200155898792 ps
CPU time 111.34 seconds
Started Jul 09 06:39:53 PM PDT 24
Finished Jul 09 06:41:46 PM PDT 24
Peak memory 201904 kb
Host smart-0e7d53e6-0b0d-40cc-aef5-b92ae0b088ce
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=646804284 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.
adc_ctrl_filters_wakeup_fixed.646804284
Directory /workspace/46.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/46.adc_ctrl_fsm_reset.3376522465
Short name T194
Test name
Test status
Simulation time 77743497215 ps
CPU time 298.27 seconds
Started Jul 09 06:39:52 PM PDT 24
Finished Jul 09 06:44:52 PM PDT 24
Peak memory 202308 kb
Host smart-a0cb5880-c8e3-4f39-b089-0b6cee89d4bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376522465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_fsm_reset.3376522465
Directory /workspace/46.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/46.adc_ctrl_lowpower_counter.1504307971
Short name T702
Test name
Test status
Simulation time 26671277601 ps
CPU time 59.95 seconds
Started Jul 09 06:39:53 PM PDT 24
Finished Jul 09 06:40:54 PM PDT 24
Peak memory 201724 kb
Host smart-19aef6a8-4155-4e3e-8141-110f3ceefc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504307971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_lowpower_counter.1504307971
Directory /workspace/46.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_poweron_counter.2722077112
Short name T477
Test name
Test status
Simulation time 4488070766 ps
CPU time 5.64 seconds
Started Jul 09 06:39:53 PM PDT 24
Finished Jul 09 06:40:00 PM PDT 24
Peak memory 201736 kb
Host smart-9c1752f3-18a3-419f-bae7-aff58e5532c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722077112 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_poweron_counter.2722077112
Directory /workspace/46.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/46.adc_ctrl_smoke.636364087
Short name T370
Test name
Test status
Simulation time 6130632497 ps
CPU time 4.45 seconds
Started Jul 09 06:39:47 PM PDT 24
Finished Jul 09 06:39:52 PM PDT 24
Peak memory 201708 kb
Host smart-ea5ce8fc-470a-40ad-b4eb-04181dbc4e83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636364087 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_smoke.636364087
Directory /workspace/46.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/46.adc_ctrl_stress_all.2140093679
Short name T776
Test name
Test status
Simulation time 273406105967 ps
CPU time 882.72 seconds
Started Jul 09 06:39:57 PM PDT 24
Finished Jul 09 06:54:41 PM PDT 24
Peak memory 202452 kb
Host smart-671f409d-7dd5-43a2-bffa-d06251f3bbb6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140093679 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.adc_ctrl_stress_all
.2140093679
Directory /workspace/46.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.adc_ctrl_alert_test.1921291688
Short name T680
Test name
Test status
Simulation time 383933167 ps
CPU time 1.12 seconds
Started Jul 09 06:40:07 PM PDT 24
Finished Jul 09 06:40:09 PM PDT 24
Peak memory 201680 kb
Host smart-0a6919d7-af33-4aea-9117-b381519493a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921291688 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_alert_test.1921291688
Directory /workspace/47.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.adc_ctrl_clock_gating.708927896
Short name T229
Test name
Test status
Simulation time 185986364049 ps
CPU time 399.73 seconds
Started Jul 09 06:40:02 PM PDT 24
Finished Jul 09 06:46:44 PM PDT 24
Peak memory 201896 kb
Host smart-06d33338-e345-49d5-90b2-0b7f1b711246
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708927896 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_g
ating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_clock_gati
ng.708927896
Directory /workspace/47.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt.2409220843
Short name T765
Test name
Test status
Simulation time 163522892506 ps
CPU time 176.99 seconds
Started Jul 09 06:40:01 PM PDT 24
Finished Jul 09 06:43:00 PM PDT 24
Peak memory 201920 kb
Host smart-e341dbf3-e1f1-4447-85bd-99488673d723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409220843 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interrupt.2409220843
Directory /workspace/47.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_interrupt_fixed.3794409837
Short name T770
Test name
Test status
Simulation time 497307327013 ps
CPU time 1120.74 seconds
Started Jul 09 06:40:02 PM PDT 24
Finished Jul 09 06:58:44 PM PDT 24
Peak memory 201924 kb
Host smart-bb23d12c-418b-410d-ab5b-47ce75deb5ce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794409837 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_interru
pt_fixed.3794409837
Directory /workspace/47.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled.524820168
Short name T588
Test name
Test status
Simulation time 164326475177 ps
CPU time 349.36 seconds
Started Jul 09 06:40:01 PM PDT 24
Finished Jul 09 06:45:52 PM PDT 24
Peak memory 201944 kb
Host smart-1839ef4e-5091-4422-8645-442441c8f0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524820168 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled.524820168
Directory /workspace/47.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_polled_fixed.2748677949
Short name T399
Test name
Test status
Simulation time 321458747384 ps
CPU time 178.01 seconds
Started Jul 09 06:39:57 PM PDT 24
Finished Jul 09 06:42:56 PM PDT 24
Peak memory 201908 kb
Host smart-0a9c92d9-4d06-43af-acc2-2ca0e1c94f88
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748677949 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters_polled_fix
ed.2748677949
Directory /workspace/47.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup.3931743599
Short name T321
Test name
Test status
Simulation time 179628408223 ps
CPU time 394.36 seconds
Started Jul 09 06:39:57 PM PDT 24
Finished Jul 09 06:46:33 PM PDT 24
Peak memory 202192 kb
Host smart-5af94d1c-eab5-4999-801c-3e21966e2409
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931743599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_filters
_wakeup.3931743599
Directory /workspace/47.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/47.adc_ctrl_filters_wakeup_fixed.2525817672
Short name T379
Test name
Test status
Simulation time 414768279072 ps
CPU time 949.33 seconds
Started Jul 09 06:40:04 PM PDT 24
Finished Jul 09 06:55:55 PM PDT 24
Peak memory 201820 kb
Host smart-c1bd7010-a2dd-4d3f-8593-e0a9855c65d9
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525817672 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47
.adc_ctrl_filters_wakeup_fixed.2525817672
Directory /workspace/47.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/47.adc_ctrl_fsm_reset.4228234587
Short name T790
Test name
Test status
Simulation time 132879648957 ps
CPU time 459.78 seconds
Started Jul 09 06:40:05 PM PDT 24
Finished Jul 09 06:47:46 PM PDT 24
Peak memory 202140 kb
Host smart-b2433136-7eec-40ed-8086-3ac8419db2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228234587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_fsm_reset.4228234587
Directory /workspace/47.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/47.adc_ctrl_lowpower_counter.1085280587
Short name T367
Test name
Test status
Simulation time 37988157265 ps
CPU time 77.92 seconds
Started Jul 09 06:40:05 PM PDT 24
Finished Jul 09 06:41:24 PM PDT 24
Peak memory 201724 kb
Host smart-eb62b69b-4cba-4f08-a4a0-831b558a6b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085280587 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_lowpower_counter.1085280587
Directory /workspace/47.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_poweron_counter.1439742658
Short name T400
Test name
Test status
Simulation time 4295521666 ps
CPU time 3.46 seconds
Started Jul 09 06:40:01 PM PDT 24
Finished Jul 09 06:40:06 PM PDT 24
Peak memory 201748 kb
Host smart-c948082e-88ed-4640-8d10-de0a22ef988c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439742658 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_poweron_counter.1439742658
Directory /workspace/47.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/47.adc_ctrl_smoke.3096142968
Short name T465
Test name
Test status
Simulation time 6152487958 ps
CPU time 14.27 seconds
Started Jul 09 06:39:58 PM PDT 24
Finished Jul 09 06:40:13 PM PDT 24
Peak memory 201552 kb
Host smart-c98297e7-8491-49be-9fa0-bacf291a7046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096142968 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_smoke.3096142968
Directory /workspace/47.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/47.adc_ctrl_stress_all.92113130
Short name T535
Test name
Test status
Simulation time 216169792942 ps
CPU time 512.8 seconds
Started Jul 09 06:40:07 PM PDT 24
Finished Jul 09 06:48:41 PM PDT 24
Peak memory 201884 kb
Host smart-ddeb8d08-272b-468e-90f4-01d3e0e5958e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92113130 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stress_
all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.adc_ctrl_stress_all.92113130
Directory /workspace/47.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_alert_test.1912030767
Short name T613
Test name
Test status
Simulation time 318133018 ps
CPU time 1.07 seconds
Started Jul 09 06:40:22 PM PDT 24
Finished Jul 09 06:40:25 PM PDT 24
Peak memory 201592 kb
Host smart-a9608cc1-54e1-467d-a912-bb68bd9281e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912030767 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_alert_test.1912030767
Directory /workspace/48.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_both.1842475196
Short name T234
Test name
Test status
Simulation time 182384168328 ps
CPU time 368.08 seconds
Started Jul 09 06:40:13 PM PDT 24
Finished Jul 09 06:46:22 PM PDT 24
Peak memory 201824 kb
Host smart-5f1c75c1-0891-43af-be9a-ce4e7f05af14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842475196 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_both.1842475196
Directory /workspace/48.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt.3744561184
Short name T626
Test name
Test status
Simulation time 501134266694 ps
CPU time 551.95 seconds
Started Jul 09 06:40:08 PM PDT 24
Finished Jul 09 06:49:21 PM PDT 24
Peak memory 201980 kb
Host smart-10008e41-cce8-4656-abdb-f49753da1c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744561184 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrupt.3744561184
Directory /workspace/48.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_interrupt_fixed.108183125
Short name T572
Test name
Test status
Simulation time 169383167629 ps
CPU time 374.47 seconds
Started Jul 09 06:40:08 PM PDT 24
Finished Jul 09 06:46:23 PM PDT 24
Peak memory 201868 kb
Host smart-38be32dc-3579-42e5-92c3-a1edeeff0993
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=108183125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_interrup
t_fixed.108183125
Directory /workspace/48.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled.1300051291
Short name T143
Test name
Test status
Simulation time 499716177589 ps
CPU time 1188.26 seconds
Started Jul 09 06:42:13 PM PDT 24
Finished Jul 09 07:02:02 PM PDT 24
Peak memory 201932 kb
Host smart-4303c3ac-ad98-447a-a696-ac382bb8057a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300051291 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled.1300051291
Directory /workspace/48.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_polled_fixed.955717553
Short name T422
Test name
Test status
Simulation time 327932580552 ps
CPU time 48.67 seconds
Started Jul 09 06:40:09 PM PDT 24
Finished Jul 09 06:40:58 PM PDT 24
Peak memory 201856 kb
Host smart-de928934-4791-4d65-b6be-c0ddc72552d6
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=955717553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters_polled_fixe
d.955717553
Directory /workspace/48.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup.1773291888
Short name T309
Test name
Test status
Simulation time 356198071642 ps
CPU time 766.42 seconds
Started Jul 09 06:40:13 PM PDT 24
Finished Jul 09 06:53:00 PM PDT 24
Peak memory 201924 kb
Host smart-11d9da1e-08ee-4fa9-a78b-d001f4757ae7
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773291888 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_filters
_wakeup.1773291888
Directory /workspace/48.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/48.adc_ctrl_filters_wakeup_fixed.3079707959
Short name T747
Test name
Test status
Simulation time 406976163953 ps
CPU time 102.53 seconds
Started Jul 09 06:40:14 PM PDT 24
Finished Jul 09 06:41:59 PM PDT 24
Peak memory 201972 kb
Host smart-02f58d1a-d302-4c65-b109-4e37c12b4297
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079707959 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48
.adc_ctrl_filters_wakeup_fixed.3079707959
Directory /workspace/48.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/48.adc_ctrl_fsm_reset.1990740125
Short name T79
Test name
Test status
Simulation time 119968263597 ps
CPU time 458.41 seconds
Started Jul 09 06:40:19 PM PDT 24
Finished Jul 09 06:48:00 PM PDT 24
Peak memory 202332 kb
Host smart-af116e36-1141-43db-8983-97cef7a2d249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990740125 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_fsm_reset.1990740125
Directory /workspace/48.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/48.adc_ctrl_lowpower_counter.477883144
Short name T539
Test name
Test status
Simulation time 34733148950 ps
CPU time 20.28 seconds
Started Jul 09 06:40:19 PM PDT 24
Finished Jul 09 06:40:41 PM PDT 24
Peak memory 201684 kb
Host smart-582180bb-8c1c-4001-9dae-e798eaf7a940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477883144 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_lowpower_counter.477883144
Directory /workspace/48.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_poweron_counter.721053758
Short name T96
Test name
Test status
Simulation time 4679834824 ps
CPU time 10.56 seconds
Started Jul 09 06:40:18 PM PDT 24
Finished Jul 09 06:40:31 PM PDT 24
Peak memory 201736 kb
Host smart-c2687198-971f-4695-93da-099c08543f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721053758 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_poweron_counter.721053758
Directory /workspace/48.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/48.adc_ctrl_smoke.3040988382
Short name T134
Test name
Test status
Simulation time 5936642382 ps
CPU time 12.41 seconds
Started Jul 09 06:40:08 PM PDT 24
Finished Jul 09 06:40:21 PM PDT 24
Peak memory 201728 kb
Host smart-0ec1655b-40ad-4ca8-8c3e-24be59b166d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040988382 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_smoke.3040988382
Directory /workspace/48.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all.1319949754
Short name T766
Test name
Test status
Simulation time 192186168032 ps
CPU time 401.49 seconds
Started Jul 09 06:40:18 PM PDT 24
Finished Jul 09 06:47:02 PM PDT 24
Peak memory 201888 kb
Host smart-c96db0cb-45c0-47bf-aab5-8a6ffbcda586
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319949754 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all
.1319949754
Directory /workspace/48.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.adc_ctrl_stress_all_with_rand_reset.2847535195
Short name T156
Test name
Test status
Simulation time 95087089907 ps
CPU time 214.7 seconds
Started Jul 09 06:40:18 PM PDT 24
Finished Jul 09 06:43:55 PM PDT 24
Peak memory 218028 kb
Host smart-a18b6dfd-ad1a-4af5-b7c6-c6362d66ba59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847535195 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 48.adc_ctrl_stress_all_with_rand_reset.2847535195
Directory /workspace/48.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_alert_test.3045081245
Short name T409
Test name
Test status
Simulation time 450691602 ps
CPU time 0.79 seconds
Started Jul 09 06:40:34 PM PDT 24
Finished Jul 09 06:40:36 PM PDT 24
Peak memory 201652 kb
Host smart-2aabda10-4b4e-4082-bc62-93a7510681f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045081245 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_alert_test.3045081245
Directory /workspace/49.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.adc_ctrl_clock_gating.2839182354
Short name T264
Test name
Test status
Simulation time 168227623005 ps
CPU time 195.01 seconds
Started Jul 09 06:40:30 PM PDT 24
Finished Jul 09 06:43:47 PM PDT 24
Peak memory 201924 kb
Host smart-444bdc21-bcec-416c-b042-f3e0f471bc79
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839182354 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_clock_gat
ing.2839182354
Directory /workspace/49.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_both.1277003701
Short name T218
Test name
Test status
Simulation time 188391007865 ps
CPU time 102.16 seconds
Started Jul 09 06:40:29 PM PDT 24
Finished Jul 09 06:42:13 PM PDT 24
Peak memory 202136 kb
Host smart-748f745c-9ae1-466e-88b0-8c315fcc3dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277003701 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_both.1277003701
Directory /workspace/49.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt.4126196349
Short name T147
Test name
Test status
Simulation time 163238994507 ps
CPU time 205.32 seconds
Started Jul 09 06:40:22 PM PDT 24
Finished Jul 09 06:43:48 PM PDT 24
Peak memory 201888 kb
Host smart-42e568a2-438a-4db1-a0e4-3b71ae979254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126196349 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interrupt.4126196349
Directory /workspace/49.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_interrupt_fixed.3100678474
Short name T655
Test name
Test status
Simulation time 161202769840 ps
CPU time 177.04 seconds
Started Jul 09 06:40:23 PM PDT 24
Finished Jul 09 06:43:21 PM PDT 24
Peak memory 201840 kb
Host smart-76ec9975-14ed-4691-b1a2-8ad628c5aa36
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100678474 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_interru
pt_fixed.3100678474
Directory /workspace/49.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled.2282160009
Short name T44
Test name
Test status
Simulation time 164906517726 ps
CPU time 350.12 seconds
Started Jul 09 06:40:23 PM PDT 24
Finished Jul 09 06:46:14 PM PDT 24
Peak memory 201996 kb
Host smart-88c7c73f-8d31-446f-b1ff-ccc54e62146b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282160009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled.2282160009
Directory /workspace/49.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_polled_fixed.3841963253
Short name T466
Test name
Test status
Simulation time 330265513860 ps
CPU time 233.24 seconds
Started Jul 09 06:40:24 PM PDT 24
Finished Jul 09 06:44:18 PM PDT 24
Peak memory 201912 kb
Host smart-f15e15f7-9881-47c1-8a9b-e009988b6f52
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841963253 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters_polled_fix
ed.3841963253
Directory /workspace/49.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup.4185992206
Short name T628
Test name
Test status
Simulation time 192580999591 ps
CPU time 395.35 seconds
Started Jul 09 06:40:23 PM PDT 24
Finished Jul 09 06:46:59 PM PDT 24
Peak memory 201976 kb
Host smart-478dbc9c-8d60-4700-a14e-1fdad82cf7af
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185992206 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_filters
_wakeup.4185992206
Directory /workspace/49.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/49.adc_ctrl_filters_wakeup_fixed.382085406
Short name T410
Test name
Test status
Simulation time 207903892731 ps
CPU time 511.9 seconds
Started Jul 09 06:40:27 PM PDT 24
Finished Jul 09 06:49:00 PM PDT 24
Peak memory 201728 kb
Host smart-c8a3d50e-d1bc-4adb-b871-77ff3d5ee6fb
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382085406 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ
=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.
adc_ctrl_filters_wakeup_fixed.382085406
Directory /workspace/49.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/49.adc_ctrl_fsm_reset.1095669735
Short name T195
Test name
Test status
Simulation time 121911733122 ps
CPU time 496.6 seconds
Started Jul 09 06:40:28 PM PDT 24
Finished Jul 09 06:48:47 PM PDT 24
Peak memory 202440 kb
Host smart-d21d6519-6e9d-499f-b11b-03ce288954d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095669735 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_fsm_reset.1095669735
Directory /workspace/49.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/49.adc_ctrl_lowpower_counter.3548442407
Short name T513
Test name
Test status
Simulation time 42134999488 ps
CPU time 28.13 seconds
Started Jul 09 06:40:27 PM PDT 24
Finished Jul 09 06:40:56 PM PDT 24
Peak memory 201676 kb
Host smart-40828fde-7e5e-4c94-b8bd-d4b4ff65663d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548442407 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_lowpower_counter.3548442407
Directory /workspace/49.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_poweron_counter.3091252961
Short name T387
Test name
Test status
Simulation time 3166115771 ps
CPU time 2.71 seconds
Started Jul 09 06:40:27 PM PDT 24
Finished Jul 09 06:40:32 PM PDT 24
Peak memory 201628 kb
Host smart-5c47821f-2999-403c-bc18-e0e89ffea605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091252961 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_poweron_counter.3091252961
Directory /workspace/49.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/49.adc_ctrl_smoke.3784787465
Short name T418
Test name
Test status
Simulation time 5830860772 ps
CPU time 3.95 seconds
Started Jul 09 06:40:23 PM PDT 24
Finished Jul 09 06:40:28 PM PDT 24
Peak memory 201732 kb
Host smart-978feb4a-8309-480d-ba89-aaf8e72320f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3784787465 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_smoke.3784787465
Directory /workspace/49.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/49.adc_ctrl_stress_all.2526400009
Short name T52
Test name
Test status
Simulation time 93783590102 ps
CPU time 340.32 seconds
Started Jul 09 06:40:30 PM PDT 24
Finished Jul 09 06:46:12 PM PDT 24
Peak memory 202308 kb
Host smart-1b7b5cdd-19b3-46a9-a46e-5702d82aef75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526400009 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.adc_ctrl_stress_all
.2526400009
Directory /workspace/49.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.adc_ctrl_alert_test.484644487
Short name T534
Test name
Test status
Simulation time 533266832 ps
CPU time 1.08 seconds
Started Jul 09 06:33:10 PM PDT 24
Finished Jul 09 06:33:22 PM PDT 24
Peak memory 201692 kb
Host smart-25abd117-1dba-4d31-b00a-db2fc76c2431
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484644487 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_alert_test.484644487
Directory /workspace/5.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.adc_ctrl_clock_gating.4026143361
Short name T795
Test name
Test status
Simulation time 159984839560 ps
CPU time 80.27 seconds
Started Jul 09 06:33:11 PM PDT 24
Finished Jul 09 06:34:41 PM PDT 24
Peak memory 201996 kb
Host smart-62c3b182-b254-4378-8f5a-b8ca8aacbc6a
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026143361 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_clock_gati
ng.4026143361
Directory /workspace/5.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_both.2508952244
Short name T226
Test name
Test status
Simulation time 188333913557 ps
CPU time 111.23 seconds
Started Jul 09 06:33:13 PM PDT 24
Finished Jul 09 06:35:13 PM PDT 24
Peak memory 201956 kb
Host smart-decbe530-ca6c-4046-9236-492927ebc9ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508952244 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_both.2508952244
Directory /workspace/5.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_interrupt_fixed.2730664549
Short name T154
Test name
Test status
Simulation time 490072295741 ps
CPU time 259.86 seconds
Started Jul 09 06:33:11 PM PDT 24
Finished Jul 09 06:37:41 PM PDT 24
Peak memory 201876 kb
Host smart-5ba85933-3507-44dc-a352-463e5e1f0ba0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730664549 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_interrup
t_fixed.2730664549
Directory /workspace/5.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled.2155908202
Short name T523
Test name
Test status
Simulation time 330800295989 ps
CPU time 381.53 seconds
Started Jul 09 06:33:07 PM PDT 24
Finished Jul 09 06:39:41 PM PDT 24
Peak memory 201992 kb
Host smart-7801e570-53b9-4d90-bf8a-2306b04a04d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155908202 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled.2155908202
Directory /workspace/5.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_polled_fixed.3090209292
Short name T674
Test name
Test status
Simulation time 333875081189 ps
CPU time 201.39 seconds
Started Jul 09 06:33:12 PM PDT 24
Finished Jul 09 06:36:43 PM PDT 24
Peak memory 201860 kb
Host smart-63ef0ea2-a120-441c-940f-e0565d01cabc
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090209292 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_polled_fixe
d.3090209292
Directory /workspace/5.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup.1928239034
Short name T698
Test name
Test status
Simulation time 164273917278 ps
CPU time 186.58 seconds
Started Jul 09 06:33:10 PM PDT 24
Finished Jul 09 06:36:28 PM PDT 24
Peak memory 201928 kb
Host smart-112e13bc-fbd9-4fd6-b01b-97654eb4e558
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928239034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_filters_
wakeup.1928239034
Directory /workspace/5.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/5.adc_ctrl_filters_wakeup_fixed.1734228913
Short name T533
Test name
Test status
Simulation time 200571582089 ps
CPU time 239.1 seconds
Started Jul 09 06:33:11 PM PDT 24
Finished Jul 09 06:37:21 PM PDT 24
Peak memory 201856 kb
Host smart-7383ccfb-694d-49a4-a9cf-141f67b9fcf7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734228913 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.
adc_ctrl_filters_wakeup_fixed.1734228913
Directory /workspace/5.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/5.adc_ctrl_fsm_reset.3995376605
Short name T583
Test name
Test status
Simulation time 108112741122 ps
CPU time 515.32 seconds
Started Jul 09 06:33:17 PM PDT 24
Finished Jul 09 06:41:59 PM PDT 24
Peak memory 202292 kb
Host smart-94c8d6b4-79e3-4f89-ae23-2708899f7954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995376605 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_fsm_reset.3995376605
Directory /workspace/5.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/5.adc_ctrl_lowpower_counter.1253327921
Short name T791
Test name
Test status
Simulation time 30909009499 ps
CPU time 37.2 seconds
Started Jul 09 06:33:10 PM PDT 24
Finished Jul 09 06:33:58 PM PDT 24
Peak memory 201688 kb
Host smart-d302d474-a586-4ae2-a0f8-b15d75d47c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253327921 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_lowpower_counter.1253327921
Directory /workspace/5.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_poweron_counter.63200093
Short name T772
Test name
Test status
Simulation time 4672354920 ps
CPU time 3.56 seconds
Started Jul 09 06:33:11 PM PDT 24
Finished Jul 09 06:33:25 PM PDT 24
Peak memory 201652 kb
Host smart-a8488646-dfd6-462b-b646-6d44af0c837c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63200093 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_poweron_counter.63200093
Directory /workspace/5.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/5.adc_ctrl_smoke.1140964520
Short name T463
Test name
Test status
Simulation time 6115607984 ps
CPU time 7.88 seconds
Started Jul 09 06:33:06 PM PDT 24
Finished Jul 09 06:33:26 PM PDT 24
Peak memory 201900 kb
Host smart-a68f359e-870f-427f-9a0a-ea8265c4735e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140964520 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_smoke.1140964520
Directory /workspace/5.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/5.adc_ctrl_stress_all.2265511442
Short name T296
Test name
Test status
Simulation time 179221332909 ps
CPU time 368.87 seconds
Started Jul 09 06:33:10 PM PDT 24
Finished Jul 09 06:39:30 PM PDT 24
Peak memory 201944 kb
Host smart-134e1a67-3172-46d9-a823-c3c6389180b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265511442 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.adc_ctrl_stress_all.
2265511442
Directory /workspace/5.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_alert_test.1146727497
Short name T72
Test name
Test status
Simulation time 514939830 ps
CPU time 1.83 seconds
Started Jul 09 06:33:36 PM PDT 24
Finished Jul 09 06:33:40 PM PDT 24
Peak memory 201660 kb
Host smart-9c870463-c22b-4437-ae6f-3a1211e442e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146727497 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_alert_test.1146727497
Directory /workspace/6.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.adc_ctrl_clock_gating.1841997187
Short name T586
Test name
Test status
Simulation time 180883593404 ps
CPU time 111.95 seconds
Started Jul 09 06:33:15 PM PDT 24
Finished Jul 09 06:35:15 PM PDT 24
Peak memory 201968 kb
Host smart-71eb1cb1-8760-4d9e-bb13-f335350604a5
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841997187 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_clock_gati
ng.1841997187
Directory /workspace/6.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_both.1524726804
Short name T182
Test name
Test status
Simulation time 574009868736 ps
CPU time 352.27 seconds
Started Jul 09 06:33:15 PM PDT 24
Finished Jul 09 06:39:15 PM PDT 24
Peak memory 201948 kb
Host smart-84fe58a1-8fe9-4137-8ba1-50cc5aafa558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524726804 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_both.1524726804
Directory /workspace/6.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt.1338417127
Short name T307
Test name
Test status
Simulation time 167031913498 ps
CPU time 359.65 seconds
Started Jul 09 06:33:15 PM PDT 24
Finished Jul 09 06:39:23 PM PDT 24
Peak memory 201896 kb
Host smart-31a39840-cc8e-4665-af3b-5b78f11f1bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338417127 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrupt.1338417127
Directory /workspace/6.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_interrupt_fixed.1704716286
Short name T612
Test name
Test status
Simulation time 325449431090 ps
CPU time 201.4 seconds
Started Jul 09 06:33:17 PM PDT 24
Finished Jul 09 06:36:45 PM PDT 24
Peak memory 201900 kb
Host smart-e8c74b80-9197-4398-8e5a-6dfe87c026f0
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704716286 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_interrup
t_fixed.1704716286
Directory /workspace/6.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_polled_fixed.872454725
Short name T627
Test name
Test status
Simulation time 486844646221 ps
CPU time 1011.7 seconds
Started Jul 09 06:33:14 PM PDT 24
Finished Jul 09 06:50:14 PM PDT 24
Peak memory 201940 kb
Host smart-8aa83af5-2971-451c-a61d-189e0abf4aae
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=872454725 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_filters_polled_fixed
.872454725
Directory /workspace/6.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_filters_wakeup_fixed.2602024473
Short name T681
Test name
Test status
Simulation time 584719928863 ps
CPU time 1287.59 seconds
Started Jul 09 06:33:15 PM PDT 24
Finished Jul 09 06:54:50 PM PDT 24
Peak memory 201904 kb
Host smart-9f49592c-7293-423e-8b01-ccf901c29d71
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602024473 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.
adc_ctrl_filters_wakeup_fixed.2602024473
Directory /workspace/6.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/6.adc_ctrl_fsm_reset.1744823681
Short name T659
Test name
Test status
Simulation time 83407482302 ps
CPU time 412 seconds
Started Jul 09 06:33:22 PM PDT 24
Finished Jul 09 06:40:18 PM PDT 24
Peak memory 202184 kb
Host smart-399a6cd3-aec0-4819-8e5a-13cbdee4328b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744823681 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_fsm_reset.1744823681
Directory /workspace/6.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/6.adc_ctrl_lowpower_counter.855865091
Short name T362
Test name
Test status
Simulation time 42969067022 ps
CPU time 89.36 seconds
Started Jul 09 06:33:36 PM PDT 24
Finished Jul 09 06:35:07 PM PDT 24
Peak memory 201724 kb
Host smart-b48e61ec-bbc6-447b-8a17-e214ee56b382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855865091 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_lowpower_counter.855865091
Directory /workspace/6.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_poweron_counter.1513689158
Short name T437
Test name
Test status
Simulation time 4347080925 ps
CPU time 5.88 seconds
Started Jul 09 06:33:18 PM PDT 24
Finished Jul 09 06:33:30 PM PDT 24
Peak memory 201724 kb
Host smart-dbe3edbe-5eda-4a6d-9b07-6defec65a747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513689158 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_poweron_counter.1513689158
Directory /workspace/6.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/6.adc_ctrl_smoke.1149481903
Short name T730
Test name
Test status
Simulation time 5968178164 ps
CPU time 4.44 seconds
Started Jul 09 06:33:10 PM PDT 24
Finished Jul 09 06:33:25 PM PDT 24
Peak memory 201724 kb
Host smart-fe47e6f0-da07-47be-b283-90c583af5351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149481903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_smoke.1149481903
Directory /workspace/6.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all.2106152599
Short name T428
Test name
Test status
Simulation time 6278622110 ps
CPU time 14.63 seconds
Started Jul 09 06:33:19 PM PDT 24
Finished Jul 09 06:33:40 PM PDT 24
Peak memory 201736 kb
Host smart-8ff41739-52fc-41e2-9ace-19956eb2e26c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106152599 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all.
2106152599
Directory /workspace/6.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.adc_ctrl_stress_all_with_rand_reset.2960330494
Short name T36
Test name
Test status
Simulation time 100639496444 ps
CPU time 102.23 seconds
Started Jul 09 06:33:25 PM PDT 24
Finished Jul 09 06:35:10 PM PDT 24
Peak memory 218448 kb
Host smart-c7a6bdd5-9ed4-48a9-950c-f39e88443edd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=adc_ctrl_stress_all_vseq +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960330494 -assert nop
ostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover
age/default.vdb -cm_log /dev/null -cm_name 6.adc_ctrl_stress_all_with_rand_reset.2960330494
Directory /workspace/6.adc_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_alert_test.3325024581
Short name T644
Test name
Test status
Simulation time 577517601 ps
CPU time 0.75 seconds
Started Jul 09 06:33:22 PM PDT 24
Finished Jul 09 06:33:27 PM PDT 24
Peak memory 201660 kb
Host smart-fb3fef82-b392-4d1a-893d-ee515a66b5ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325024581 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_alert_test.3325024581
Directory /workspace/7.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_both.3650788642
Short name T594
Test name
Test status
Simulation time 206387307733 ps
CPU time 195.5 seconds
Started Jul 09 06:33:19 PM PDT 24
Finished Jul 09 06:36:41 PM PDT 24
Peak memory 201892 kb
Host smart-b0ab4426-0b11-4353-93f2-20230f8c9207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650788642 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_both.3650788642
Directory /workspace/7.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_interrupt_fixed.2042154747
Short name T660
Test name
Test status
Simulation time 330131560836 ps
CPU time 704.48 seconds
Started Jul 09 06:33:20 PM PDT 24
Finished Jul 09 06:45:10 PM PDT 24
Peak memory 201868 kb
Host smart-8a609e36-8def-4efd-b3c2-e42493a66471
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042154747 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_interrup
t_fixed.2042154747
Directory /workspace/7.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled.3686770300
Short name T319
Test name
Test status
Simulation time 164639138448 ps
CPU time 380.52 seconds
Started Jul 09 06:33:19 PM PDT 24
Finished Jul 09 06:39:45 PM PDT 24
Peak memory 201924 kb
Host smart-a1dc3994-6ccc-4814-9335-3aba6d7d202c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686770300 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled.3686770300
Directory /workspace/7.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_polled_fixed.1343555270
Short name T661
Test name
Test status
Simulation time 499038848425 ps
CPU time 286.91 seconds
Started Jul 09 06:33:18 PM PDT 24
Finished Jul 09 06:38:11 PM PDT 24
Peak memory 201884 kb
Host smart-4992856a-63f3-432c-bf6f-d12d5d37d8d1
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343555270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_polled_fixe
d.1343555270
Directory /workspace/7.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup.2082623375
Short name T276
Test name
Test status
Simulation time 358110282772 ps
CPU time 411.29 seconds
Started Jul 09 06:33:19 PM PDT 24
Finished Jul 09 06:40:16 PM PDT 24
Peak memory 201888 kb
Host smart-435d7ac1-22db-4521-9007-af1f6753ce3f
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082623375 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_filters_
wakeup.2082623375
Directory /workspace/7.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/7.adc_ctrl_filters_wakeup_fixed.3647084756
Short name T593
Test name
Test status
Simulation time 591037418024 ps
CPU time 722.08 seconds
Started Jul 09 06:33:22 PM PDT 24
Finished Jul 09 06:45:28 PM PDT 24
Peak memory 201836 kb
Host smart-8722f6c9-b9ad-4066-b430-9268d825612c
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647084756 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.
adc_ctrl_filters_wakeup_fixed.3647084756
Directory /workspace/7.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/7.adc_ctrl_fsm_reset.1151556034
Short name T603
Test name
Test status
Simulation time 130728902949 ps
CPU time 680.18 seconds
Started Jul 09 06:33:19 PM PDT 24
Finished Jul 09 06:44:45 PM PDT 24
Peak memory 202216 kb
Host smart-4ec9b99f-da1b-4327-a772-11af8e97bd05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151556034 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_fsm_reset.1151556034
Directory /workspace/7.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/7.adc_ctrl_lowpower_counter.4051411122
Short name T783
Test name
Test status
Simulation time 34381630268 ps
CPU time 16.13 seconds
Started Jul 09 06:33:21 PM PDT 24
Finished Jul 09 06:33:42 PM PDT 24
Peak memory 201896 kb
Host smart-d4e6af12-d02f-4552-8ddb-c301cea847cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051411122 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_lowpower_counter.4051411122
Directory /workspace/7.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_poweron_counter.1684353238
Short name T712
Test name
Test status
Simulation time 3222118265 ps
CPU time 2.58 seconds
Started Jul 09 06:33:36 PM PDT 24
Finished Jul 09 06:33:41 PM PDT 24
Peak memory 201472 kb
Host smart-952f3c70-7aa6-4e17-8dcf-3c8c5dabca80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684353238 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_poweron_counter.1684353238
Directory /workspace/7.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/7.adc_ctrl_smoke.3415360165
Short name T779
Test name
Test status
Simulation time 5966456698 ps
CPU time 13.83 seconds
Started Jul 09 06:33:36 PM PDT 24
Finished Jul 09 06:33:52 PM PDT 24
Peak memory 201716 kb
Host smart-48ce6935-39d9-4979-9cc7-3ed6088e3455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415360165 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_smoke.3415360165
Directory /workspace/7.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/7.adc_ctrl_stress_all.3372259049
Short name T498
Test name
Test status
Simulation time 142170873484 ps
CPU time 709.26 seconds
Started Jul 09 06:33:22 PM PDT 24
Finished Jul 09 06:45:16 PM PDT 24
Peak memory 202284 kb
Host smart-7007dcaa-358b-48f9-b0b5-36d963d6fa48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372259049 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.adc_ctrl_stress_all.
3372259049
Directory /workspace/7.adc_ctrl_stress_all/latest

Test location /workspace/coverage/default/8.adc_ctrl_alert_test.1632176270
Short name T630
Test name
Test status
Simulation time 446482875 ps
CPU time 0.96 seconds
Started Jul 09 06:33:26 PM PDT 24
Finished Jul 09 06:33:30 PM PDT 24
Peak memory 201588 kb
Host smart-0bbb1997-81e3-4b9a-9bcf-a54185c3cafb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632176270 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_alert_test.1632176270
Directory /workspace/8.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.adc_ctrl_clock_gating.3705409507
Short name T166
Test name
Test status
Simulation time 166434007083 ps
CPU time 178.48 seconds
Started Jul 09 06:33:36 PM PDT 24
Finished Jul 09 06:36:37 PM PDT 24
Peak memory 201900 kb
Host smart-340d60c1-ad00-4bbf-990c-4908cfaf04bc
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705409507 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_clock_gati
ng.3705409507
Directory /workspace/8.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_both.185355734
Short name T259
Test name
Test status
Simulation time 172846904181 ps
CPU time 259.05 seconds
Started Jul 09 06:33:23 PM PDT 24
Finished Jul 09 06:37:46 PM PDT 24
Peak memory 201928 kb
Host smart-1ffd144b-5feb-45e6-96e8-8189cb720d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185355734 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_both.185355734
Directory /workspace/8.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt.1899411152
Short name T7
Test name
Test status
Simulation time 331920825848 ps
CPU time 355.7 seconds
Started Jul 09 06:33:36 PM PDT 24
Finished Jul 09 06:39:34 PM PDT 24
Peak memory 201912 kb
Host smart-e12da14a-e40d-410f-84c6-316b282155dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899411152 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrupt.1899411152
Directory /workspace/8.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_interrupt_fixed.1529484021
Short name T174
Test name
Test status
Simulation time 324674337874 ps
CPU time 191.68 seconds
Started Jul 09 06:33:43 PM PDT 24
Finished Jul 09 06:36:57 PM PDT 24
Peak memory 201876 kb
Host smart-f05e575a-5d04-4fc0-93d0-e62122f9da9d
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529484021 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_interrup
t_fixed.1529484021
Directory /workspace/8.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled.1939363189
Short name T98
Test name
Test status
Simulation time 162847699728 ps
CPU time 379.52 seconds
Started Jul 09 06:33:22 PM PDT 24
Finished Jul 09 06:39:46 PM PDT 24
Peak memory 201848 kb
Host smart-a8877520-61ab-4c25-b18c-eadff44e7eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939363189 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled.1939363189
Directory /workspace/8.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_polled_fixed.3527461983
Short name T687
Test name
Test status
Simulation time 495599520828 ps
CPU time 174.64 seconds
Started Jul 09 06:33:36 PM PDT 24
Finished Jul 09 06:36:33 PM PDT 24
Peak memory 201680 kb
Host smart-861f85f5-815b-4b9e-8189-d922ff0c313b
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527461983 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_polled_fixe
d.3527461983
Directory /workspace/8.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup.2576115533
Short name T269
Test name
Test status
Simulation time 546750743966 ps
CPU time 1150.13 seconds
Started Jul 09 06:33:18 PM PDT 24
Finished Jul 09 06:52:34 PM PDT 24
Peak memory 201896 kb
Host smart-e14e8ab5-d9c0-47fa-9539-0c9a0366441c
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576115533 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_filters_
wakeup.2576115533
Directory /workspace/8.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/8.adc_ctrl_filters_wakeup_fixed.3559690359
Short name T8
Test name
Test status
Simulation time 590093718863 ps
CPU time 319.75 seconds
Started Jul 09 06:33:19 PM PDT 24
Finished Jul 09 06:38:44 PM PDT 24
Peak memory 201888 kb
Host smart-672274f7-1683-4504-a330-8a3475edd9ce
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559690359 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.
adc_ctrl_filters_wakeup_fixed.3559690359
Directory /workspace/8.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/8.adc_ctrl_fsm_reset.1426111895
Short name T609
Test name
Test status
Simulation time 83403755729 ps
CPU time 422.75 seconds
Started Jul 09 06:33:24 PM PDT 24
Finished Jul 09 06:40:30 PM PDT 24
Peak memory 202232 kb
Host smart-8fdbed58-572e-4e51-9d53-dd8c6cfc50a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426111895 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_fsm_reset.1426111895
Directory /workspace/8.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/8.adc_ctrl_lowpower_counter.3730769025
Short name T454
Test name
Test status
Simulation time 34487242356 ps
CPU time 74.67 seconds
Started Jul 09 06:33:25 PM PDT 24
Finished Jul 09 06:34:43 PM PDT 24
Peak memory 201740 kb
Host smart-57c68ec3-b599-4528-a56d-aeae714cdc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730769025 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_lowpower_counter.3730769025
Directory /workspace/8.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_poweron_counter.1444131410
Short name T568
Test name
Test status
Simulation time 5214038940 ps
CPU time 5.9 seconds
Started Jul 09 06:33:23 PM PDT 24
Finished Jul 09 06:33:33 PM PDT 24
Peak memory 201948 kb
Host smart-e796bcc7-630f-4621-b937-b8de82d9f423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444131410 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_poweron_counter.1444131410
Directory /workspace/8.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/8.adc_ctrl_smoke.1441870606
Short name T601
Test name
Test status
Simulation time 6078041817 ps
CPU time 7.77 seconds
Started Jul 09 06:33:36 PM PDT 24
Finished Jul 09 06:33:46 PM PDT 24
Peak memory 201712 kb
Host smart-02205d01-b730-4f06-af45-637cb81920c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441870606 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.adc_ctrl_smoke.1441870606
Directory /workspace/8.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_alert_test.1703713192
Short name T395
Test name
Test status
Simulation time 445543646 ps
CPU time 1.7 seconds
Started Jul 09 06:33:27 PM PDT 24
Finished Jul 09 06:33:31 PM PDT 24
Peak memory 201652 kb
Host smart-13a6c3e8-a82d-4ae9-886e-ced5e6251b34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703713192 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_alert_test.1703713192
Directory /workspace/9.adc_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.adc_ctrl_clock_gating.4019992003
Short name T253
Test name
Test status
Simulation time 352377242916 ps
CPU time 118.67 seconds
Started Jul 09 06:33:27 PM PDT 24
Finished Jul 09 06:35:28 PM PDT 24
Peak memory 201908 kb
Host smart-0814411d-6709-4d35-bfb7-1c42515e7eda
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019992003 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_clock_
gating_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_clock_gati
ng.4019992003
Directory /workspace/9.adc_ctrl_clock_gating/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_both.953784752
Short name T222
Test name
Test status
Simulation time 172003718310 ps
CPU time 104.1 seconds
Started Jul 09 06:33:29 PM PDT 24
Finished Jul 09 06:35:15 PM PDT 24
Peak memory 201944 kb
Host smart-339fde90-5689-4e6a-9a11-04147652b60f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953784752 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_both_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_both.953784752
Directory /workspace/9.adc_ctrl_filters_both/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt.3179215971
Short name T649
Test name
Test status
Simulation time 486036153615 ps
CPU time 529.58 seconds
Started Jul 09 06:33:25 PM PDT 24
Finished Jul 09 06:42:18 PM PDT 24
Peak memory 201928 kb
Host smart-1be7bc32-16cd-483e-a3ce-30c840e45f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179215971 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt.3179215971
Directory /workspace/9.adc_ctrl_filters_interrupt/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_interrupt_fixed.991094875
Short name T757
Test name
Test status
Simulation time 322124276691 ps
CPU time 788.11 seconds
Started Jul 09 06:33:25 PM PDT 24
Finished Jul 09 06:46:37 PM PDT 24
Peak memory 201884 kb
Host smart-f865ea4f-3ea9-4aba-899c-fc10740ddc6e
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=991094875 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_interrupt_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_interrupt
_fixed.991094875
Directory /workspace/9.adc_ctrl_filters_interrupt_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled.2742247553
Short name T139
Test name
Test status
Simulation time 325698276341 ps
CPU time 181.42 seconds
Started Jul 09 06:33:25 PM PDT 24
Finished Jul 09 06:36:30 PM PDT 24
Peak memory 201916 kb
Host smart-215c1852-8c42-460d-99c2-c71539e244ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742247553 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled.2742247553
Directory /workspace/9.adc_ctrl_filters_polled/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_polled_fixed.4007861116
Short name T415
Test name
Test status
Simulation time 495152454606 ps
CPU time 295.21 seconds
Started Jul 09 06:33:22 PM PDT 24
Finished Jul 09 06:38:22 PM PDT 24
Peak memory 201996 kb
Host smart-9d8a6f27-a02b-4ac6-8a56-12f5f8f0e9ce
User root
Command /workspace/default/simv +filters_fixed=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/rep
o_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007861116 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filters_polled_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_polled_fixe
d.4007861116
Directory /workspace/9.adc_ctrl_filters_polled_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup.2820243903
Short name T310
Test name
Test status
Simulation time 535227648883 ps
CPU time 831.67 seconds
Started Jul 09 06:33:24 PM PDT 24
Finished Jul 09 06:47:20 PM PDT 24
Peak memory 202000 kb
Host smart-f72fa609-3cd5-492e-8c52-bb1f310c5493
User root
Command /workspace/default/simv +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp
ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820243903 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_filter
s_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_filters_
wakeup.2820243903
Directory /workspace/9.adc_ctrl_filters_wakeup/latest

Test location /workspace/coverage/default/9.adc_ctrl_filters_wakeup_fixed.1902077368
Short name T650
Test name
Test status
Simulation time 193995443631 ps
CPU time 292.46 seconds
Started Jul 09 06:33:28 PM PDT 24
Finished Jul 09 06:38:23 PM PDT 24
Peak memory 201940 kb
Host smart-996919a0-d905-41f4-ba24-7a777029a3f7
User root
Command /workspace/default/simv +filters_fixed=1 +test_timeout_ns=2000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902077368 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SE
Q=adc_ctrl_filters_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.
adc_ctrl_filters_wakeup_fixed.1902077368
Directory /workspace/9.adc_ctrl_filters_wakeup_fixed/latest

Test location /workspace/coverage/default/9.adc_ctrl_fsm_reset.1722537271
Short name T788
Test name
Test status
Simulation time 85755020729 ps
CPU time 367.38 seconds
Started Jul 09 06:33:26 PM PDT 24
Finished Jul 09 06:39:37 PM PDT 24
Peak memory 202256 kb
Host smart-62c15bb4-f82c-4256-b6da-06102500af79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722537271 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_fsm_reset_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_fsm_reset.1722537271
Directory /workspace/9.adc_ctrl_fsm_reset/latest

Test location /workspace/coverage/default/9.adc_ctrl_lowpower_counter.4281557433
Short name T624
Test name
Test status
Simulation time 43125405937 ps
CPU time 88.23 seconds
Started Jul 09 06:33:28 PM PDT 24
Finished Jul 09 06:34:58 PM PDT 24
Peak memory 201736 kb
Host smart-3c480925-2079-42d5-bd78-4906ffea7a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281557433 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_lowpower_counter_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_lowpower_counter.4281557433
Directory /workspace/9.adc_ctrl_lowpower_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_poweron_counter.958164759
Short name T638
Test name
Test status
Simulation time 4210618651 ps
CPU time 9.54 seconds
Started Jul 09 06:33:27 PM PDT 24
Finished Jul 09 06:33:39 PM PDT 24
Peak memory 201708 kb
Host smart-df6c47b0-0508-4261-95bc-f60799f4d6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958164759 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_poweron_counter_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_poweron_counter.958164759
Directory /workspace/9.adc_ctrl_poweron_counter/latest

Test location /workspace/coverage/default/9.adc_ctrl_smoke.1866008849
Short name T786
Test name
Test status
Simulation time 6006447779 ps
CPU time 14.13 seconds
Started Jul 09 06:33:25 PM PDT 24
Finished Jul 09 06:33:42 PM PDT 24
Peak memory 201556 kb
Host smart-c796e6e1-6264-4ef1-8df6-869095574b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866008849 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_smoke_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_smoke.1866008849
Directory /workspace/9.adc_ctrl_smoke/latest

Test location /workspace/coverage/default/9.adc_ctrl_stress_all.1267078304
Short name T527
Test name
Test status
Simulation time 208688088899 ps
CPU time 236.65 seconds
Started Jul 09 06:33:29 PM PDT 24
Finished Jul 09 06:37:28 PM PDT 24
Peak memory 201892 kb
Host smart-fe48c314-bb71-47fe-a4b6-9463c40d39b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267078304 -assert nopostproc +UVM_TESTNAME=adc_ctrl_base_test +UVM_TEST_SEQ=adc_ctrl_stres
s_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.adc_ctrl_stress_all.
1267078304
Directory /workspace/9.adc_ctrl_stress_all/latest
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