Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1201320	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1174556

1

T1

398

T2

20

T4

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2074706	1			T4	1		T3	6557		T6	2423
values[0x0]	149537	1			T1	505		T2	26		T4	2
values[0x1]	151633	1			T1	507		T2	14		T4	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	962174	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1413702

1

T1

481

T2

24

T4

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8609	1			T3	15		T6	12		T7	40
valid_sources[0x01]	7440	1			T1	6		T3	7		T6	11
valid_sources[0x02]	8277	1			T3	17		T7	53		T9	14
valid_sources[0x03]	11454	1			T1	2		T3	30		T6	3
valid_sources[0x04]	8174	1			T1	3		T3	6		T7	46
valid_sources[0x05]	7611	1			T1	1		T3	10		T6	15
valid_sources[0x06]	7923	1			T1	1		T3	40		T6	11
valid_sources[0x07]	7124	1			T1	2		T3	14		T6	4
valid_sources[0x08]	7214	1			T1	5		T3	16		T6	20
valid_sources[0x09]	7311	1			T1	14		T3	19		T6	7
valid_sources[0x0a]	11615	1			T1	14		T3	24		T6	20
valid_sources[0x0b]	8147	1			T1	2		T3	9		T6	23
valid_sources[0x0c]	7428	1			T3	41		T6	11		T7	58
valid_sources[0x0d]	7099	1			T1	8		T3	37		T6	16
valid_sources[0x0e]	7552	1			T1	12		T3	12		T5	1
valid_sources[0x0f]	7414	1			T3	38		T6	5		T7	78
valid_sources[0x10]	15671	1			T1	2		T3	12		T6	16
valid_sources[0x11]	12070	1			T3	30		T6	12		T7	47
valid_sources[0x12]	13369	1			T3	24		T6	2		T7	51
valid_sources[0x13]	8075	1			T3	20		T6	14		T7	58
valid_sources[0x14]	7466	1			T1	3		T3	11		T6	25
valid_sources[0x15]	7895	1			T1	10		T3	31		T7	61
valid_sources[0x16]	8405	1			T1	7		T3	68		T6	7
valid_sources[0x17]	13423	1			T3	24		T6	2		T7	40
valid_sources[0x18]	7115	1			T1	10		T3	33		T6	6
valid_sources[0x19]	11308	1			T1	3		T3	23		T6	3
valid_sources[0x1a]	7564	1			T1	10		T3	40		T6	14
valid_sources[0x1b]	8583	1			T1	2		T3	12		T6	6
valid_sources[0x1c]	7098	1			T1	3		T3	29		T6	7
valid_sources[0x1d]	16913	1			T1	7		T3	48		T6	17
valid_sources[0x1e]	7083	1			T1	10		T3	12		T6	2
valid_sources[0x1f]	8154	1			T1	1		T3	27		T6	9
valid_sources[0x20]	8016	1			T1	2		T3	39		T6	9
valid_sources[0x21]	7851	1			T1	6		T3	12		T6	21
valid_sources[0x22]	11665	1			T3	36		T6	9		T7	42
valid_sources[0x23]	7299	1			T1	10		T3	39		T6	3
valid_sources[0x24]	11280	1			T1	9		T4	10		T3	16
valid_sources[0x25]	7900	1			T1	3		T3	22		T6	2
valid_sources[0x26]	10168	1			T1	1		T3	59		T6	18
valid_sources[0x27]	7276	1			T1	2		T3	8		T6	35
valid_sources[0x28]	12392	1			T1	9		T3	11		T6	35
valid_sources[0x29]	8505	1			T3	35		T6	11		T7	45
valid_sources[0x2a]	10380	1			T1	5		T3	64		T6	2
valid_sources[0x2b]	7213	1			T3	43		T6	17		T7	43
valid_sources[0x2c]	11805	1			T1	1		T3	13		T6	35
valid_sources[0x2d]	7592	1			T3	87		T6	11		T7	55
valid_sources[0x2e]	7399	1			T1	3		T3	29		T6	12
valid_sources[0x2f]	7244	1			T3	30		T6	25		T7	54
valid_sources[0x30]	12877	1			T1	7		T3	37		T6	9
valid_sources[0x31]	7984	1			T3	22		T6	10		T7	70
valid_sources[0x32]	7614	1			T1	4		T3	62		T6	37
valid_sources[0x33]	9261	1			T3	64		T6	2		T7	70
valid_sources[0x34]	7532	1			T1	1		T3	14		T6	4
valid_sources[0x35]	10092	1			T1	11		T3	36		T7	59
valid_sources[0x36]	9589	1			T3	36		T6	9		T7	58
valid_sources[0x37]	7708	1			T1	3		T3	36		T6	15
valid_sources[0x38]	11418	1			T3	12		T6	6		T7	42
valid_sources[0x39]	7035	1			T3	2		T7	49		T9	11
valid_sources[0x3a]	7492	1			T1	11		T3	13		T6	17
valid_sources[0x3b]	7483	1			T1	8		T3	16		T6	4
valid_sources[0x3c]	7971	1			T1	7		T3	45		T6	23
valid_sources[0x3d]	15659	1			T1	7		T3	83		T5	7
valid_sources[0x3e]	8095	1			T3	12		T6	8		T7	56
valid_sources[0x3f]	7461	1			T1	2		T3	72		T6	6
valid_sources[0x40]	9971	1			T1	4		T3	27		T7	54
valid_sources[0x41]	7837	1			T1	5		T3	5		T7	39
valid_sources[0x42]	12267	1			T1	3		T3	24		T7	42
valid_sources[0x43]	10064	1			T1	6		T3	27		T6	16
valid_sources[0x44]	7818	1			T1	13		T3	24		T6	9
valid_sources[0x45]	12504	1			T1	7		T3	25		T6	7
valid_sources[0x46]	7229	1			T3	12		T7	69		T10	24
valid_sources[0x47]	7062	1			T1	1		T3	33		T6	6
valid_sources[0x48]	7230	1			T1	8		T3	23		T6	15
valid_sources[0x49]	6976	1			T1	10		T3	14		T6	8
valid_sources[0x4a]	9916	1			T3	7		T7	46		T10	50
valid_sources[0x4b]	7734	1			T1	3		T3	76		T6	9
valid_sources[0x4c]	8181	1			T1	5		T3	29		T7	45
valid_sources[0x4d]	8403	1			T1	6		T3	27		T6	5
valid_sources[0x4e]	7658	1			T1	9		T3	51		T6	7
valid_sources[0x4f]	7109	1			T1	2		T3	9		T6	1
valid_sources[0x50]	7203	1			T3	12		T6	11		T7	48
valid_sources[0x51]	9014	1			T1	17		T3	19		T7	50
valid_sources[0x52]	11675	1			T1	4		T3	21		T6	12
valid_sources[0x53]	7065	1			T1	5		T3	5		T6	7
valid_sources[0x54]	7240	1			T1	7		T3	43		T5	2
valid_sources[0x55]	14465	1			T1	2		T3	3		T7	58
valid_sources[0x56]	7522	1			T1	9		T3	35		T6	21
valid_sources[0x57]	8814	1			T1	12		T3	24		T6	20
valid_sources[0x58]	8741	1			T3	26		T7	51		T10	22
valid_sources[0x59]	8050	1			T1	1		T3	53		T6	12
valid_sources[0x5a]	11977	1			T3	27		T6	18		T7	44
valid_sources[0x5b]	11715	1			T1	8		T3	38		T6	4
valid_sources[0x5c]	21198	1			T1	5		T3	41		T6	11
valid_sources[0x5d]	8212	1			T1	2		T3	25		T7	57
valid_sources[0x5e]	9390	1			T1	3		T3	23		T6	2
valid_sources[0x5f]	7660	1			T3	34		T6	11		T7	73
valid_sources[0x60]	10863	1			T3	28		T6	28		T7	46
valid_sources[0x61]	7374	1			T1	3		T3	16		T6	9
valid_sources[0x62]	7219	1			T1	2		T3	23		T6	20
valid_sources[0x63]	10227	1			T1	1		T3	26		T6	29
valid_sources[0x64]	11858	1			T3	29		T6	7		T7	56
valid_sources[0x65]	9580	1			T3	22		T6	16		T7	64
valid_sources[0x66]	19896	1			T1	1		T3	12		T6	7
valid_sources[0x67]	10227	1			T1	2		T3	29		T6	10
valid_sources[0x68]	15614	1			T3	24		T6	4		T7	52
valid_sources[0x69]	8469	1			T1	2		T3	14		T6	1
valid_sources[0x6a]	8054	1			T3	24		T6	13		T7	40
valid_sources[0x6b]	11254	1			T1	5		T3	9		T6	5
valid_sources[0x6c]	7436	1			T3	23		T6	7		T7	56
valid_sources[0x6d]	7469	1			T1	3		T3	30		T6	8
valid_sources[0x6e]	7223	1			T3	11		T6	4		T7	50
valid_sources[0x6f]	11198	1			T1	13		T3	32		T7	51
valid_sources[0x70]	7601	1			T1	10		T3	39		T5	3
valid_sources[0x71]	7365	1			T1	4		T3	4		T6	9
valid_sources[0x72]	11741	1			T1	3		T3	28		T6	5
valid_sources[0x73]	20341	1			T1	1		T3	23		T6	3
valid_sources[0x74]	7864	1			T3	3		T6	8		T7	36
valid_sources[0x75]	7728	1			T1	2		T3	16		T6	7
valid_sources[0x76]	10984	1			T1	2		T3	42		T6	28
valid_sources[0x77]	16978	1			T1	11		T6	37		T7	56
valid_sources[0x78]	7460	1			T3	49		T6	4		T7	55
valid_sources[0x79]	7451	1			T1	5		T3	11		T6	7
valid_sources[0x7a]	7456	1			T3	24		T6	6		T7	45
valid_sources[0x7b]	6967	1			T1	1		T3	78		T6	5
valid_sources[0x7c]	13453	1			T1	8		T3	32		T6	37
valid_sources[0x7d]	9128	1			T1	8		T3	40		T6	8
valid_sources[0x7e]	11519	1			T1	2		T3	10		T6	14
valid_sources[0x7f]	7193	1			T1	12		T3	36		T6	12
valid_sources[0x80]	10057	1			T1	9		T3	31		T7	44

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1032953

1

T3

3264

T6

1229

T7

5906

values[0x0]

all_enables

biggest_size

81972

1

T1

224

T2

14

T4

1

values[0x1]

all_enables

biggest_size

59631

1

T1

174

T2

6

T3

97