Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	28022	1			T1	234		T3	14		T6	5
auto[PWRUP]	133	1			T1	2		T9	1		T11	2
auto[ONEST_0]	66	1			T1	1		T11	1		T47	1
auto[ONEST_021]	16	1			T1	1		T15	1		T47	1
auto[ONEST_1]	84	1			T1	2		T11	1		T15	2
auto[ONEST_DONE]	4	1			T194	1		T195	1		T196	2
auto[LP_0]	114	1			T1	2		T9	2		T11	1
auto[LP_021]	19	1			T1	1		T197	1		T198	2
auto[LP_1]	134	1			T1	4		T9	2		T11	4
auto[LP_EVAL]	68	1			T1	1		T9	1		T11	1
auto[LP_SLP]	469	1			T1	8		T9	14		T11	4
auto[LP_PWRUP]	33	1			T1	2		T9	2		T15	1
auto[NP_0]	164	1			T1	2		T9	1		T11	4
auto[NP_021]	27	1			T9	1		T11	1		T55	1
auto[NP_1]	166	1			T1	1		T11	1		T15	5
auto[NP_EVAL]	41	1			T9	1		T15	1		T197	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

4

1

T17

1

T199

1

T200

1

min

27462

1

T1

239

T3

14

T6

5

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27471	1			T1	240		T3	14		T6	5
pow[0x1]	10	1			T201	1		T202	1		T203	1
pow[0x2]	23	1			T9	1		T15	1		T47	1
pow[0x3]	31	1			T1	1		T55	1		T204	3
pow[0x4]	60	1			T1	1		T11	1		T47	1
pow[0x5]	130	1			T1	1		T9	2		T11	1
pow[0x6]	242	1			T1	2		T9	2		T11	4
pow[0x7]	545	1			T1	5		T9	7		T11	6

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

176

1

T1

4

T9

1

T11

1

min

27024

1

T1

225

T3

14

T6

5

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x5]	0	1	1
pow[0x7]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27024	1			T1	225		T3	14		T6	5
pow[0x4]	2	1			T205	1		T206	1		-	-
pow[0x6]	1	1			T194	1		-	-		-	-
pow[0x8]	1	1			T207	1		-	-		-	-
pow[0x9]	8	1			T1	1		T208	1		T166	1
pow[0xa]	17	1			T47	1		T26	1		T17	1
pow[0xb]	40	1			T15	1		T47	1		T209	1
pow[0xc]	58	1			T1	2		T9	2		T15	2
pow[0xd]	157	1			T1	2		T9	2		T11	2
pow[0xe]	309	1			T1	4		T9	5		T11	2
pow[0xf]	575	1			T1	9		T9	9		T11	10