Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.56	95.56	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	95.56	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.56	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	2	43	95.56

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	1	15	93.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2390	1			T1	13		T3	4		T9	21
auto[PWRUP]	141	1			T9	2		T11	1		T15	2
auto[ONEST_0]	90	1			T1	1		T9	1		T11	1
auto[ONEST_021]	13	1			T98	2		T166	3		T338	1
auto[ONEST_1]	91	1			T11	2		T47	2		T55	1
auto[ONEST_DONE]	4	1			T1	1		T339	1		T340	1
auto[LP_0]	140	1			T9	1		T11	3		T15	1
auto[LP_021]	31	1			T1	2		T9	1		T55	2
auto[LP_1]	153	1			T1	4		T9	1		T11	2
auto[LP_EVAL]	59	1			T1	1		T11	1		T15	1
auto[LP_SLP]	579	1			T1	6		T9	4		T11	8
auto[LP_PWRUP]	33	1			T9	1		T47	1		T341	1
auto[NP_0]	232	1			T1	2		T11	1		T47	3
auto[NP_021]	57	1			T1	1		T11	1		T15	1
auto[NP_1]	233	1			T1	1		T9	2		T11	1
auto[NP_EVAL]	42	1			T9	1		T47	1		T16	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

12

1

T342

1

T166

2

T203

1

min

2103

1

T1

10

T3

4

T9

7

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	2119	1			T1	10		T3	4		T9	7
pow[0x1]	13	1			T47	1		T197	1		T341	1
pow[0x2]	32	1			T1	1		T47	2		T204	1
pow[0x3]	53	1			T11	1		T197	1		T26	2
pow[0x4]	68	1			T1	3		T11	3		T15	1
pow[0x5]	130	1			T1	2		T9	2		T11	1
pow[0x6]	267	1			T1	1		T9	7		T11	4
pow[0x7]	519	1			T1	9		T9	9		T11	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

219

1

T1

5

T9

2

T11

3

min

1439

1

T1

3

T3

4

T9

2

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	1	15	93.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1442	1			T1	3		T3	4		T9	2
pow[0x1]	14	1			T16	2		T32	1		T17	1
pow[0x2]	42	1			T18	3		T56	1		T19	1
pow[0x3]	40	1			T47	4		T32	1		T56	1
pow[0x4]	62	1			T32	2		T36	3		T48	5
pow[0x5]	3	1			T19	1		T98	1		T343	1
pow[0x7]	3	1			T102	1		T207	1		T344	1
pow[0x8]	5	1			T47	1		T197	1		T195	1
pow[0x9]	10	1			T197	2		T209	1		T98	1
pow[0xa]	16	1			T9	1		T17	1		T345	1
pow[0xb]	37	1			T1	1		T9	1		T209	1
pow[0xc]	68	1			T9	1		T11	1		T15	1
pow[0xd]	159	1			T1	2		T9	1		T11	5
pow[0xe]	312	1			T1	6		T9	3		T11	5
pow[0xf]	602	1			T1	4		T9	5		T11	17