Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2999	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2886	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2933	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	3034	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	3006	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	3026	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	3076	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	3028	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	3029	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	3177	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	2973	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2828	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	3132	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	3141	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2845	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	3084	0	0
adc_en_ctl_rd_A	2147483647	2745	0	0
adc_fsm_rst_rd_A	2147483647	2683	0	0
adc_intr_ctl_rd_A	2147483647	3155	0	0
adc_lp_sample_ctl_rd_A	2147483647	2632	0	0
adc_pd_ctl_rd_A	2147483647	2827	0	0
adc_sample_ctl_rd_A	2147483647	2471	0	0
adc_wakeup_ctl_rd_A	2147483647	2599	0	0
intr_enable_rd_A	2147483647	3375	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2999	0	0
T16	325643	10	0	0
T17	880795	15	0	0
T18	0	21	0	0
T19	0	43	0	0
T20	0	24	0	0
T21	0	7	0	0
T22	0	19	0	0
T23	0	19	0	0
T24	0	13	0	0
T25	0	22	0	0
T26	708554	0	0	0
T27	156657	0	0	0
T28	74483	0	0	0
T29	353966	0	0	0
T30	587726	0	0	0
T31	5891	0	0	0
T32	578664	0	0	0
T33	164892	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2886	0	0
T16	325643	17	0	0
T17	880795	7	0	0
T18	0	23	0	0
T19	0	42	0	0
T20	0	24	0	0
T21	0	4	0	0
T22	0	25	0	0
T23	0	5	0	0
T24	0	16	0	0
T25	0	8	0	0
T26	708554	0	0	0
T27	156657	0	0	0
T28	74483	0	0	0
T29	353966	0	0	0
T30	587726	0	0	0
T31	5891	0	0	0
T32	578664	0	0	0
T33	164892	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2933	0	0
T16	325643	8	0	0
T17	880795	8	0	0
T18	0	26	0	0
T19	0	47	0	0
T20	0	21	0	0
T21	0	18	0	0
T22	0	16	0	0
T23	0	24	0	0
T24	0	14	0	0
T25	0	17	0	0
T26	708554	0	0	0
T27	156657	0	0	0
T28	74483	0	0	0
T29	353966	0	0	0
T30	587726	0	0	0
T31	5891	0	0	0
T32	578664	0	0	0
T33	164892	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3034	0	0
T16	325643	20	0	0
T17	880795	20	0	0
T18	0	32	0	0
T19	0	25	0	0
T20	0	15	0	0
T21	0	3	0	0
T22	0	13	0	0
T23	0	19	0	0
T24	0	21	0	0
T25	0	19	0	0
T26	708554	0	0	0
T27	156657	0	0	0
T28	74483	0	0	0
T29	353966	0	0	0
T30	587726	0	0	0
T31	5891	0	0	0
T32	578664	0	0	0
T33	164892	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3006	0	0
T16	325643	15	0	0
T17	880795	9	0	0
T18	0	22	0	0
T19	0	27	0	0
T20	0	7	0	0
T21	0	11	0	0
T22	0	24	0	0
T23	0	9	0	0
T24	0	29	0	0
T25	0	34	0	0
T26	708554	0	0	0
T27	156657	0	0	0
T28	74483	0	0	0
T29	353966	0	0	0
T30	587726	0	0	0
T31	5891	0	0	0
T32	578664	0	0	0
T33	164892	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3026	0	0
T16	325643	19	0	0
T17	880795	10	0	0
T18	0	33	0	0
T19	0	40	0	0
T20	0	17	0	0
T21	0	14	0	0
T22	0	19	0	0
T24	0	25	0	0
T25	0	9	0	0
T26	708554	0	0	0
T27	156657	0	0	0
T28	74483	0	0	0
T29	353966	0	0	0
T30	587726	0	0	0
T31	5891	0	0	0
T32	578664	0	0	0
T33	164892	0	0	0
T34	0	9	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3076	0	0
T16	325643	28	0	0
T17	880795	10	0	0
T18	0	48	0	0
T19	0	34	0	0
T20	0	26	0	0
T21	0	8	0	0
T22	0	14	0	0
T23	0	9	0	0
T24	0	21	0	0
T25	0	16	0	0
T26	708554	0	0	0
T27	156657	0	0	0
T28	74483	0	0	0
T29	353966	0	0	0
T30	587726	0	0	0
T31	5891	0	0	0
T32	578664	0	0	0
T33	164892	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3028	0	0
T16	325643	24	0	0
T17	880795	11	0	0
T18	0	28	0	0
T19	0	40	0	0
T20	0	21	0	0
T21	0	12	0	0
T22	0	18	0	0
T23	0	5	0	0
T24	0	25	0	0
T25	0	8	0	0
T26	708554	0	0	0
T27	156657	0	0	0
T28	74483	0	0	0
T29	353966	0	0	0
T30	587726	0	0	0
T31	5891	0	0	0
T32	578664	0	0	0
T33	164892	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3029	0	0
T16	325643	31	0	0
T17	880795	11	0	0
T18	0	10	0	0
T19	0	28	0	0
T20	0	20	0	0
T22	0	12	0	0
T23	0	9	0	0
T24	0	15	0	0
T25	0	25	0	0
T26	708554	0	0	0
T27	156657	0	0	0
T28	74483	0	0	0
T29	353966	0	0	0
T30	587726	0	0	0
T31	5891	0	0	0
T32	578664	0	0	0
T33	164892	0	0	0
T34	0	16	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3177	0	0
T16	325643	11	0	0
T17	880795	4	0	0
T18	0	16	0	0
T19	0	49	0	0
T20	0	16	0	0
T21	0	2	0	0
T22	0	19	0	0
T23	0	14	0	0
T24	0	13	0	0
T25	0	12	0	0
T26	708554	0	0	0
T27	156657	0	0	0
T28	74483	0	0	0
T29	353966	0	0	0
T30	587726	0	0	0
T31	5891	0	0	0
T32	578664	0	0	0
T33	164892	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2973	0	0
T16	325643	15	0	0
T17	880795	4	0	0
T18	0	35	0	0
T19	0	38	0	0
T20	0	19	0	0
T21	0	12	0	0
T22	0	15	0	0
T23	0	21	0	0
T24	0	29	0	0
T25	0	20	0	0
T26	708554	0	0	0
T27	156657	0	0	0
T28	74483	0	0	0
T29	353966	0	0	0
T30	587726	0	0	0
T31	5891	0	0	0
T32	578664	0	0	0
T33	164892	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2828	0	0
T16	325643	16	0	0
T17	880795	1	0	0
T18	0	35	0	0
T19	0	47	0	0
T20	0	16	0	0
T22	0	15	0	0
T24	0	8	0	0
T25	0	14	0	0
T26	708554	0	0	0
T27	156657	0	0	0
T28	74483	0	0	0
T29	353966	0	0	0
T30	587726	0	0	0
T31	5891	0	0	0
T32	578664	0	0	0
T33	164892	0	0	0
T34	0	8	0	0
T35	0	39	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3132	0	0
T16	325643	20	0	0
T17	880795	14	0	0
T18	0	18	0	0
T19	0	48	0	0
T20	0	15	0	0
T22	0	13	0	0
T23	0	9	0	0
T24	0	12	0	0
T25	0	30	0	0
T26	708554	0	0	0
T27	156657	0	0	0
T28	74483	0	0	0
T29	353966	0	0	0
T30	587726	0	0	0
T31	5891	0	0	0
T32	578664	0	0	0
T33	164892	0	0	0
T34	0	12	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3141	0	0
T16	325643	13	0	0
T17	880795	29	0	0
T18	0	34	0	0
T19	0	46	0	0
T20	0	18	0	0
T21	0	2	0	0
T22	0	26	0	0
T23	0	13	0	0
T24	0	11	0	0
T25	0	17	0	0
T26	708554	0	0	0
T27	156657	0	0	0
T28	74483	0	0	0
T29	353966	0	0	0
T30	587726	0	0	0
T31	5891	0	0	0
T32	578664	0	0	0
T33	164892	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2845	0	0
T16	325643	25	0	0
T17	880795	11	0	0
T18	0	12	0	0
T19	0	28	0	0
T20	0	5	0	0
T21	0	10	0	0
T22	0	18	0	0
T24	0	29	0	0
T25	0	8	0	0
T26	708554	0	0	0
T27	156657	0	0	0
T28	74483	0	0	0
T29	353966	0	0	0
T30	587726	0	0	0
T31	5891	0	0	0
T32	578664	0	0	0
T33	164892	0	0	0
T34	0	14	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3084	0	0
T16	325643	18	0	0
T17	880795	2	0	0
T18	0	44	0	0
T19	0	23	0	0
T20	0	17	0	0
T21	0	14	0	0
T22	0	23	0	0
T23	0	10	0	0
T24	0	24	0	0
T25	0	21	0	0
T26	708554	0	0	0
T27	156657	0	0	0
T28	74483	0	0	0
T29	353966	0	0	0
T30	587726	0	0	0
T31	5891	0	0	0
T32	578664	0	0	0
T33	164892	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2745	0	0
T17	880795	9	0	0
T18	0	40	0	0
T19	0	48	0	0
T20	0	13	0	0
T22	0	20	0	0
T23	0	15	0	0
T24	0	19	0	0
T25	0	13	0	0
T34	0	24	0	0
T35	0	29	0	0
T36	171976	0	0	0
T37	330436	0	0	0
T38	11053	0	0	0
T39	69025	0	0	0
T40	174736	0	0	0
T41	130546	0	0	0
T42	21609	0	0	0
T43	158247	0	0	0
T44	313554	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2683	0	0
T16	325643	39	0	0
T17	880795	13	0	0
T18	0	24	0	0
T19	0	38	0	0
T20	0	12	0	0
T21	0	3	0	0
T22	0	27	0	0
T23	0	7	0	0
T24	0	19	0	0
T25	0	26	0	0
T26	708554	0	0	0
T27	156657	0	0	0
T28	74483	0	0	0
T29	353966	0	0	0
T30	587726	0	0	0
T31	5891	0	0	0
T32	578664	0	0	0
T33	164892	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3155	0	0
T16	325643	20	0	0
T17	880795	9	0	0
T18	0	38	0	0
T19	0	31	0	0
T20	0	23	0	0
T22	0	31	0	0
T23	0	18	0	0
T24	0	15	0	0
T25	0	16	0	0
T26	708554	0	0	0
T27	156657	0	0	0
T28	74483	0	0	0
T29	353966	0	0	0
T30	587726	0	0	0
T31	5891	0	0	0
T32	578664	0	0	0
T33	164892	0	0	0
T34	0	14	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2632	0	0
T16	325643	14	0	0
T17	880795	16	0	0
T18	0	28	0	0
T19	0	32	0	0
T20	0	22	0	0
T21	0	16	0	0
T22	0	16	0	0
T23	0	16	0	0
T24	0	24	0	0
T25	0	14	0	0
T26	708554	0	0	0
T27	156657	0	0	0
T28	74483	0	0	0
T29	353966	0	0	0
T30	587726	0	0	0
T31	5891	0	0	0
T32	578664	0	0	0
T33	164892	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2827	0	0
T16	325643	26	0	0
T17	880795	19	0	0
T18	0	30	0	0
T19	0	49	0	0
T20	0	28	0	0
T21	0	8	0	0
T22	0	14	0	0
T23	0	16	0	0
T24	0	24	0	0
T25	0	13	0	0
T26	708554	0	0	0
T27	156657	0	0	0
T28	74483	0	0	0
T29	353966	0	0	0
T30	587726	0	0	0
T31	5891	0	0	0
T32	578664	0	0	0
T33	164892	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2471	0	0
T16	325643	24	0	0
T17	880795	9	0	0
T18	0	15	0	0
T19	0	33	0	0
T20	0	17	0	0
T22	0	19	0	0
T23	0	17	0	0
T24	0	16	0	0
T25	0	17	0	0
T26	708554	0	0	0
T27	156657	0	0	0
T28	74483	0	0	0
T29	353966	0	0	0
T30	587726	0	0	0
T31	5891	0	0	0
T32	578664	0	0	0
T33	164892	0	0	0
T34	0	13	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2599	0	0
T16	325643	39	0	0
T17	880795	13	0	0
T18	0	31	0	0
T19	0	26	0	0
T20	0	25	0	0
T22	0	22	0	0
T23	0	26	0	0
T24	0	28	0	0
T25	0	14	0	0
T26	708554	0	0	0
T27	156657	0	0	0
T28	74483	0	0	0
T29	353966	0	0	0
T30	587726	0	0	0
T31	5891	0	0	0
T32	578664	0	0	0
T33	164892	0	0	0
T34	0	21	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3375	0	0
T16	325643	21	0	0
T17	880795	34	0	0
T18	0	68	0	0
T19	0	53	0	0
T20	0	18	0	0
T21	0	9	0	0
T22	0	25	0	0
T23	0	6	0	0
T26	708554	0	0	0
T27	156657	0	0	0
T28	74483	0	0	0
T29	353966	0	0	0
T30	587726	0	0	0
T31	5891	0	0	0
T32	578664	0	0	0
T33	164892	0	0	0
T45	0	17	0	0
T46	0	17	0	0