Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_adc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1206448	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1177978

1

T1

486

T2

458

T3

63

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2090049	1			T1	838		T2	850		T3	81
values[0x0]	146617	1			T1	53		T2	48		T3	41
values[0x1]	147760	1			T1	44		T2	39		T3	22

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	967115	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1417311

1

T1

576

T2

554

T3

75

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7488	1			T1	2		T4	1		T6	1
valid_sources[0x01]	7225	1			T1	6		T4	5		T6	1
valid_sources[0x02]	7008	1			T3	1		T4	3		T5	1
valid_sources[0x03]	11529	1			T1	3		T4	4		T5	2
valid_sources[0x04]	7456	1			T3	1		T4	9		T5	1
valid_sources[0x05]	7268	1			T1	7		T3	1		T4	8
valid_sources[0x06]	16137	1			T1	9		T5	2		T6	3
valid_sources[0x07]	7460	1			T4	2		T5	1		T6	4
valid_sources[0x08]	7160	1			T1	2		T3	1		T4	5
valid_sources[0x09]	11131	1			T3	1		T6	5		T8	3
valid_sources[0x0a]	7311	1			T1	7		T3	2		T4	1
valid_sources[0x0b]	7035	1			T1	13		T3	1		T4	1
valid_sources[0x0c]	7941	1			T1	5		T4	2		T6	3
valid_sources[0x0d]	8324	1			T1	5		T4	5		T8	969
valid_sources[0x0e]	7038	1			T1	2		T4	3		T6	3
valid_sources[0x0f]	7349	1			T1	17		T6	12		T8	21
valid_sources[0x10]	12291	1			T6	2		T8	4		T9	32
valid_sources[0x11]	14079	1			T3	1		T4	7		T5	7
valid_sources[0x12]	6848	1			T6	10		T8	3		T9	22
valid_sources[0x13]	9629	1			T3	5		T4	3		T8	3
valid_sources[0x14]	16200	1			T4	6		T8	5		T9	43
valid_sources[0x15]	7412	1			T1	5		T4	2		T8	1
valid_sources[0x16]	7518	1			T4	4		T5	1		T8	20
valid_sources[0x17]	12387	1			T4	13		T6	8		T8	7
valid_sources[0x18]	7129	1			T1	9		T3	1		T5	2
valid_sources[0x19]	11825	1			T4	5		T6	2		T8	3
valid_sources[0x1a]	7029	1			T1	7		T4	3		T8	29
valid_sources[0x1b]	7282	1			T1	1		T4	2		T6	1
valid_sources[0x1c]	12803	1			T1	2		T4	7		T5	1
valid_sources[0x1d]	7051	1			T3	2		T4	3		T5	1
valid_sources[0x1e]	9524	1			T1	4		T3	1		T8	9
valid_sources[0x1f]	7045	1			T1	6		T4	3		T5	1
valid_sources[0x20]	11426	1			T1	5		T4	3		T8	3
valid_sources[0x21]	15638	1			T1	17		T3	1		T4	1
valid_sources[0x22]	6821	1			T1	2		T4	4		T6	6
valid_sources[0x23]	12562	1			T4	1		T8	3		T9	32
valid_sources[0x24]	11129	1			T1	18		T4	3		T6	5
valid_sources[0x25]	7464	1			T1	1		T4	11		T6	1
valid_sources[0x26]	12419	1			T4	1		T6	2		T8	6
valid_sources[0x27]	7176	1			T1	1		T4	3		T5	1
valid_sources[0x28]	11754	1			T1	12		T8	12		T9	16
valid_sources[0x29]	8294	1			T1	7		T4	4		T9	22
valid_sources[0x2a]	6895	1			T4	8		T5	1		T8	28
valid_sources[0x2b]	7012	1			T1	10		T2	1		T3	1
valid_sources[0x2c]	8586	1			T1	5		T3	1		T4	5
valid_sources[0x2d]	7621	1			T1	5		T6	2		T8	4
valid_sources[0x2e]	11360	1			T4	2		T8	13		T9	29
valid_sources[0x2f]	8432	1			T1	16		T4	4		T6	1
valid_sources[0x30]	12327	1			T4	2		T6	4		T8	4
valid_sources[0x31]	7409	1			T1	5		T3	1		T4	2
valid_sources[0x32]	7794	1			T4	8		T5	2		T6	5
valid_sources[0x33]	7941	1			T1	9		T3	1		T6	18
valid_sources[0x34]	8251	1			T1	9		T3	1		T4	17
valid_sources[0x35]	19896	1			T1	6		T3	1		T4	5
valid_sources[0x36]	11467	1			T4	4		T5	1		T6	6
valid_sources[0x37]	7150	1			T1	18		T3	1		T4	4
valid_sources[0x38]	9308	1			T4	3		T5	1		T8	6
valid_sources[0x39]	7102	1			T1	9		T4	4		T5	1
valid_sources[0x3a]	8892	1			T1	4		T3	1		T4	2
valid_sources[0x3b]	7219	1			T1	7		T4	7		T5	1
valid_sources[0x3c]	7147	1			T4	4		T6	2		T8	7
valid_sources[0x3d]	7158	1			T3	1		T6	6		T8	4
valid_sources[0x3e]	8352	1			T3	1		T5	2		T8	6
valid_sources[0x3f]	7372	1			T4	8		T6	1		T8	3
valid_sources[0x40]	7031	1			T1	2		T3	2		T4	1
valid_sources[0x41]	9087	1			T4	3		T6	1		T8	2
valid_sources[0x42]	7341	1			T1	2		T4	1		T9	48
valid_sources[0x43]	7191	1			T1	5		T6	3		T8	4
valid_sources[0x44]	9062	1			T3	1		T4	8		T5	1
valid_sources[0x45]	12151	1			T1	6		T3	2		T5	1
valid_sources[0x46]	11524	1			T1	18		T4	1		T5	1
valid_sources[0x47]	8250	1			T1	8		T4	5		T8	3
valid_sources[0x48]	8211	1			T1	8		T4	4		T6	2
valid_sources[0x49]	7234	1			T1	9		T4	1		T6	8
valid_sources[0x4a]	10318	1			T1	6		T4	2		T6	3
valid_sources[0x4b]	21970	1			T1	7		T4	2		T5	1
valid_sources[0x4c]	6820	1			T3	2		T4	16		T6	2
valid_sources[0x4d]	7021	1			T1	25		T3	2		T5	1
valid_sources[0x4e]	8505	1			T4	4		T5	1		T8	6
valid_sources[0x4f]	7251	1			T1	12		T3	1		T5	1
valid_sources[0x50]	20015	1			T1	28		T8	5		T9	30
valid_sources[0x51]	15556	1			T4	7		T5	4		T8	2
valid_sources[0x52]	10668	1			T6	3		T8	56		T9	60
valid_sources[0x53]	6848	1			T1	4		T4	2		T6	1
valid_sources[0x54]	7389	1			T1	10		T4	5		T6	3
valid_sources[0x55]	11826	1			T4	2		T6	4		T8	10
valid_sources[0x56]	8471	1			T1	6		T4	2		T8	4
valid_sources[0x57]	7193	1			T4	4		T8	11		T9	42
valid_sources[0x58]	10273	1			T1	15		T4	6		T6	1
valid_sources[0x59]	12743	1			T1	4		T6	7		T8	2
valid_sources[0x5a]	7704	1			T6	918		T8	1		T9	48
valid_sources[0x5b]	7551	1			T1	2		T4	6		T5	1
valid_sources[0x5c]	7174	1			T3	2		T4	7		T8	4
valid_sources[0x5d]	11458	1			T1	24		T3	1		T4	2
valid_sources[0x5e]	9790	1			T1	11		T3	1		T4	9
valid_sources[0x5f]	11662	1			T3	3		T4	3		T8	5
valid_sources[0x60]	7770	1			T1	2		T4	6		T6	1
valid_sources[0x61]	12779	1			T1	1		T4	1		T6	2
valid_sources[0x62]	8673	1			T1	15		T4	2		T5	4
valid_sources[0x63]	7289	1			T4	1		T6	11		T8	4
valid_sources[0x64]	12441	1			T3	1		T4	6		T8	39
valid_sources[0x65]	7895	1			T1	3		T3	1		T8	6
valid_sources[0x66]	6805	1			T3	1		T4	8		T5	5
valid_sources[0x67]	10774	1			T1	1		T4	4		T5	1
valid_sources[0x68]	8176	1			T3	1		T4	1		T6	7
valid_sources[0x69]	9344	1			T3	1		T4	4		T6	3
valid_sources[0x6a]	6929	1			T3	2		T4	7		T5	1
valid_sources[0x6b]	8994	1			T4	3		T5	4		T8	7
valid_sources[0x6c]	7318	1			T1	2		T4	10		T6	8
valid_sources[0x6d]	16532	1			T1	1		T3	1		T4	8
valid_sources[0x6e]	7669	1			T3	1		T4	1		T5	1
valid_sources[0x6f]	7564	1			T4	7		T6	4		T8	3
valid_sources[0x70]	11217	1			T1	2		T3	3		T4	5
valid_sources[0x71]	12802	1			T4	2		T6	4		T7	833
valid_sources[0x72]	7946	1			T3	1		T4	2		T8	1
valid_sources[0x73]	7477	1			T1	4		T3	2		T4	4
valid_sources[0x74]	11322	1			T1	11		T4	3		T6	7
valid_sources[0x75]	8346	1			T5	1		T8	2		T9	34
valid_sources[0x76]	13176	1			T1	6		T4	1		T6	3
valid_sources[0x77]	7596	1			T3	1		T4	2		T6	5
valid_sources[0x78]	7124	1			T1	4		T3	1		T4	3
valid_sources[0x79]	11432	1			T3	1		T4	3		T8	7
valid_sources[0x7a]	7155	1			T1	3		T4	6		T5	1
valid_sources[0x7b]	7098	1			T1	1		T3	2		T4	6
valid_sources[0x7c]	8273	1			T1	1		T6	25		T8	3
valid_sources[0x7d]	20145	1			T4	8		T5	1		T6	7
valid_sources[0x7e]	6948	1			T4	3		T5	2		T6	2
valid_sources[0x7f]	7114	1			T4	3		T8	1		T9	24
valid_sources[0x80]	7041	1			T4	10		T5	1		T6	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1039879

1

T1

443

T2

414

T3

42

values[0x0]

all_enables

biggest_size

80052

1

T1

28

T2

30

T3

18

values[0x1]

all_enables

biggest_size

58047

1

T1

15

T2

14

T3

3