Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_fsm_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	86.67	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_fsm_reset_cg_inst	86.67	1	100	1	64	64

---

Group Instance : adc_ctrl_fsm_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
86.67	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_fsm_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	6	39	86.67

Variables for Group Instance adc_ctrl_fsm_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	5	11	68.75	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	28018	1			T1	8		T2	10		T4	6
auto[PWRUP]	114	1			T7	2		T37	2		T53	1
auto[ONEST_0]	77	1			T7	1		T37	2		T52	1
auto[ONEST_021]	15	1			T7	1		T116	1		T248	1
auto[ONEST_1]	101	1			T37	2		T50	2		T175	1
auto[ONEST_DONE]	6	1			T169	1		T249	1		T250	1
auto[LP_0]	107	1			T7	2		T37	1		T52	2
auto[LP_021]	37	1			T37	1		T52	1		T50	1
auto[LP_1]	144	1			T6	2		T7	4		T37	4
auto[LP_EVAL]	67	1			T6	1		T53	2		T50	3
auto[LP_SLP]	478	1			T6	2		T7	3		T37	5
auto[LP_PWRUP]	28	1			T37	1		T53	1		T52	1
auto[NP_0]	126	1			T37	1		T52	1		T50	5
auto[NP_021]	26	1			T6	1		T50	3		T51	1
auto[NP_1]	187	1			T6	1		T37	3		T53	1
auto[NP_EVAL]	31	1			T37	1		T50	1		T55	2

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

8

1

T7

1

T251

1

T252

1

min

27537

1

T1

8

T2

10

T4

6

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27543	1			T1	8		T2	10		T4	6
pow[0x1]	4	1			T50	1		T169	1		T253	1
pow[0x2]	19	1			T175	2		T29	1		T170	1
pow[0x3]	35	1			T55	1		T254	1		T56	2
pow[0x4]	77	1			T37	1		T51	2		T54	2
pow[0x5]	140	1			T53	2		T52	1		T50	5
pow[0x6]	243	1			T7	2		T37	1		T53	3
pow[0x7]	508	1			T6	3		T7	2		T37	4

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

183

1

T6

1

T37

3

T53

2

min

27075

1

T1

8

T2

10

T4

6

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	5	11	68.75

User Defined Bins for np_sample_cnt_pow_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
pow[0x1]	0	1	1
pow[0x2]	0	1	1
pow[0x3]	0	1	1
pow[0x4]	0	1	1
pow[0x6]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	27076	1			T1	8		T2	10		T4	6
pow[0x5]	1	1			T255	1		-	-		-	-
pow[0x7]	3	1			T192	1		T256	1		T257	1
pow[0x8]	3	1			T51	1		T258	1		T255	1
pow[0x9]	8	1			T15	1		T116	1		T106	1
pow[0xa]	16	1			T7	1		T52	1		T259	1
pow[0xb]	27	1			T53	1		T259	1		T251	1
pow[0xc]	72	1			T37	1		T53	1		T50	2
pow[0xd]	130	1			T7	4		T37	2		T53	1
pow[0xe]	285	1			T6	2		T7	1		T37	3
pow[0xf]	585	1			T6	5		T7	4		T37	6