Unified Coverage Report :: Group :: tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

Group : tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_cov_if::adc_ctrl_hw_reset_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
97.78	97.78	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_cov_0/adc_ctrl_core_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
adc_ctrl_hw_reset_cg_inst	97.78	1	100	1	64	64

---

Group Instance : adc_ctrl_hw_reset_cg_inst

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
97.78	1	100	1	64	64

---

Summary for Group Instance adc_ctrl_hw_reset_cg_inst

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	45	1	44	97.78

Variables for Group Instance adc_ctrl_hw_reset_cg_inst

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
fsm_state_cp	17	1	16	94.12	100	1	1	0
lp_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
lp_sample_cnt_pow_cp	8	0	8	100.00	100	1	1	0
np_sample_cnt_min_max_cp	2	0	2	100.00	100	1	1	0
np_sample_cnt_pow_cp	16	0	16	100.00	100	1	1	0

Summary for Variable fsm_state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	17	1	16	94.12

Automatically Generated Bins for fsm_state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[NP_DONE]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[PWRDN]	2267	1			T6	17		T7	13		T10	4
auto[PWRUP]	133	1			T6	1		T7	2		T37	1
auto[ONEST_0]	82	1			T7	1		T37	3		T53	2
auto[ONEST_021]	26	1			T55	1		T56	1		T35	1
auto[ONEST_1]	105	1			T6	1		T37	1		T53	1
auto[ONEST_DONE]	5	1			T7	1		T248	1		T377	1
auto[LP_0]	147	1			T7	4		T53	2		T52	2
auto[LP_021]	27	1			T7	1		T50	1		T54	1
auto[LP_1]	143	1			T6	3		T7	1		T37	2
auto[LP_EVAL]	50	1			T50	1		T55	2		T54	1
auto[LP_SLP]	522	1			T6	4		T7	8		T37	2
auto[LP_PWRUP]	28	1			T37	1		T53	1		T245	1
auto[NP_0]	244	1			T6	6		T37	2		T52	2
auto[NP_021]	55	1			T52	1		T55	1		T175	1
auto[NP_1]	236	1			T6	2		T7	1		T53	2
auto[NP_EVAL]	34	1			T35	1		T29	1		T259	1

---

Summary for Variable lp_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for lp_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

9

1

T37

1

T175

1

T245

1

min

1965

1

T6

19

T7

10

T10

4

---

Summary for Variable lp_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for lp_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1976	1			T6	19		T7	10		T10	4
pow[0x1]	13	1			T52	1		T245	1		T251	1
pow[0x2]	23	1			T6	1		T54	1		T245	2
pow[0x3]	41	1			T55	2		T175	1		T254	1
pow[0x4]	71	1			T6	1		T52	1		T50	1
pow[0x5]	115	1			T52	4		T50	4		T51	1
pow[0x6]	255	1			T6	1		T7	7		T37	3
pow[0x7]	501	1			T6	4		T7	6		T37	3

---

Summary for Variable np_sample_cnt_min_max_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for np_sample_cnt_min_max_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max

226

1

T6

3

T7

1

T37

5

min

1347

1

T6

12

T7

1

T10

4

---

Summary for Variable np_sample_cnt_pow_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	16	0	16	100.00

User Defined Bins for np_sample_cnt_pow_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
pow[0x0]	1351	1			T6	12		T7	1		T10	4
pow[0x1]	16	1			T35	6		T40	3		T295	1
pow[0x2]	29	1			T6	2		T36	2		T29	2
pow[0x3]	56	1			T39	1		T43	1		T44	1
pow[0x4]	54	1			T39	2		T14	3		T28	3
pow[0x5]	1	1			T378	1		-	-		-	-
pow[0x6]	1	1			T97	1		-	-		-	-
pow[0x7]	3	1			T169	1		T379	1		T377	1
pow[0x8]	5	1			T6	1		T37	1		T259	1
pow[0x9]	6	1			T6	1		T7	1		T249	1
pow[0xa]	15	1			T7	1		T55	1		T245	1
pow[0xb]	32	1			T52	1		T50	1		T245	1
pow[0xc]	87	1			T6	2		T7	1		T37	2
pow[0xd]	156	1			T7	4		T53	2		T52	4
pow[0xe]	288	1			T6	2		T7	5		T53	4
pow[0xf]	532	1			T6	4		T7	5		T37	6