Assert Coverage for Module :
adc_ctrl_fsm_sva
Assertion Details
FsmDebugOut_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
31405572 |
31327754 |
0 |
0 |
T1 |
32804 |
32724 |
0 |
0 |
T2 |
35883 |
35823 |
0 |
0 |
T3 |
1167 |
1071 |
0 |
0 |
T4 |
37972 |
37894 |
0 |
0 |
T5 |
1124 |
1062 |
0 |
0 |
T6 |
137 |
1 |
0 |
0 |
T7 |
95 |
1 |
0 |
0 |
T8 |
122634 |
122564 |
0 |
0 |
T9 |
100917 |
100863 |
0 |
0 |
T13 |
88 |
1 |
0 |
0 |
FsmStateHwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1106 |
1106 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
2 |
2 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
FsmStateSwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
31405572 |
6504 |
0 |
0 |
T1 |
32804 |
8 |
0 |
0 |
T2 |
35883 |
10 |
0 |
0 |
T3 |
1167 |
0 |
0 |
0 |
T4 |
37972 |
6 |
0 |
0 |
T5 |
1124 |
0 |
0 |
0 |
T6 |
137 |
0 |
0 |
0 |
T7 |
95 |
0 |
0 |
0 |
T8 |
122634 |
20 |
0 |
0 |
T9 |
100917 |
22 |
0 |
0 |
T10 |
0 |
13 |
0 |
0 |
T11 |
0 |
16 |
0 |
0 |
T12 |
0 |
14 |
0 |
0 |
T13 |
88 |
0 |
0 |
0 |
T38 |
0 |
7 |
0 |
0 |
T45 |
0 |
17 |
0 |
0 |
LpSampleCntHwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1106 |
1106 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
2 |
2 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
LpSampleCntSwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
31405572 |
6504 |
0 |
0 |
T1 |
32804 |
8 |
0 |
0 |
T2 |
35883 |
10 |
0 |
0 |
T3 |
1167 |
0 |
0 |
0 |
T4 |
37972 |
6 |
0 |
0 |
T5 |
1124 |
0 |
0 |
0 |
T6 |
137 |
0 |
0 |
0 |
T7 |
95 |
0 |
0 |
0 |
T8 |
122634 |
20 |
0 |
0 |
T9 |
100917 |
22 |
0 |
0 |
T10 |
0 |
13 |
0 |
0 |
T11 |
0 |
16 |
0 |
0 |
T12 |
0 |
14 |
0 |
0 |
T13 |
88 |
0 |
0 |
0 |
T38 |
0 |
7 |
0 |
0 |
T45 |
0 |
17 |
0 |
0 |
NpSampleCntHwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1106 |
1106 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
2 |
2 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
NpSampleCntSwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
31405572 |
6504 |
0 |
0 |
T1 |
32804 |
8 |
0 |
0 |
T2 |
35883 |
10 |
0 |
0 |
T3 |
1167 |
0 |
0 |
0 |
T4 |
37972 |
6 |
0 |
0 |
T5 |
1124 |
0 |
0 |
0 |
T6 |
137 |
0 |
0 |
0 |
T7 |
95 |
0 |
0 |
0 |
T8 |
122634 |
20 |
0 |
0 |
T9 |
100917 |
22 |
0 |
0 |
T10 |
0 |
13 |
0 |
0 |
T11 |
0 |
16 |
0 |
0 |
T12 |
0 |
14 |
0 |
0 |
T13 |
88 |
0 |
0 |
0 |
T38 |
0 |
7 |
0 |
0 |
T45 |
0 |
17 |
0 |
0 |
PwrupTimerCntHwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1106 |
1106 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
2 |
2 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
PwrupTimerCntSwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
31405572 |
6504 |
0 |
0 |
T1 |
32804 |
8 |
0 |
0 |
T2 |
35883 |
10 |
0 |
0 |
T3 |
1167 |
0 |
0 |
0 |
T4 |
37972 |
6 |
0 |
0 |
T5 |
1124 |
0 |
0 |
0 |
T6 |
137 |
0 |
0 |
0 |
T7 |
95 |
0 |
0 |
0 |
T8 |
122634 |
20 |
0 |
0 |
T9 |
100917 |
22 |
0 |
0 |
T10 |
0 |
13 |
0 |
0 |
T11 |
0 |
16 |
0 |
0 |
T12 |
0 |
14 |
0 |
0 |
T13 |
88 |
0 |
0 |
0 |
T38 |
0 |
7 |
0 |
0 |
T45 |
0 |
17 |
0 |
0 |
WakeupTimerCntHwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1106 |
1106 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
2 |
2 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T13 |
1 |
1 |
0 |
0 |
WakeupTimerCntSwReset_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
31405572 |
6504 |
0 |
0 |
T1 |
32804 |
8 |
0 |
0 |
T2 |
35883 |
10 |
0 |
0 |
T3 |
1167 |
0 |
0 |
0 |
T4 |
37972 |
6 |
0 |
0 |
T5 |
1124 |
0 |
0 |
0 |
T6 |
137 |
0 |
0 |
0 |
T7 |
95 |
0 |
0 |
0 |
T8 |
122634 |
20 |
0 |
0 |
T9 |
100917 |
22 |
0 |
0 |
T10 |
0 |
13 |
0 |
0 |
T11 |
0 |
16 |
0 |
0 |
T12 |
0 |
14 |
0 |
0 |
T13 |
88 |
0 |
0 |
0 |
T38 |
0 |
7 |
0 |
0 |
T45 |
0 |
17 |
0 |
0 |