Unified Coverage Report :: Module :: adc_ctrl_csr_assert_fpv

Module : adc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_adc_ctrl_csr_assert_0/adc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.adc_ctrl_csr_assert	96.00						96.00

---

Module Instance : tb.dut.adc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.00						96.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : adc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	24	96.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	24	96.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2147483647	0	0	0
adc_chn0_filter_ctl_0_rd_A	2147483647	2215	0	0
adc_chn0_filter_ctl_1_rd_A	2147483647	2029	0	0
adc_chn0_filter_ctl_2_rd_A	2147483647	2045	0	0
adc_chn0_filter_ctl_3_rd_A	2147483647	2192	0	0
adc_chn0_filter_ctl_4_rd_A	2147483647	2067	0	0
adc_chn0_filter_ctl_5_rd_A	2147483647	2119	0	0
adc_chn0_filter_ctl_6_rd_A	2147483647	2063	0	0
adc_chn0_filter_ctl_7_rd_A	2147483647	2248	0	0
adc_chn1_filter_ctl_0_rd_A	2147483647	2237	0	0
adc_chn1_filter_ctl_1_rd_A	2147483647	2068	0	0
adc_chn1_filter_ctl_2_rd_A	2147483647	1968	0	0
adc_chn1_filter_ctl_3_rd_A	2147483647	2091	0	0
adc_chn1_filter_ctl_4_rd_A	2147483647	2093	0	0
adc_chn1_filter_ctl_5_rd_A	2147483647	2331	0	0
adc_chn1_filter_ctl_6_rd_A	2147483647	2102	0	0
adc_chn1_filter_ctl_7_rd_A	2147483647	2121	0	0
adc_en_ctl_rd_A	2147483647	1809	0	0
adc_fsm_rst_rd_A	2147483647	1472	0	0
adc_intr_ctl_rd_A	2147483647	1982	0	0
adc_lp_sample_ctl_rd_A	2147483647	1487	0	0
adc_pd_ctl_rd_A	2147483647	2075	0	0
adc_sample_ctl_rd_A	2147483647	1411	0	0
adc_wakeup_ctl_rd_A	2147483647	1650	0	0
intr_enable_rd_A	2147483647	2072	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	0	0	0

adc_chn0_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2215	0	0
T14	259840	17	0	0
T15	0	37	0	0
T16	0	21	0	0
T17	0	35	0	0
T18	0	30	0	0
T19	0	20	0	0
T20	0	31	0	0
T21	0	41	0	0
T22	0	30	0	0
T23	0	10	0	0
T24	122620	0	0	0
T25	166362	0	0	0
T26	576554	0	0	0
T27	327917	0	0	0
T28	283158	0	0	0
T29	171720	0	0	0
T30	281711	0	0	0
T31	9564	0	0	0
T32	194252	0	0	0

adc_chn0_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2029	0	0
T14	259840	8	0	0
T15	0	34	0	0
T16	0	19	0	0
T17	0	29	0	0
T18	0	16	0	0
T19	0	16	0	0
T20	0	37	0	0
T21	0	35	0	0
T22	0	42	0	0
T23	0	30	0	0
T24	122620	0	0	0
T25	166362	0	0	0
T26	576554	0	0	0
T27	327917	0	0	0
T28	283158	0	0	0
T29	171720	0	0	0
T30	281711	0	0	0
T31	9564	0	0	0
T32	194252	0	0	0

adc_chn0_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2045	0	0
T14	259840	16	0	0
T15	0	36	0	0
T16	0	7	0	0
T17	0	45	0	0
T18	0	8	0	0
T19	0	17	0	0
T20	0	34	0	0
T21	0	25	0	0
T22	0	47	0	0
T23	0	14	0	0
T24	122620	0	0	0
T25	166362	0	0	0
T26	576554	0	0	0
T27	327917	0	0	0
T28	283158	0	0	0
T29	171720	0	0	0
T30	281711	0	0	0
T31	9564	0	0	0
T32	194252	0	0	0

adc_chn0_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2192	0	0
T14	259840	7	0	0
T15	0	27	0	0
T16	0	13	0	0
T17	0	29	0	0
T18	0	15	0	0
T19	0	20	0	0
T20	0	27	0	0
T21	0	48	0	0
T22	0	23	0	0
T23	0	17	0	0
T24	122620	0	0	0
T25	166362	0	0	0
T26	576554	0	0	0
T27	327917	0	0	0
T28	283158	0	0	0
T29	171720	0	0	0
T30	281711	0	0	0
T31	9564	0	0	0
T32	194252	0	0	0

adc_chn0_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2067	0	0
T14	259840	10	0	0
T15	0	39	0	0
T16	0	1	0	0
T17	0	34	0	0
T18	0	14	0	0
T19	0	20	0	0
T20	0	41	0	0
T21	0	26	0	0
T22	0	42	0	0
T23	0	16	0	0
T24	122620	0	0	0
T25	166362	0	0	0
T26	576554	0	0	0
T27	327917	0	0	0
T28	283158	0	0	0
T29	171720	0	0	0
T30	281711	0	0	0
T31	9564	0	0	0
T32	194252	0	0	0

adc_chn0_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2119	0	0
T14	259840	34	0	0
T15	0	31	0	0
T16	0	23	0	0
T17	0	21	0	0
T18	0	32	0	0
T19	0	24	0	0
T20	0	49	0	0
T21	0	34	0	0
T22	0	36	0	0
T23	0	31	0	0
T24	122620	0	0	0
T25	166362	0	0	0
T26	576554	0	0	0
T27	327917	0	0	0
T28	283158	0	0	0
T29	171720	0	0	0
T30	281711	0	0	0
T31	9564	0	0	0
T32	194252	0	0	0

adc_chn0_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2063	0	0
T14	259840	13	0	0
T15	0	19	0	0
T16	0	14	0	0
T17	0	21	0	0
T18	0	23	0	0
T19	0	8	0	0
T20	0	27	0	0
T21	0	28	0	0
T22	0	40	0	0
T23	0	17	0	0
T24	122620	0	0	0
T25	166362	0	0	0
T26	576554	0	0	0
T27	327917	0	0	0
T28	283158	0	0	0
T29	171720	0	0	0
T30	281711	0	0	0
T31	9564	0	0	0
T32	194252	0	0	0

adc_chn0_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2248	0	0
T14	259840	26	0	0
T15	0	22	0	0
T16	0	29	0	0
T17	0	37	0	0
T18	0	10	0	0
T19	0	16	0	0
T20	0	47	0	0
T21	0	25	0	0
T22	0	49	0	0
T23	0	20	0	0
T24	122620	0	0	0
T25	166362	0	0	0
T26	576554	0	0	0
T27	327917	0	0	0
T28	283158	0	0	0
T29	171720	0	0	0
T30	281711	0	0	0
T31	9564	0	0	0
T32	194252	0	0	0

adc_chn1_filter_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2237	0	0
T14	259840	24	0	0
T15	0	39	0	0
T16	0	13	0	0
T17	0	32	0	0
T18	0	11	0	0
T19	0	16	0	0
T20	0	37	0	0
T21	0	55	0	0
T22	0	31	0	0
T23	0	24	0	0
T24	122620	0	0	0
T25	166362	0	0	0
T26	576554	0	0	0
T27	327917	0	0	0
T28	283158	0	0	0
T29	171720	0	0	0
T30	281711	0	0	0
T31	9564	0	0	0
T32	194252	0	0	0

adc_chn1_filter_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2068	0	0
T14	259840	19	0	0
T15	0	21	0	0
T16	0	13	0	0
T17	0	36	0	0
T18	0	13	0	0
T19	0	18	0	0
T20	0	38	0	0
T21	0	24	0	0
T22	0	13	0	0
T23	0	17	0	0
T24	122620	0	0	0
T25	166362	0	0	0
T26	576554	0	0	0
T27	327917	0	0	0
T28	283158	0	0	0
T29	171720	0	0	0
T30	281711	0	0	0
T31	9564	0	0	0
T32	194252	0	0	0

adc_chn1_filter_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1968	0	0
T14	259840	30	0	0
T15	0	33	0	0
T16	0	10	0	0
T17	0	40	0	0
T18	0	7	0	0
T19	0	11	0	0
T20	0	24	0	0
T21	0	32	0	0
T22	0	37	0	0
T23	0	13	0	0
T24	122620	0	0	0
T25	166362	0	0	0
T26	576554	0	0	0
T27	327917	0	0	0
T28	283158	0	0	0
T29	171720	0	0	0
T30	281711	0	0	0
T31	9564	0	0	0
T32	194252	0	0	0

adc_chn1_filter_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2091	0	0
T14	259840	12	0	0
T15	0	34	0	0
T16	0	5	0	0
T17	0	27	0	0
T18	0	4	0	0
T19	0	16	0	0
T20	0	26	0	0
T21	0	28	0	0
T22	0	29	0	0
T23	0	15	0	0
T24	122620	0	0	0
T25	166362	0	0	0
T26	576554	0	0	0
T27	327917	0	0	0
T28	283158	0	0	0
T29	171720	0	0	0
T30	281711	0	0	0
T31	9564	0	0	0
T32	194252	0	0	0

adc_chn1_filter_ctl_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2093	0	0
T14	259840	20	0	0
T15	0	28	0	0
T16	0	18	0	0
T17	0	36	0	0
T18	0	19	0	0
T19	0	4	0	0
T20	0	22	0	0
T21	0	30	0	0
T22	0	29	0	0
T23	0	28	0	0
T24	122620	0	0	0
T25	166362	0	0	0
T26	576554	0	0	0
T27	327917	0	0	0
T28	283158	0	0	0
T29	171720	0	0	0
T30	281711	0	0	0
T31	9564	0	0	0
T32	194252	0	0	0

adc_chn1_filter_ctl_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2331	0	0
T14	259840	24	0	0
T15	0	43	0	0
T16	0	26	0	0
T17	0	23	0	0
T18	0	13	0	0
T19	0	11	0	0
T20	0	34	0	0
T21	0	25	0	0
T22	0	46	0	0
T23	0	18	0	0
T24	122620	0	0	0
T25	166362	0	0	0
T26	576554	0	0	0
T27	327917	0	0	0
T28	283158	0	0	0
T29	171720	0	0	0
T30	281711	0	0	0
T31	9564	0	0	0
T32	194252	0	0	0

adc_chn1_filter_ctl_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2102	0	0
T14	259840	9	0	0
T15	0	30	0	0
T16	0	3	0	0
T17	0	26	0	0
T18	0	7	0	0
T19	0	3	0	0
T20	0	46	0	0
T21	0	48	0	0
T22	0	39	0	0
T23	0	25	0	0
T24	122620	0	0	0
T25	166362	0	0	0
T26	576554	0	0	0
T27	327917	0	0	0
T28	283158	0	0	0
T29	171720	0	0	0
T30	281711	0	0	0
T31	9564	0	0	0
T32	194252	0	0	0

adc_chn1_filter_ctl_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2121	0	0
T14	259840	28	0	0
T15	0	25	0	0
T16	0	13	0	0
T17	0	36	0	0
T18	0	6	0	0
T19	0	18	0	0
T20	0	38	0	0
T21	0	34	0	0
T22	0	28	0	0
T23	0	15	0	0
T24	122620	0	0	0
T25	166362	0	0	0
T26	576554	0	0	0
T27	327917	0	0	0
T28	283158	0	0	0
T29	171720	0	0	0
T30	281711	0	0	0
T31	9564	0	0	0
T32	194252	0	0	0

adc_en_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1809	0	0
T14	259840	24	0	0
T15	0	37	0	0
T16	0	14	0	0
T17	0	45	0	0
T18	0	16	0	0
T19	0	17	0	0
T20	0	34	0	0
T21	0	31	0	0
T22	0	40	0	0
T23	0	11	0	0
T24	122620	0	0	0
T25	166362	0	0	0
T26	576554	0	0	0
T27	327917	0	0	0
T28	283158	0	0	0
T29	171720	0	0	0
T30	281711	0	0	0
T31	9564	0	0	0
T32	194252	0	0	0

adc_fsm_rst_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1472	0	0
T14	259840	22	0	0
T15	0	33	0	0
T16	0	21	0	0
T17	0	31	0	0
T18	0	17	0	0
T19	0	4	0	0
T20	0	52	0	0
T21	0	35	0	0
T22	0	50	0	0
T23	0	14	0	0
T24	122620	0	0	0
T25	166362	0	0	0
T26	576554	0	0	0
T27	327917	0	0	0
T28	283158	0	0	0
T29	171720	0	0	0
T30	281711	0	0	0
T31	9564	0	0	0
T32	194252	0	0	0

adc_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1982	0	0
T14	259840	23	0	0
T15	0	31	0	0
T16	0	12	0	0
T17	0	56	0	0
T18	0	26	0	0
T19	0	25	0	0
T20	0	28	0	0
T21	0	29	0	0
T22	0	46	0	0
T23	0	15	0	0
T24	122620	0	0	0
T25	166362	0	0	0
T26	576554	0	0	0
T27	327917	0	0	0
T28	283158	0	0	0
T29	171720	0	0	0
T30	281711	0	0	0
T31	9564	0	0	0
T32	194252	0	0	0

adc_lp_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1487	0	0
T14	259840	11	0	0
T15	0	25	0	0
T16	0	12	0	0
T17	0	42	0	0
T18	0	7	0	0
T19	0	18	0	0
T20	0	34	0	0
T21	0	35	0	0
T22	0	36	0	0
T23	0	18	0	0
T24	122620	0	0	0
T25	166362	0	0	0
T26	576554	0	0	0
T27	327917	0	0	0
T28	283158	0	0	0
T29	171720	0	0	0
T30	281711	0	0	0
T31	9564	0	0	0
T32	194252	0	0	0

adc_pd_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2075	0	0
T14	259840	24	0	0
T15	0	32	0	0
T16	0	3	0	0
T17	0	46	0	0
T18	0	21	0	0
T19	0	22	0	0
T20	0	48	0	0
T21	0	37	0	0
T22	0	43	0	0
T23	0	20	0	0
T24	122620	0	0	0
T25	166362	0	0	0
T26	576554	0	0	0
T27	327917	0	0	0
T28	283158	0	0	0
T29	171720	0	0	0
T30	281711	0	0	0
T31	9564	0	0	0
T32	194252	0	0	0

adc_sample_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1411	0	0
T14	259840	6	0	0
T15	0	19	0	0
T16	0	8	0	0
T17	0	37	0	0
T18	0	15	0	0
T19	0	27	0	0
T20	0	27	0	0
T21	0	45	0	0
T22	0	30	0	0
T23	0	10	0	0
T24	122620	0	0	0
T25	166362	0	0	0
T26	576554	0	0	0
T27	327917	0	0	0
T28	283158	0	0	0
T29	171720	0	0	0
T30	281711	0	0	0
T31	9564	0	0	0
T32	194252	0	0	0

adc_wakeup_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1650	0	0
T14	259840	20	0	0
T15	0	37	0	0
T16	0	11	0	0
T17	0	37	0	0
T18	0	22	0	0
T19	0	14	0	0
T20	0	35	0	0
T21	0	33	0	0
T22	0	23	0	0
T23	0	4	0	0
T24	122620	0	0	0
T25	166362	0	0	0
T26	576554	0	0	0
T27	327917	0	0	0
T28	283158	0	0	0
T29	171720	0	0	0
T30	281711	0	0	0
T31	9564	0	0	0
T32	194252	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2072	0	0
T14	259840	52	0	0
T15	0	72	0	0
T16	0	21	0	0
T17	0	49	0	0
T18	0	19	0	0
T19	0	66	0	0
T20	0	33	0	0
T21	0	36	0	0
T24	122620	0	0	0
T25	166362	0	0	0
T26	576554	0	0	0
T27	327917	0	0	0
T28	283158	0	0	0
T29	171720	0	0	0
T30	281711	0	0	0
T31	9564	0	0	0
T32	194252	0	0	0
T33	0	26	0	0
T34	0	6	0	0