Unified Coverage Report :: Group :: adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

Group : adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_adc_ctrl_env_0.1/adc_ctrl_env_cov.sv

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Summary for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00

Variables for Group adc_ctrl_env_pkg::adc_ctrl_env_cov::adc_ctrl_testmode_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
testmode_cp	12	0	12	100.00	100	1	1	0

Summary for Variable testmode_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for testmode_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
testmodes[AdcCtrlTestmodeOneShot]	6867	1			T2	69		T4	69		T6	9
testmodes[AdcCtrlTestmodeNormal]	5462	1			T2	63		T3	3		T4	59
testmodes[AdcCtrlTestmodeLowpower]	5719	1			T1	1		T2	44		T4	57
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeOneShot]	3670	1			T2	30		T4	25		T6	4
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeNormal]	1761	1			T2	23		T4	23		T6	5
transitions[AdcCtrlTestmodeOneShot=>AdcCtrlTestmodeLowpower]	1325	1			T2	16		T4	21		T9	24
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeOneShot]	1750	1			T2	21		T4	24		T6	4
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeNormal]	2031	1			T2	24		T3	2		T4	18
transitions[AdcCtrlTestmodeNormal=>AdcCtrlTestmodeLowpower]	1350	1			T2	18		T4	16		T9	23
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeOneShot]	1338	1			T2	18		T4	20		T9	26
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeNormal]	1321	1			T2	16		T4	18		T9	22
transitions[AdcCtrlTestmodeLowpower=>AdcCtrlTestmodeLowpower]	2804	1			T2	9		T4	19		T5	1