---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.adc_ctrl_csr_assert.TlulOOBAddrErr_A	0	0	2147483647	0	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.BusySrcReqChk_A	0	0	2147483647	0	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.SrcAckBusyChk_A	0	0	2147483647	0	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34535855	0	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	0	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.BusySrcReqChk_A	0	0	2147483647	0	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.SrcAckBusyChk_A	0	0	2147483647	0	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34535855	0	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	0	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	34535855	0	0	918

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AdcKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.AlertsKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	2147483647	80	0	0
tb.dut.IntrKnown	0	0	2147483647	2147483647	0	0
tb.dut.TlOAReadyKnown	0	0	2147483647	2147483647	0	0
tb.dut.TlODValidKnown	0	0	2147483647	2147483647	0	0
tb.dut.WakeKnown	0	0	2147483647	2147483647	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_0_rd_A	0	0	2147483647	2398	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_1_rd_A	0	0	2147483647	2363	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_2_rd_A	0	0	2147483647	2434	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_3_rd_A	0	0	2147483647	2413	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_4_rd_A	0	0	2147483647	2344	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_5_rd_A	0	0	2147483647	2426	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_6_rd_A	0	0	2147483647	2284	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn0_filter_ctl_7_rd_A	0	0	2147483647	2430	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_0_rd_A	0	0	2147483647	2275	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_1_rd_A	0	0	2147483647	2435	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_2_rd_A	0	0	2147483647	2384	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_3_rd_A	0	0	2147483647	2373	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_4_rd_A	0	0	2147483647	2277	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_5_rd_A	0	0	2147483647	2328	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_6_rd_A	0	0	2147483647	2281	0	0
tb.dut.adc_ctrl_csr_assert.adc_chn1_filter_ctl_7_rd_A	0	0	2147483647	2291	0	0
tb.dut.adc_ctrl_csr_assert.adc_en_ctl_rd_A	0	0	2147483647	2096	0	0
tb.dut.adc_ctrl_csr_assert.adc_fsm_rst_rd_A	0	0	2147483647	1892	0	0
tb.dut.adc_ctrl_csr_assert.adc_intr_ctl_rd_A	0	0	2147483647	2462	0	0
tb.dut.adc_ctrl_csr_assert.adc_lp_sample_ctl_rd_A	0	0	2147483647	1894	0	0
tb.dut.adc_ctrl_csr_assert.adc_pd_ctl_rd_A	0	0	2147483647	2340	0	0
tb.dut.adc_ctrl_csr_assert.adc_sample_ctl_rd_A	0	0	2147483647	1826	0	0
tb.dut.adc_ctrl_csr_assert.adc_wakeup_ctl_rd_A	0	0	2147483647	2204	0	0
tb.dut.adc_ctrl_csr_assert.intr_enable_rd_A	0	0	2147483647	2560	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	2147483647	29908379	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	2147483647	2147483647	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	2147483647	5033136	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	2147483647	2147483647	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.tlul_assert_device.gen_assert_final[0].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[100].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[101].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[102].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[103].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[104].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[105].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[106].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[107].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[108].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[109].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[10].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[110].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[111].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[112].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[113].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[114].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[115].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[116].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[117].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[118].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[119].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[11].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[120].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[121].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[122].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[123].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[124].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[125].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[126].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[127].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[128].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[129].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[12].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[130].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[131].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[132].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[133].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[134].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[135].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[136].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[137].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[138].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[139].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[13].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[140].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[141].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[142].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[143].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[144].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[145].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[146].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[147].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[148].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[149].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[14].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[150].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[151].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[152].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[153].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[154].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[155].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[156].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[157].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[158].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[159].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[15].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[160].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[161].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[162].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[163].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[164].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[165].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[166].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[167].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[168].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[169].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[16].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[170].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[171].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[172].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[173].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[174].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[175].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[176].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[177].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[17].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[180].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[181].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[182].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[183].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[184].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[185].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[186].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[187].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[188].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[189].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[18].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[190].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[192].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[199].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[19].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[1].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[200].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[201].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[202].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[203].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[204].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[205].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[206].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[207].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[208].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[209].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[20].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[210].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[211].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[212].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[213].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
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tb.dut.tlul_assert_device.gen_assert_final[217].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[218].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[219].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[21].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[220].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
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tb.dut.tlul_assert_device.gen_assert_final[223].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
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tb.dut.tlul_assert_device.gen_assert_final[226].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[227].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[228].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[229].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[22].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[230].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
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tb.dut.tlul_assert_device.gen_assert_final[232].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[233].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[234].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
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tb.dut.tlul_assert_device.gen_assert_final[238].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[239].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[23].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[240].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[241].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
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tb.dut.tlul_assert_device.gen_assert_final[245].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
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tb.dut.tlul_assert_device.gen_assert_final[247].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[248].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[249].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[24].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[250].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[251].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[252].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[253].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[254].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[255].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[25].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[26].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[27].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[28].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[29].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[2].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[30].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[31].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[32].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[33].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[34].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[35].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
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tb.dut.tlul_assert_device.gen_assert_final[38].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[39].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[3].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[40].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[41].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[42].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[43].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
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tb.dut.tlul_assert_device.gen_assert_final[46].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[47].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[48].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[49].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[4].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[50].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[51].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[52].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
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tb.dut.tlul_assert_device.gen_assert_final[59].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
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tb.dut.tlul_assert_device.gen_assert_final[60].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[61].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[62].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[63].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[64].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[65].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[66].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[67].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[68].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[69].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[6].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[70].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[71].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[72].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[73].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[74].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[75].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[76].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[77].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[78].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[79].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[7].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[80].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[81].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[82].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[83].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[84].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[85].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[86].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[87].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[88].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[89].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[8].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[90].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[91].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[92].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[93].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[94].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[95].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[96].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[97].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_assert_final[9].noOutstandingReqsAtEndOfSim_A	0	0	918	918	0	0
tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	2147483647	16482568	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	2147483647	3178	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	2147483647	20132084	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	2147483647	4163551	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	2147483647	2867	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	2147483647	29908489	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	2147483647	5033195	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	2147483647	29908489	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	2147483647	5033195	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	2147483647	5033195	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	2147483647	5033195	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	2147483647	2860	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	2147483647	3472	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	918	918	0	0
tb.dut.u_adc_ctrl_core.MaxFilters_A	0	0	34443164	34128965	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[0].MatchCheck00_A	0	0	34443164	10772127	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[0].MatchCheck01_A	0	0	34443164	2312118	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[0].MatchCheck10_A	0	0	34443164	3021261	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[0].MatchCheck11_A	0	0	34443164	18023459	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[1].MatchCheck00_A	0	0	34443164	11423657	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[1].MatchCheck01_A	0	0	34443164	1442016	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[1].MatchCheck10_A	0	0	34443164	1120395	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[1].MatchCheck11_A	0	0	34443164	20142897	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[2].MatchCheck00_A	0	0	34443164	12845617	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[2].MatchCheck01_A	0	0	34443164	538276	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[2].MatchCheck10_A	0	0	34443164	708890	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[2].MatchCheck11_A	0	0	34443164	20036182	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[3].MatchCheck00_A	0	0	34443164	12420387	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[3].MatchCheck01_A	0	0	34443164	454763	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[3].MatchCheck10_A	0	0	34443164	274293	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[3].MatchCheck11_A	0	0	34443164	20979522	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[4].MatchCheck00_A	0	0	34443164	12991782	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[4].MatchCheck01_A	0	0	34443164	32959	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[4].MatchCheck10_A	0	0	34443164	121	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[4].MatchCheck11_A	0	0	34443164	21104103	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[5].MatchCheck00_A	0	0	34443164	13089446	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[5].MatchCheck01_A	0	0	34443164	88225	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[5].MatchCheck10_A	0	0	34443164	142899	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[5].MatchCheck11_A	0	0	34443164	20808395	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[6].MatchCheck00_A	0	0	34443164	13420991	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[6].MatchCheck01_A	0	0	34443164	64423	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[6].MatchCheck10_A	0	0	34443164	245738	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[6].MatchCheck11_A	0	0	34443164	20397813	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[7].MatchCheck00_A	0	0	34443164	13079466	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[7].MatchCheck01_A	0	0	34443164	158980	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[7].MatchCheck10_A	0	0	34443164	189061	0	0
tb.dut.u_adc_ctrl_core.gen_filter_match[7].MatchCheck11_A	0	0	34443164	20701458	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.LpSampleCntCfg_M	0	0	31763486	31679283	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.NpCntClrMisMatch_A	0	0	31763486	165470	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.NpCntClrPwrDn_A	0	0	31763486	95389	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.NpSampleCntCfg_M	0	0	31763486	31679283	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.FsmDebugOut_A	0	0	31763486	31679283	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.FsmStateHwReset_A	0	0	1217	1217	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.FsmStateSwReset_A	0	0	31763486	6711	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.LpSampleCntHwReset_A	0	0	1217	1217	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.LpSampleCntSwReset_A	0	0	31763486	6711	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.NpSampleCntHwReset_A	0	0	1217	1217	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.NpSampleCntSwReset_A	0	0	31763486	6711	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.PwrupTimerCntHwReset_A	0	0	1217	1217	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.PwrupTimerCntSwReset_A	0	0	31763486	6711	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.WakeupTimerCntHwReset_A	0	0	1217	1217	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_fsm.u_adc_ctrl_fsm_sva.WakeupTimerCntSwReset_A	0	0	31763486	6711	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.i_adc_ctrl_intr_o.IntrTKind_A	0	0	753	753	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.u_match_sync.SyncReqAckAckNeedsReq	0	0	2147483647	17379	0	0
tb.dut.u_adc_ctrl_core.u_adc_ctrl_intr.u_match_sync.SyncReqAckHoldReq	0	0	34443164	17377	0	0
tb.dut.u_adc_ctrl_core.u_oneshot_done_sync.DstPulseCheck_A	0	0	2147483647	6422	0	0
tb.dut.u_adc_ctrl_core.u_oneshot_done_sync.SrcPulseCheck_M	0	0	34443164	6425	0	0
tb.dut.u_reg.en2addrHit	0	0	2147483647	2473576	0	0
tb.dut.u_reg.reAfterRv	0	0	2147483647	2473575	0	0
tb.dut.u_reg.rePulse	0	0	2147483647	2177796	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.BusySrcReqChk_A	0	0	2147483647	1997958	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.DstReqKnown_A	0	0	34535855	34188823	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.SrcAckBusyChk_A	0	0	2147483647	2205	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	2205	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34535855	2205	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34535855	2116	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2217	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.BusySrcReqChk_A	0	0	2147483647	1856010	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.DstReqKnown_A	0	0	34535855	34188823	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.SrcAckBusyChk_A	0	0	2147483647	2057	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	2057	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34535855	2057	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34535855	1976	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2070	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.BusySrcReqChk_A	0	0	2147483647	1879010	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.DstReqKnown_A	0	0	34535855	34188823	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.SrcAckBusyChk_A	0	0	2147483647	2078	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	2078	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34535855	2078	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34535855	1992	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2089	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.BusySrcReqChk_A	0	0	2147483647	1879070	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.DstReqKnown_A	0	0	34535855	34188823	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.SrcAckBusyChk_A	0	0	2147483647	2092	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	2092	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34535855	2092	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34535855	2005	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2102	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.BusySrcReqChk_A	0	0	2147483647	1857701	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.DstReqKnown_A	0	0	34535855	34188823	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.SrcAckBusyChk_A	0	0	2147483647	2086	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	2086	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34535855	2086	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34535855	2005	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_4_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2099	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.BusySrcReqChk_A	0	0	2147483647	1874297	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.DstReqKnown_A	0	0	34535855	34188823	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.SrcAckBusyChk_A	0	0	2147483647	2100	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	2100	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34535855	2100	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34535855	2013	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_5_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2112	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.BusySrcReqChk_A	0	0	2147483647	1851650	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.DstReqKnown_A	0	0	34535855	34188823	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.SrcAckBusyChk_A	0	0	2147483647	2091	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	2091	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34535855	2091	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34535855	2010	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_6_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2102	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.BusySrcReqChk_A	0	0	2147483647	1823468	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.DstReqKnown_A	0	0	34535855	34188823	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.SrcAckBusyChk_A	0	0	2147483647	2074	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	2074	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34535855	2074	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34535855	1986	0	0
tb.dut.u_reg.u_adc_chn0_filter_ctl_7_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2086	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.BusySrcReqChk_A	0	0	2147483647	1946825	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.DstReqKnown_A	0	0	34535855	34188823	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.SrcAckBusyChk_A	0	0	2147483647	2190	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	2190	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34535855	2190	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34535855	2106	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_0_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2201	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.BusySrcReqChk_A	0	0	2147483647	1852262	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.DstReqKnown_A	0	0	34535855	34188823	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.SrcAckBusyChk_A	0	0	2147483647	2104	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	2104	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34535855	2104	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34535855	2020	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_1_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2115	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.BusySrcReqChk_A	0	0	2147483647	1836601	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.DstReqKnown_A	0	0	34535855	34188823	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.SrcAckBusyChk_A	0	0	2147483647	2091	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	2091	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34535855	2091	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34535855	2007	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_2_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2101	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.BusySrcReqChk_A	0	0	2147483647	1824804	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.DstReqKnown_A	0	0	34535855	34188823	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.SrcAckBusyChk_A	0	0	2147483647	2073	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	2073	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34535855	2073	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34535855	1990	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_3_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2085	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.BusySrcReqChk_A	0	0	2147483647	1823187	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.DstReqKnown_A	0	0	34535855	34188823	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.SrcAckBusyChk_A	0	0	2147483647	2088	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	2088	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34535855	2088	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34535855	2003	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_4_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2097	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.BusySrcReqChk_A	0	0	2147483647	1803775	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.DstReqKnown_A	0	0	34535855	34188823	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.SrcAckBusyChk_A	0	0	2147483647	2057	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	2057	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34535855	2057	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34535855	1975	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_5_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2069	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.BusySrcReqChk_A	0	0	2147483647	1855245	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.DstReqKnown_A	0	0	34535855	34188823	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.SrcAckBusyChk_A	0	0	2147483647	2112	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	2112	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34535855	2112	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34535855	2026	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_6_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2123	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.BusySrcReqChk_A	0	0	2147483647	1812429	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.DstReqKnown_A	0	0	34535855	34188823	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.SrcAckBusyChk_A	0	0	2147483647	2075	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	2075	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34535855	2075	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34535855	1992	0	0
tb.dut.u_reg.u_adc_chn1_filter_ctl_7_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	2086	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.DstReqKnown_A	0	0	34535855	34188823	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	34535855	650501	0	918
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	34535855	650682	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	2147483647	650686	0	0
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	34535855	650399	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.DstReqKnown_A	0	0	34535855	34188823	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	34535855	634851	0	918
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	34535855	642747	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	2147483647	642751	0	0
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	34535855	632234	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.BusySrcReqChk_A	0	0	2147483647	35197258	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.DstReqKnown_A	0	0	34535855	34188823	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.SrcAckBusyChk_A	0	0	2147483647	38310	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	38310	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34535855	38323	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34535855	38219	0	0
tb.dut.u_reg.u_adc_en_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	38355	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.BusySrcReqChk_A	0	0	2147483647	18535376	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.DstReqKnown_A	0	0	34535855	34188823	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.SrcAckBusyChk_A	0	0	2147483647	20005	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	20005	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34535855	20005	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34535855	19922	0	0
tb.dut.u_reg.u_adc_fsm_rst_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	20017	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.BusySrcReqChk_A	0	0	2147483647	106589	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.DstReqKnown_A	0	0	34535855	34188823	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.SrcAckBusyChk_A	0	0	2147483647	99	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	34535855	3275052	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	2147483647	3275178	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	34535855	1698081	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34535855	86	0	0
tb.dut.u_reg.u_adc_fsm_state_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	394	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.BusySrcReqChk_A	0	0	2147483647	12854143	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.DstReqKnown_A	0	0	34535855	34188823	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.SrcAckBusyChk_A	0	0	2147483647	14253	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	14253	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34535855	14253	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34535855	14145	0	0
tb.dut.u_reg.u_adc_lp_sample_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	14300	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.BusySrcReqChk_A	0	0	2147483647	16237700	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.DstReqKnown_A	0	0	34535855	34188823	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.SrcAckBusyChk_A	0	0	2147483647	18196	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	18196	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34535855	18196	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34535855	18110	0	0
tb.dut.u_reg.u_adc_pd_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	18210	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.BusySrcReqChk_A	0	0	2147483647	12961624	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.DstReqKnown_A	0	0	34535855	34188823	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.SrcAckBusyChk_A	0	0	2147483647	14262	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	14262	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34535855	14262	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34535855	14152	0	0
tb.dut.u_reg.u_adc_sample_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	14308	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.BusySrcReqChk_A	0	0	2147483647	1326382	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.DstReqKnown_A	0	0	34535855	34188823	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.SrcAckBusyChk_A	0	0	2147483647	1533	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.DstPulseCheck_A	0	0	2147483647	1533	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_arb.gen_passthru.u_dst_to_src_ack.SrcPulseCheck_M	0	0	34535855	1533	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34535855	1450	0	0
tb.dut.u_reg.u_adc_wakeup_ctl_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	1542	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	918	918	0	0
tb.dut.u_reg.u_filter_status_cdc.BusySrcReqChk_A	0	0	2147483647	61604797	0	0
tb.dut.u_reg.u_filter_status_cdc.DstReqKnown_A	0	0	34535855	34188823	0	0
tb.dut.u_reg.u_filter_status_cdc.SrcAckBusyChk_A	0	0	2147483647	68468	0	0
tb.dut.u_reg.u_filter_status_cdc.SrcBusyKnown_A	0	0	2147483647	2147483647	0	0
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	34535855	15584	0	918
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.HwIdSelCheck_A	0	0	34535855	15651	0	0
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckAckNeedsReq	0	0	2147483647	84119	0	0
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.u_dst_update_sync.SyncReqAckHoldReq	0	0	34535855	83177	0	0
tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req.DstPulseCheck_A	0	0	34535855	68381	0	0
tb.dut.u_reg.u_filter_status_cdc.u_src_to_dst_req.SrcPulseCheck_M	0	0	2147483647	68480	0	0
tb.dut.u_reg.u_reg_if.AllowedLatency_A	0	0	918	918	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	918	918	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	918	918	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	918	918	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	918	918	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	918	918	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	918	918	0	0
tb.dut.u_reg.wePulse	0	0	2147483647	295779	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_reg.u_adc_chn_val_0_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	34535855	650501	0	918
tb.dut.u_reg.u_adc_chn_val_1_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	34535855	634851	0	918
tb.dut.u_reg.u_adc_fsm_state_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	34535855	0	0	918
tb.dut.u_reg.u_filter_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A	0	0	34535855	15584	0	918

---

Detail Report for Cover Sequences

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	2147483647	1283527	1283527	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	2147483647	1319	1319	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	2147483647	2981	2981	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	2147483647	1806	1806	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	2147483647	2673	2673	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	2147483647	1456	1456	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	2147483647	1948	1948	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	2147483647	3040	3040	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	2147483647	5743	5743	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	2147483647	1263715	1263715	849

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	2147483647	1283527	1283527	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	2147483647	1319	1319	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	2147483647	2981	2981	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	2147483647	1806	1806	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	2147483647	2673	2673	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	2147483647	1456	1456	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	2147483647	1948	1948	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	2147483647	3040	3040	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	2147483647	5743	5743	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	2147483647	1263715	1263715	849