Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26602

1

T1

19

T2

176

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22851

1

T1

19

T2

176

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3751

1

T5

13

T11

11

T13

70

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20526

1

T2

176

T4

185

T5

13

auto[1]

6076

1

T1

19

T3

3

T5

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22211

1

T1

19

T2

176

T3

3

auto[1]

4391

1

T11

23

T13

85

T14

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	98	1			T155	1		T213	26		T214	19
values[1]	690	1			T5	12		T43	23		T144	13
values[2]	2878	1			T1	19		T3	3		T8	2
values[3]	765	1			T11	11		T44	2		T149	19
values[4]	604	1			T5	13		T12	1		T13	9
values[5]	801	1			T30	9		T33	17		T44	23
values[6]	891	1			T12	1		T13	22		T14	5
values[7]	747	1			T13	6		T32	31		T39	12
values[8]	668	1			T14	9		T158	10		T43	6
values[9]	1357	1			T11	13		T13	61		T158	17
minimum	17103	1			T2	176		T4	185		T6	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	911	1			T5	12		T13	24		T43	23
values[1]	2992	1			T1	19		T3	3		T8	2
values[2]	756	1			T5	13		T11	11		T44	2
values[3]	564	1			T12	1		T13	9		T33	17
values[4]	829	1			T13	5		T14	5		T30	9
values[5]	878	1			T13	17		T30	19		T32	31
values[6]	708	1			T12	1		T13	6		T39	12
values[7]	675	1			T13	8		T14	9		T158	10
values[8]	974	1			T11	13		T13	53		T158	17
values[9]	204	1			T161	18		T140	21		T215	2
minimum	17111	1			T2	176		T4	185		T6	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22439

1

T1

1

T2

176

T3

3

auto[1]

4163

1

T1

18

T5

23

T13

36

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T5	12		T13	10		T144	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T43	23		T145	3		T147	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1550	1			T1	19		T3	3		T8	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T141	1		T144	8		T38	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T44	1		T149	19		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T5	13		T11	1		T216	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T12	1		T33	10		T217	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T13	1		T144	8		T143	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T13	1		T30	3		T147	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T14	5		T44	11		T77	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T13	9		T32	17		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T13	2		T30	10		T45	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T12	1		T148	8		T169	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	2		T39	7		T217	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T13	1		T14	1		T76	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T14	4		T158	1		T43	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	288	1			T11	1		T158	1		T145	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T13	23		T141	1		T175	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T218	7		T82	13		T180	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T161	1		T140	11		T215	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16969	1			T2	176		T4	185		T6	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T219	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T13	14		T134	10		T175	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T145	5		T147	7		T153	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1090	1			T197	13		T179	17		T137	16
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T38	2		T17	5		T220	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T44	1		T216	15		T155	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T11	10		T216	10		T159	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T33	7		T221	8		T170	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T13	8		T39	15		T222	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T13	4		T30	6		T147	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T44	12		T77	12		T134	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T13	6		T32	14		T159	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T30	9		T161	13		T148	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T148	6		T169	3		T140	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T13	4		T39	5		T34	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T13	7		T76	7		T145	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T14	4		T158	9		T221	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T11	12		T158	16		T145	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T13	30		T141	14		T175	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T218	7		T82	12		T180	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T161	17		T140	10		T215	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	1		T13	12		T33	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T213	14		T214	11		T223	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T155	1		T224	1		T180	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T5	12		T144	13		T134	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T43	23		T145	3		T147	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1454	1			T1	19		T3	3		T8	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T141	1		T144	8		T175	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	249	1			T44	1		T149	19		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T11	1		T216	1		T38	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T12	1		T217	11		T221	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T5	13		T13	1		T144	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T30	3		T33	10		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T44	11		T77	1		T134	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T12	1		T13	10		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T13	2		T14	5		T30	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T32	17		T169	5		T225	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T13	2		T39	7		T217	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T14	1		T76	1		T145	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T14	4		T158	1		T43	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	349	1			T11	1		T13	1		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	336	1			T13	23		T141	1		T161	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16969	1			T2	176		T4	185		T6	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T213	12		T214	8		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T224	5		T180	10		T226	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T134	10		T175	6		T103	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T145	5		T147	7		T222	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1038	1			T13	14		T197	13		T179	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T175	2		T17	5		T153	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T44	1		T216	15		T155	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T11	10		T216	10		T38	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	53	1			T221	8		T35	10		T42	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T13	8		T159	13		T39	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T30	6		T33	7		T147	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T44	12		T77	12		T134	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T13	10		T159	8		T178	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T30	9		T161	13		T214	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T32	14		T169	3		T225	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T13	4		T39	5		T34	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T76	7		T145	7		T148	6
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T14	4		T158	9		T221	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	348	1			T11	12		T13	7		T158	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	324	1			T13	30		T141	14		T161	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	1		T13	12		T33	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T5	1		T13	15		T144	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T43	2		T145	6		T147	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1424	1			T1	1		T3	3		T8	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T141	1		T144	1		T38	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T44	2		T149	2		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T5	1		T11	11		T216	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T12	1		T33	8		T217	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T13	9		T144	1		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	269	1			T13	5		T30	7		T147	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T14	3		T44	13		T77	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T13	7		T32	15		T159	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T13	2		T30	10		T45	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T12	1		T148	7		T169	4
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T13	6		T39	9		T217	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	8		T14	1		T76	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T14	7		T158	10		T43	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T11	13		T158	17		T145	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T13	34		T141	15		T175	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T218	8		T82	14		T180	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T161	18		T140	11		T215	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17103	1			T2	176		T4	185		T6	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T219	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T5	11		T13	9		T144	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T43	21		T145	2		T227	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1216	1			T1	18		T228	23		T150	39
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T144	7		T103	3		T191	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T149	17		T146	10		T155	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T5	12		T159	12		T175	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T33	9		T217	10		T221	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T144	7		T143	11		T39	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T30	2		T178	6		T139	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T14	2		T44	10		T134	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T13	8		T32	16		T40	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T30	9		T45	11		T214	20
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T148	7		T169	4		T140	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T39	3		T217	11		T34	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T145	10		T154	11		T229	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T14	1		T43	5		T221	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T145	9		T176	12		T217	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T13	19		T175	5		T136	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T218	6		T82	11		T180	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T140	10		T230	5		T194	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T219	7		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T213	13		T214	9		T223	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T155	1		T224	6		T180	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T5	1		T144	1		T134	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T43	2		T145	6		T147	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1361	1			T1	1		T3	3		T8	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T141	1		T144	1		T175	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T44	2		T149	2		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T11	11		T216	11		T38	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	80	1			T12	1		T217	1		T221	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T5	1		T13	9		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	235	1			T30	7		T33	8		T147	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T44	13		T77	13		T134	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T12	1		T13	12		T159	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T13	2		T14	3		T30	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T32	15		T169	4		T225	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T13	6		T39	9		T217	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T14	1		T76	8		T145	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T14	7		T158	10		T43	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	416	1			T11	13		T13	8		T158	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	394	1			T13	34		T141	15		T161	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17103	1			T2	176		T4	185		T6	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T213	13		T214	10		T231	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T180	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T5	11		T144	12		T134	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T43	21		T145	2		T219	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1131	1			T1	18		T13	9		T228	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T144	7		T175	7		T191	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T149	17		T146	10		T155	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T16	2		T136	10		T139	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T217	10		T221	10		T232	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T5	12		T144	7		T143	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T30	2		T33	9		T139	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T44	10		T134	12		T37	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T13	8		T178	6		T40	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T14	2		T30	9		T45	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T32	16		T169	4		T225	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T39	3		T217	11		T34	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T145	10		T148	7		T154	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T14	1		T43	5		T221	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T145	9		T176	12		T217	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T13	19		T175	5		T136	15

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22439

1

T1

1

T2

176

T3

3

auto[1]

auto[0]

4163

1

T1

18

T5

23

T13

36

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26602

1

T1

19

T2

176

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20511

1

T2

176

T4

185

T6

14

auto[ADC_CTRL_FILTER_COND_OUT]

6091

1

T1

19

T3

3

T5

25

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20664

1

T2

176

T4

185

T5

25

auto[1]

5938

1

T1

19

T3

3

T8

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22211

1

T1

19

T2

176

T3

3

auto[1]

4391

1

T11

23

T13

85

T14

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for max_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	90	1			T16	13		T192	10		T233	39
values[1]	749	1			T12	1		T14	8		T32	31
values[2]	868	1			T13	24		T30	19		T134	22
values[3]	622	1			T30	9		T45	12		T149	5
values[4]	855	1			T13	29		T14	1		T141	1
values[5]	730	1			T13	6		T158	10		T144	8
values[6]	755	1			T9	1		T13	38		T141	15
values[7]	732	1			T11	13		T13	10		T33	17
values[8]	717	1			T13	15		T14	5		T158	17
values[9]	3381	1			T1	19		T3	3		T5	25
minimum	17103	1			T2	176		T4	185		T6	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1033	1			T12	1		T30	19		T32	31
values[1]	2950	1			T1	19		T3	3		T8	2
values[2]	681	1			T13	48		T30	9		T141	1
values[3]	775	1			T13	5		T14	1		T158	10
values[4]	749	1			T9	1		T13	6		T43	14
values[5]	769	1			T13	38		T141	15		T144	8
values[6]	857	1			T11	13		T13	10		T33	17
values[7]	604	1			T5	25		T13	15		T14	5
values[8]	861	1			T11	11		T12	1		T144	13
values[9]	193	1			T175	10		T148	14		T139	19
minimum	17130	1			T2	176		T4	185		T6	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22439

1

T1

1

T2

176

T3

3

auto[1]

4163

1

T1

18

T5

23

T13

36

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	321	1			T32	17		T43	9		T77	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T12	1		T30	10		T43	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T149	9		T232	13		T157	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1552	1			T1	19		T3	3		T8	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T30	3		T141	1		T149	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T13	12		T45	12		T143	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T149	14		T147	1		T175	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	1		T14	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T13	2		T145	3		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T9	1		T43	14		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T13	21		T135	1		T40	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T13	1		T141	1		T144	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T13	2		T33	10		T144	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T11	1		T13	1		T44	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T14	5		T160	1		T216	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T5	25		T13	9		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T11	1		T12	1		T39	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T144	13		T145	11		T137	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T175	8		T148	8		T139	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T140	5		T164	1		T183	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16969	1			T2	176		T4	185		T6	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T234	1		T235	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T32	14		T77	12		T38	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T30	9		T44	12		T134	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T157	2		T230	15		T194	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1035	1			T14	4		T197	13		T134	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T30	6		T216	15		T236	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T13	36		T199	11		T57	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T147	7		T175	6		T136	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T13	4		T158	9		T76	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T13	4		T145	5		T161	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T159	8		T161	13		T17	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T13	16		T40	1		T154	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T141	14		T170	9		T237	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T33	7		T148	8		T138	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T11	12		T13	7		T44	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T216	4		T147	10		T175	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T13	6		T158	16		T236	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T11	10		T39	5		T222	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T145	7		T137	16		T169	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T175	2		T148	6		T139	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T140	4		T164	13		T183	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	1		T13	12		T33	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T234	14		T235	11		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T192	3		T233	14		T238	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T16	9		T233	7		T239	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T32	17		T43	9		T77	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	205	1			T12	1		T14	4		T43	6
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T149	9		T38	3		T176	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T13	10		T30	10		T134	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T30	3		T149	5		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T45	12		T160	1		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T141	1		T149	14		T216	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T13	3		T14	1		T43	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T13	2		T145	3		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T158	1		T144	8		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T13	21		T135	1		T40	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T9	1		T13	1		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T13	2		T33	10		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	1		T13	1		T44	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T14	5		T144	8		T216	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T13	9		T158	1		T144	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T11	1		T12	1		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1740	1			T1	19		T3	3		T5	25
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16969	1			T2	176		T4	185		T6	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T192	7		T233	11		T238	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T16	4		T233	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T32	14		T77	12		T221	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T14	4		T44	12		T134	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T38	2		T225	7		T157	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T13	14		T30	9		T134	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T30	6		T147	7		T236	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T213	12		T57	10		T18	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T216	15		T175	6		T136	15
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T13	26		T76	7		T39	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T13	4		T145	5		T161	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T158	9		T161	13		T240	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T13	16		T40	1		T136	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T141	14		T159	8		T17	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T33	7		T148	8		T138	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T11	12		T13	7		T44	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T216	4		T215	1		T218	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T13	6		T158	16		T169	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T11	10		T147	10		T175	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1198	1			T197	13		T145	7		T179	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	1		T13	12		T33	2