Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26602

1

T1

19

T2

176

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22734

1

T1

19

T2

176

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3868

1

T5

25

T9

1

T11

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20337

1

T2

176

T4

185

T6

14

auto[1]

6265

1

T1

19

T3

3

T5

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22211

1

T1

19

T2

176

T3

3

auto[1]

4391

1

T11

23

T13

85

T14

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	176	1			T137	1		T249	2		T295	1
values[0]	63	1			T13	8		T216	11		T296	29
values[1]	642	1			T43	14		T144	8		T37	3
values[2]	798	1			T30	9		T44	2		T77	13
values[3]	650	1			T13	1		T30	19		T141	15
values[4]	881	1			T5	12		T13	25		T14	1
values[5]	767	1			T11	11		T13	9		T14	8
values[6]	697	1			T5	13		T14	5		T33	17
values[7]	820	1			T9	1		T11	13		T13	39
values[8]	2840	1			T1	19		T3	3		T8	2
values[9]	1165	1			T12	1		T13	29		T32	31
minimum	17103	1			T2	176		T4	185		T6	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	841	1			T30	9		T43	14		T77	13
values[1]	652	1			T30	19		T44	2		T145	21
values[2]	717	1			T13	26		T14	1		T158	10
values[3]	796	1			T5	12		T149	19		T216	16
values[4]	852	1			T11	11		T13	9		T14	8
values[5]	625	1			T5	13		T13	15		T14	5
values[6]	3002	1			T1	19		T3	3		T8	2
values[7]	626	1			T12	1		T13	11		T43	6
values[8]	1051	1			T13	29		T32	31		T158	17
values[9]	155	1			T219	8		T222	2		T249	1
minimum	17285	1			T2	176		T4	185		T6	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22439

1

T1

1

T2

176

T3

3

auto[1]

4163

1

T1

18

T5

23

T13

36

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T144	8		T161	1		T147	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T30	3		T43	14		T77	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T30	10		T44	1		T145	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T147	1		T153	1		T139	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T13	1		T14	1		T141	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T13	11		T158	1		T159	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T216	1		T17	1		T155	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T5	12		T149	19		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T11	1		T14	4		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T13	1		T134	13		T146	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T13	9		T148	8		T264	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T5	13		T14	5		T33	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1512	1			T1	19		T3	3		T8	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T9	1		T11	1		T134	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T12	1		T13	3		T43	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T144	13		T160	1		T217	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T13	10		T32	17		T44	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T13	3		T158	1		T76	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	58	1			T222	1		T297	9		T298	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T219	8		T249	1		T254	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17013	1			T2	176		T4	185		T6	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T216	1		T251	8		T299	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T161	17		T175	4		T214	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T30	6		T77	12		T37	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T30	9		T44	1		T145	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T147	7		T153	13		T139	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T141	14		T216	4		T175	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T13	14		T158	9		T159	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T216	15		T17	5		T155	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T159	8		T154	7		T103	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T11	10		T14	4		T39	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T13	8		T134	13		T243	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T13	6		T148	6		T191	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T33	7		T161	13		T138	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1036	1			T13	14		T197	13		T145	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T11	12		T134	10		T145	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T13	8		T38	2		T136	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T154	2		T222	12		T102	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T13	2		T32	14		T44	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T13	14		T158	16		T76	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	18	1			T222	1		T298	5		T300	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T254	9		T301	9		T273	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T11	1		T13	19		T33	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	58	1			T216	10		T251	7		T270	3

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T137	1		T249	1		T198	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	40	1			T249	1		T295	1		T192	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T13	1		T296	20		T302	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T216	1		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T144	8		T147	1		T214	21
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T43	14		T37	2		T16	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T44	1		T145	10		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T30	3		T77	1		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T13	1		T30	10		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T159	13		T153	1		T139	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T14	1		T216	2		T17	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T5	12		T13	11		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T11	1		T14	4		T160	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T13	1		T149	5		T154	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T148	8		T259	15		T264	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T5	13		T14	5		T33	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T13	19		T43	9		T144	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	276	1			T9	1		T11	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1503	1			T1	19		T3	3		T8	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T144	13		T160	1		T217	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	302	1			T12	1		T13	10		T32	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	362	1			T13	3		T158	1		T76	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16969	1			T2	176		T4	185		T6	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T198	12		T192	7		T300	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T192	14		T247	8		T303	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T13	7		T296	9		T302	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T216	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T147	10		T214	16		T57	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T37	1		T16	4		T148	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T44	1		T145	11		T161	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T30	6		T77	12		T147	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T30	9		T141	14		T175	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T159	13		T153	13		T139	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T216	19		T17	5		T155	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T13	14		T158	9		T159	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T11	10		T14	4		T39	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T13	8		T154	7		T236	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T148	6		T259	13		T191	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T33	7		T134	13		T161	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T13	20		T145	7		T39	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T11	12		T134	10		T145	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1039	1			T13	8		T197	13		T179	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T213	12		T154	2		T222	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T13	2		T32	14		T44	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T13	14		T158	16		T76	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	1		T13	12		T33	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T144	1		T161	18		T147	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T30	7		T43	1		T77	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T30	10		T44	2		T145	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T147	8		T153	14		T139	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T13	1		T14	1		T141	15
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	15		T158	10		T159	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T216	16		T17	6		T155	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T5	1		T149	2		T159	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	272	1			T11	11		T14	7		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T13	9		T134	14		T146	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T13	7		T148	7		T264	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T5	1		T14	3		T33	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1371	1			T1	1		T3	3		T8	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T9	1		T11	13		T134	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T12	1		T13	11		T43	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T144	1		T160	1		T217	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T13	3		T32	15		T44	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	341	1			T13	17		T158	17		T76	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T222	2		T297	1		T298	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T219	1		T249	1		T254	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17156	1			T2	176		T4	185		T6	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T216	11		T251	8		T299	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T144	7		T175	5		T214	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T30	2		T43	13		T37	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	94	1			T30	9		T145	9		T243	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T139	3		T156	6		T170	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T175	7		T136	15		T266	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T13	10		T159	12		T34	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T155	7		T241	10		T232	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T5	11		T149	17		T154	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T14	1		T39	3		T221	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T134	12		T146	10		T243	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T13	8		T148	7		T105	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T5	12		T14	2		T33	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1177	1			T1	18		T13	9		T43	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T134	11		T145	2		T243	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T43	5		T144	7		T176	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T144	12		T217	10		T154	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T13	9		T32	16		T44	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	270	1			T45	11		T175	6		T217	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T297	8		T298	6		T300	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T219	7		T301	11		T304	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T22	2		T296	19		T302	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T251	7		T280	4		T270	3

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T137	1		T249	1		T198	13
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T249	1		T295	1		T192	15
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	23	1			T13	8		T296	10		T302	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T216	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T144	1		T147	11		T214	17
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T43	1		T37	2		T16	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T44	2		T145	12		T161	18
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T30	7		T77	13		T147	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T13	1		T30	10		T141	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T159	14		T153	14		T139	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T14	1		T216	21		T17	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T5	1		T13	15		T158	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T11	11		T14	7		T160	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T13	9		T149	1		T154	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T148	7		T259	14		T264	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T5	1		T14	3		T33	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	22		T43	1		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T9	1		T11	13		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1376	1			T1	1		T3	3		T8	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T144	1		T160	1		T217	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T12	1		T13	3		T32	15
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	383	1			T13	17		T158	17		T76	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17103	1			T2	176		T4	185		T6	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	45	1			T192	2		T166	9		T300	2
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	26	1			T192	12		T305	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T296	19		T302	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T144	7		T214	20		T229	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T43	13		T37	1		T16	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T145	9		T175	5		T243	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T30	2		T139	1		T221	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T30	9		T175	7		T136	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T159	12		T139	2		T34	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T155	7		T241	10		T171	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T5	11		T13	10		T149	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T14	1		T39	3		T221	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T149	4		T154	8		T236	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T148	7		T259	14		T105	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T5	12		T14	2		T33	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T13	17		T43	8		T144	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T134	11		T149	8		T145	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1166	1			T1	18		T43	5		T228	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T144	12		T217	10		T213	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T13	9		T32	16		T44	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T45	11		T175	6		T217	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22439

1

T1

1

T2

176

T3

3

auto[1]

auto[0]

4163

1

T1

18

T5

23

T13

36