Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26602

1

T1

19

T2

176

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22538

1

T1

19

T2

176

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

4064

1

T5

13

T9

1

T11

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20366

1

T2

176

T4

185

T6

14

auto[1]

6236

1

T1

19

T3

3

T5

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22211

1

T1

19

T2

176

T3

3

auto[1]

4391

1

T11

23

T13

85

T14

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	294	1			T158	17		T45	12		T176	9
values[0]	40	1			T43	14		T157	2		T165	1
values[1]	866	1			T5	13		T12	1		T13	29
values[2]	790	1			T13	25		T44	23		T77	13
values[3]	730	1			T12	1		T13	15		T44	2
values[4]	2941	1			T1	19		T3	3		T8	2
values[5]	841	1			T11	24		T149	9		T39	12
values[6]	569	1			T9	1		T30	9		T134	26
values[7]	812	1			T5	12		T13	15		T32	31
values[8]	724	1			T13	30		T14	8		T159	26
values[9]	892	1			T13	8		T158	10		T43	9
minimum	17103	1			T2	176		T4	185		T6	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	850	1			T5	13		T12	1		T13	49
values[1]	610	1			T44	23		T77	13		T160	1
values[2]	805	1			T12	1		T13	15		T44	2
values[3]	2952	1			T1	19		T3	3		T8	2
values[4]	805	1			T11	11		T30	9		T149	9
values[5]	567	1			T9	1		T134	26		T149	5
values[6]	813	1			T5	12		T13	17		T32	31
values[7]	703	1			T13	28		T14	8		T134	22
values[8]	825	1			T13	8		T158	27		T43	9
values[9]	223	1			T216	11		T146	11		T175	13
minimum	17449	1			T2	176		T4	185		T6	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22439

1

T1

1

T2

176

T3

3

auto[1]

4163

1

T1

18

T5

23

T13

36

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T12	1		T13	21		T14	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T5	13		T43	14		T76	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T44	11		T77	1		T175	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T160	1		T147	1		T222	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T12	1		T13	1		T44	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T13	2		T145	11		T39	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1509	1			T1	19		T3	3		T8	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T30	10		T144	8		T145	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T39	7		T154	9		T222	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	308	1			T11	1		T30	3		T149	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	151	1			T149	5		T160	1		T216	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T9	1		T134	13		T40	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T5	12		T13	11		T32	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T141	1		T145	3		T216	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T13	12		T14	4		T219	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T134	12		T143	12		T159	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T158	2		T45	12		T16	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T13	1		T43	9		T144	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T146	11		T154	12		T185	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T216	1		T175	7		T153	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17065	1			T2	176		T4	185		T6	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	114	1			T13	1		T171	14		T157	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T13	28		T161	17		T139	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T76	7		T161	13		T251	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T44	12		T77	12		T175	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T147	7		T222	1		T191	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T13	8		T44	1		T147	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T13	4		T145	7		T39	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1018	1			T11	12		T33	7		T141	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T30	9		T145	11		T153	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T39	5		T154	7		T222	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T11	10		T30	6		T148	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T216	15		T140	2		T87	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T134	13		T40	1		T136	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T13	6		T32	14		T38	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T145	5		T216	4		T159	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T13	16		T14	4		T221	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T134	10		T159	13		T37	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T158	25		T16	4		T136	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T13	7		T17	5		T139	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	60	1			T154	2		T265	3		T306	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	64	1			T216	10		T175	6		T153	13
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	1		T13	12		T33	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T13	4		T157	1		T192	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T158	1		T45	12		T221	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T176	9		T248	1		T307	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T165	1		T308	13		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T43	14		T157	1		T58	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T12	1		T13	10		T14	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T5	13		T13	1		T76	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T13	11		T44	11		T77	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T160	1		T161	1		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T12	1		T13	1		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T13	2		T145	11		T137	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1502	1			T1	19		T3	3		T8	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T30	10		T144	8		T145	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T11	1		T39	7		T154	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T11	1		T149	9		T213	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T160	1		T216	1		T243	10
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T9	1		T30	3		T134	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T5	12		T13	9		T32	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T141	1		T134	12		T145	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T13	14		T14	4		T219	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T159	13		T37	2		T178	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T158	1		T146	11		T16	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	292	1			T13	1		T43	9		T144	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16969	1			T2	176		T4	185		T6	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T158	16		T221	4		T230	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T267	12		T309	12		T291	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T157	1		T58	1		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T13	14		T161	17		T243	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T13	4		T76	7		T34	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T13	14		T44	12		T77	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T161	13		T147	7		T251	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T13	8		T44	1		T147	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T13	4		T145	7		T137	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	956	1			T33	7		T141	14		T197	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T30	9		T145	11		T39	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T11	12		T39	5		T154	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	267	1			T11	10		T213	12		T221	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T216	15		T140	2		T222	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T30	6		T134	13		T136	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T13	6		T32	14		T38	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T134	10		T145	5		T216	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	16		T14	4		T221	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T159	13		T37	1		T178	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T158	9		T16	4		T136	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T13	7		T216	10		T175	10
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	1		T13	12		T33	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T12	1		T13	30		T14	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	325	1			T5	1		T43	1		T76	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T44	13		T77	13		T175	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T160	1		T147	8		T222	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T12	1		T13	9		T44	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T13	6		T145	8		T39	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1351	1			T1	1		T3	3		T8	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T30	10		T144	1		T145	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T39	9		T154	8		T222	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T11	11		T30	7		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T149	1		T160	1		T216	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T9	1		T134	14		T40	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	254	1			T5	1		T13	9		T32	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T141	1		T145	6		T216	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T13	19		T14	7		T219	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T134	11		T143	1		T159	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T158	27		T45	1		T16	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T13	8		T43	1		T144	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T146	1		T154	3		T185	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T216	11		T175	7		T153	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17171	1			T2	176		T4	185		T6	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T13	5		T171	1		T157	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T13	19		T43	5		T144	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T5	12		T43	13		T251	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T44	10		T175	7		T243	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T191	14		T262	14		T257	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	176	1			T156	22		T192	2		T162	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T145	10		T39	2		T170	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1176	1			T1	18		T33	9		T228	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T30	9		T144	7		T145	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T39	3		T154	8		T222	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T30	2		T149	8		T148	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T149	4		T243	9		T140	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T134	12		T40	1		T136	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T5	11		T13	8		T32	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T145	2		T178	6		T155	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	9		T14	1		T219	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T134	11		T143	11		T159	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T45	11		T16	2		T136	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T43	8		T144	12		T176	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	59	1			T146	10		T154	11		T306	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T175	6		T310	9		-	-
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	76	1			T14	2		T243	11		T217	11
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T171	13		T192	12		T194	15

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T158	17		T45	1		T221	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T176	1		T248	1		T307	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T165	1		T308	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T43	1		T157	2		T58	7
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T12	1		T13	15		T14	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	316	1			T5	1		T13	5		T76	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T13	15		T44	13		T77	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T160	1		T161	14		T147	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T12	1		T13	9		T44	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T13	6		T145	8		T137	17
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1284	1			T1	1		T3	3		T8	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T30	10		T144	1		T145	12
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T11	13		T39	9		T154	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	326	1			T11	11		T149	1		T213	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T160	1		T216	16		T243	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T9	1		T30	7		T134	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T5	1		T13	7		T32	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T141	1		T134	11		T145	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T13	21		T14	7		T219	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T159	14		T37	2		T178	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T158	10		T146	1		T16	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T13	8		T43	1		T144	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17103	1			T2	176		T4	185		T6	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T45	11		T221	8		T230	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T176	8		T310	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T308	12		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T43	13		T58	3		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T13	9		T14	2		T43	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T5	12		T34	5		T171	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	102	1			T13	10		T44	10		T144	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T251	14		T229	8		T225	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T156	22		T192	2		T162	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T145	10		T214	20		T232	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1174	1			T1	18		T33	9		T228	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T30	9		T144	7		T145	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T39	3		T154	8		T139	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T149	8		T213	13		T221	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T243	9		T140	14		T222	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T30	2		T134	12		T136	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T5	11		T13	8		T32	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T134	11		T145	2		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	9		T14	1		T219	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T159	12		T37	1		T178	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T146	10		T16	2		T136	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T43	8		T144	12		T143	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22439

1

T1

1

T2

176

T3

3

auto[1]

auto[0]

4163

1

T1

18

T5

23

T13

36