Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_6

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26602

1

T1

19

T2

176

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22871

1

T1

19

T2

176

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3731

1

T5

13

T11

11

T13

70

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20495

1

T2

176

T4

185

T5

13

auto[1]

6107

1

T1

19

T3

3

T5

12

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22211

1

T1

19

T2

176

T3

3

auto[1]

4391

1

T11

23

T13

85

T14

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	266	1			T136	31		T186	36		T109	19
values[0]	37	1			T155	1		T214	19		T224	6
values[1]	725	1			T5	12		T43	23		T144	13
values[2]	2898	1			T1	19		T3	3		T8	2
values[3]	815	1			T11	11		T44	2		T149	19
values[4]	541	1			T5	13		T12	1		T13	9
values[5]	829	1			T14	5		T30	9		T33	17
values[6]	879	1			T12	1		T13	22		T30	19
values[7]	748	1			T13	6		T32	31		T39	12
values[8]	654	1			T14	9		T158	10		T43	6
values[9]	1107	1			T11	13		T13	61		T158	17
minimum	17103	1			T2	176		T4	185		T6	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	742	1			T5	12		T13	24		T144	13
values[1]	2938	1			T1	19		T3	3		T8	2
values[2]	711	1			T5	13		T11	11		T44	2
values[3]	548	1			T12	1		T13	9		T144	8
values[4]	893	1			T13	5		T14	5		T30	9
values[5]	870	1			T12	1		T13	17		T30	19
values[6]	682	1			T13	6		T39	12		T148	14
values[7]	715	1			T13	15		T14	9		T158	10
values[8]	999	1			T11	13		T13	46		T158	17
values[9]	175	1			T161	18		T136	31		T251	15
minimum	17329	1			T2	176		T4	185		T6	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22439

1

T1

1

T2

176

T3

3

auto[1]

4163

1

T1

18

T5

23

T13

36

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	12		T13	10		T144	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T145	3		T147	2		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1510	1			T1	19		T3	3		T8	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T141	1		T144	8		T175	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T44	1		T149	19		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T5	13		T11	1		T216	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	85	1			T12	1		T217	11		T139	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T13	1		T144	8		T143	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T13	1		T30	3		T33	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T14	5		T44	11		T77	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T12	1		T13	9		T32	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T13	2		T30	10		T45	12
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T148	8		T169	5		T140	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T13	2		T39	7		T217	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T14	1		T76	1		T145	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T13	1		T14	4		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T11	1		T13	1		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	211	1			T13	22		T141	1		T175	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T164	1		T180	3		T311	16
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T161	1		T136	16		T251	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17037	1			T2	176		T4	185		T6	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T43	23		T284	1		T249	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T13	14		T134	10		T175	6
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T145	5		T147	7		T153	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1078	1			T197	13		T216	15		T179	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T175	2		T38	2		T17	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T44	1		T16	4		T155	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T11	10		T216	10		T159	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	84	1			T139	7		T221	8		T170	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T13	8		T39	15		T242	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T13	4		T30	6		T33	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T44	12		T77	12		T134	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T13	6		T32	14		T159	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T30	9		T161	13		T214	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T148	6		T169	3		T140	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T13	4		T39	5		T34	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T76	7		T145	7		T137	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T13	14		T14	4		T158	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	296	1			T11	12		T13	7		T158	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T13	16		T141	14		T175	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T164	13		T180	5		T311	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T161	17		T136	15		T251	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T11	1		T13	12		T33	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T312	11		T313	4		T314	10

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	57	1			T109	15		T218	14		T263	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	67	1			T136	16		T186	19		T230	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T214	11		T315	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T155	1		T224	1		T226	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T5	12		T144	13		T134	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T43	23		T145	3		T147	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1456	1			T1	19		T3	3		T8	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T141	1		T144	8		T175	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T44	1		T149	19		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T11	1		T216	1		T159	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T12	1		T217	11		T221	11
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T5	13		T13	1		T144	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T30	3		T33	10		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T14	5		T44	11		T77	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T12	1		T13	10		T159	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	290	1			T13	2		T30	10		T45	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T32	17		T148	8		T169	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T13	2		T39	7		T217	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T14	1		T76	1		T145	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T14	4		T158	1		T43	6
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T11	1		T13	1		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T13	23		T141	1		T161	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16969	1			T2	176		T4	185		T6	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T109	4		T218	2		T263	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	68	1			T136	15		T186	17		T230	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	8	1			T214	8		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T224	5		T226	9		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T134	10		T175	6		T213	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T145	5		T147	7		T222	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1039	1			T13	14		T197	13		T179	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T175	2		T153	13		T191	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T44	1		T216	15		T16	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T11	10		T216	10		T159	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	44	1			T221	8		T35	10		T316	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T13	8		T39	15		T138	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T30	6		T33	7		T147	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T44	12		T77	12		T134	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T13	10		T159	8		T178	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T30	9		T161	13		T148	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T32	14		T148	6		T169	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T13	4		T39	5		T34	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T76	7		T145	7		T137	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T14	4		T158	9		T221	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T11	12		T13	7		T158	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T13	30		T141	14		T161	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	1		T13	12		T33	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T5	1		T13	15		T144	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T145	6		T147	9		T155	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1407	1			T1	1		T3	3		T8	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T141	1		T144	1		T175	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T44	2		T149	2		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T5	1		T11	11		T216	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T12	1		T217	1		T139	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	9		T144	1		T143	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T13	5		T30	7		T33	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T14	3		T44	13		T77	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	281	1			T12	1		T13	7		T32	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T13	2		T30	10		T45	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T148	7		T169	4		T140	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T13	6		T39	9		T217	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T14	1		T76	8		T145	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T13	15		T14	7		T158	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	348	1			T11	13		T13	8		T158	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T13	19		T141	15		T175	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T164	14		T180	6		T311	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	79	1			T161	18		T136	16		T251	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17172	1			T2	176		T4	185		T6	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	54	1			T43	2		T284	1		T249	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T5	11		T13	9		T144	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T145	2		T219	7		T227	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1181	1			T1	18		T228	23		T150	39
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T144	7		T175	7		T103	3
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T149	17		T146	10		T16	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T5	12		T159	12		T136	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T217	10		T139	2		T221	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T144	7		T143	11		T39	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T30	2		T33	9		T139	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T14	2		T44	10		T134	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T13	8		T32	16		T178	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T30	9		T45	11		T149	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T148	7		T169	4		T140	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T39	3		T217	11		T156	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T145	10		T154	11		T229	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T14	1		T43	5		T221	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T145	9		T176	12		T217	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T13	19		T175	5		T140	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T180	2		T311	15		-	-
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T136	15		T251	7		T230	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T213	13		T214	10		T231	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T43	21		T312	13		T313	5

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	83	1			T109	5		T218	3		T263	16
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	76	1			T136	16		T186	18		T230	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T214	9		T315	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	17	1			T155	1		T224	6		T226	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T5	1		T144	1		T134	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T43	2		T145	6		T147	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1364	1			T1	1		T3	3		T8	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T141	1		T144	1		T175	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T44	2		T149	2		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T11	11		T216	11		T159	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	66	1			T12	1		T217	1		T221	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T5	1		T13	9		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T30	7		T33	8		T147	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T14	3		T44	13		T77	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T12	1		T13	12		T159	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T13	2		T30	10		T45	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	236	1			T32	15		T148	7		T169	4
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T13	6		T39	9		T217	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T14	1		T76	8		T145	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T14	7		T158	10		T43	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	333	1			T11	13		T13	8		T158	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T13	34		T141	15		T161	18
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17103	1			T2	176		T4	185		T6	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	48	1			T109	14		T218	13		T263	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	59	1			T136	15		T186	18		T230	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T214	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T5	11		T144	12		T134	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T43	21		T145	2		T219	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1131	1			T1	18		T13	9		T228	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T144	7		T175	7		T191	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T149	17		T146	10		T16	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T159	12		T136	10		T139	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	70	1			T217	10		T221	10		T270	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	12		T144	7		T143	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T30	2		T33	9		T139	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T14	2		T44	10		T134	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T13	8		T178	6		T40	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T30	9		T45	11		T149	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T32	16		T148	7		T169	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T39	3		T217	11		T34	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T145	10		T154	11		T140	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T14	1		T43	5		T221	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T145	9		T176	12		T217	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T13	19		T175	5		T140	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22439

1

T1

1

T2

176

T3

3

auto[1]

auto[0]

4163

1

T1

18

T5

23

T13

36