Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26602

1

T1

19

T2

176

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22584

1

T1

19

T2

176

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

4018

1

T5

12

T11

24

T12

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20391

1

T2

172

T4

179

T5

13

auto[1]

6211

1

T1

19

T2

4

T3

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22211

1

T1

19

T2

176

T3

3

auto[1]

4391

1

T11

23

T13

85

T14

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	495	1			T2	4		T4	6		T9	9
values[0]	33	1			T134	26		T187	7		-	-
values[1]	611	1			T5	12		T14	9		T45	12
values[2]	3098	1			T1	19		T3	3		T5	13
values[3]	821	1			T158	17		T176	22		T17	6
values[4]	590	1			T11	13		T13	30		T30	19
values[5]	807	1			T13	9		T158	10		T134	22
values[6]	541	1			T13	1		T32	31		T44	23
values[7]	934	1			T9	1		T12	1		T13	39
values[8]	561	1			T13	12		T76	8		T145	18
values[9]	1392	1			T11	11		T12	1		T13	31
minimum	16719	1			T2	172		T4	179		T6	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	912	1			T5	25		T14	14		T45	12
values[1]	3167	1			T1	19		T3	3		T8	2
values[2]	528	1			T11	13		T149	9		T176	22
values[3]	757	1			T13	39		T30	19		T141	1
values[4]	617	1			T32	31		T158	10		T134	22
values[5]	817	1			T9	1		T12	1		T13	25
values[6]	766	1			T13	15		T43	6		T44	23
values[7]	615	1			T13	27		T33	17		T43	14
values[8]	988	1			T11	11		T12	1		T13	10
values[9]	306	1			T13	6		T175	20		T39	12
minimum	17129	1			T2	176		T4	185		T6	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22439

1

T1

1

T2

176

T3

3

auto[1]

4163

1

T1

18

T5

23

T13

36

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T5	13		T14	9		T45	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	307	1			T5	12		T14	1		T144	8
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1527	1			T1	19		T3	3		T8	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T158	1		T144	13		T143	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T17	1		T243	12		T248	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T11	1		T149	9		T176	22
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T13	2		T30	10		T145	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T13	11		T141	1		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T32	17		T154	12		T253	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T158	1		T134	12		T217	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T9	1		T144	8		T175	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T12	1		T13	11		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T13	1		T77	1		T145	11
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T43	6		T44	11		T76	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	77	1			T147	1		T137	1		T222	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T13	19		T33	10		T43	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	310	1			T13	3		T141	1		T43	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T11	1		T12	1		T216	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T175	6		T39	7		T240	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T13	2		T175	8		T221	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16969	1			T2	176		T4	185		T6	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T134	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T14	4		T145	11		T159	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T148	6		T154	7		T236	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1030	1			T30	6		T44	1		T197	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	304	1			T158	16		T40	1		T153	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T17	5		T243	13		T254	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T11	12		T140	10		T241	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T13	12		T30	9		T145	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T13	14		T161	17		T38	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T32	14		T154	2		T102	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T158	9		T134	10		T251	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T175	6		T236	11		T222	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	253	1			T13	14		T137	16		T250	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T13	14		T77	12		T145	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T44	12		T76	7		T213	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T147	7		T137	9		T222	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T13	8		T33	7		T161	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T13	7		T141	14		T139	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T11	10		T216	10		T37	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T175	4		T39	5		T240	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T13	4		T175	2		T221	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	1		T13	12		T33	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T134	13		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	413	1			T2	4		T4	6		T9	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T180	11		T166	15		T261	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T187	5		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T134	13		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	118	1			T14	4		T45	12		T145	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	214	1			T5	12		T14	1		T144	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1539	1			T1	19		T3	3		T5	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	306	1			T144	13		T143	12		T146	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T17	1		T148	1		T243	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T158	1		T176	22		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T13	1		T30	10		T178	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T11	1		T13	11		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T13	1		T145	3		T155	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T158	1		T134	12		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T32	17		T144	8		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T13	1		T44	11		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T9	1		T13	1		T77	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T12	1		T13	10		T43	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	89	1			T145	11		T159	1		T138	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T13	10		T76	1		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	402	1			T13	3		T141	1		T43	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	379	1			T11	1		T12	1		T13	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16585	1			T2	172		T4	179		T6	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T139	2		T291	4		T252	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T180	10		T166	14		T261	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T187	2		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T134	13		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T14	4		T145	11		T159	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T148	6		T154	7		T236	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1003	1			T30	6		T44	1		T197	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	250	1			T40	1		T222	12		T229	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T17	5		T148	2		T243	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T158	16		T153	13		T221	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T13	4		T30	9		T178	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T11	12		T13	14		T38	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T13	8		T145	5		T155	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T158	9		T134	10		T161	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T32	14		T175	6		T154	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T44	12		T137	16		T250	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	286	1			T13	14		T77	12		T216	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T13	14		T251	7		T199	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	82	1			T145	7		T159	8		T138	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T13	2		T76	7		T161	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	330	1			T13	7		T141	14		T147	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T11	10		T13	10		T33	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	1		T13	12		T33	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T5	1		T14	10		T45	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	293	1			T5	1		T14	1		T144	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1357	1			T1	1		T3	3		T8	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	368	1			T158	17		T144	1		T143	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T17	6		T243	14		T248	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T11	13		T149	1		T176	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T13	14		T30	10		T145	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T13	15		T141	1		T161	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T32	15		T154	3		T253	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T158	10		T134	11		T217	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	225	1			T9	1		T144	1		T175	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T12	1		T13	16		T137	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	297	1			T13	15		T77	13		T145	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T43	1		T44	13		T76	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T147	8		T137	10		T222	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T13	10		T33	8		T43	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T13	10		T141	15		T43	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	285	1			T11	11		T12	1		T216	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T175	5		T39	9		T240	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	39	1			T13	6		T175	3		T221	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17103	1			T2	176		T4	185		T6	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T134	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T5	12		T14	3		T45	11
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T5	11		T144	7		T148	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1200	1			T1	18		T30	2		T228	23
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T144	12		T143	11		T146	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T243	11		T246	15		T230	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T149	8		T176	20		T219	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T30	9		T145	2		T178	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T13	10		T169	4		T217	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T32	16		T154	11		T171	18
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T134	11		T217	18		T251	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T144	7		T175	6		T236	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T13	9		T250	12		T232	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T145	10		T136	15		T227	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T43	5		T44	10		T149	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	46	1			T229	8		T182	8		T280	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T13	17		T33	9		T43	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T43	8		T243	2		T139	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T37	1		T16	2		T39	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	87	1			T175	5		T39	3		T225	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T175	7		T221	8		T103	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T134	12		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	408	1			T2	4		T4	6		T9	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T180	11		T166	15		T261	12
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	3	1			T187	3		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T134	14		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T14	7		T45	1		T145	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T5	1		T14	1		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1332	1			T1	1		T3	3		T5	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	309	1			T144	1		T143	1		T146	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T17	6		T148	3		T243	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T158	17		T176	2		T153	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T13	5		T30	10		T178	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T11	13		T13	15		T141	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T13	9		T145	6		T155	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T158	10		T134	11		T161	18
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T32	15		T144	1		T160	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	1		T44	13		T137	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	332	1			T9	1		T13	15		T77	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T12	1		T13	15		T43	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	110	1			T145	8		T159	9		T138	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T13	3		T76	8		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	409	1			T13	10		T141	15		T43	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	365	1			T11	11		T12	1		T13	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16719	1			T2	172		T4	179		T6	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T139	1		T317	9		T252	15
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T180	10		T166	14		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T187	4		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T134	12		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T14	1		T45	11		T145	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T5	11		T144	7		T148	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1210	1			T1	18		T5	12		T14	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T144	12		T143	11		T146	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T243	11		T246	15		T218	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T176	20		T219	7		T221	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T30	9		T178	6		T214	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T13	10		T149	8		T169	4
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T145	2		T155	7		T171	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	232	1			T134	11		T217	18		T156	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T32	16		T144	7		T175	6
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	89	1			T44	10		T250	12		T232	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T136	15		T236	9		T227	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T13	9		T43	5		T149	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T145	10		T34	5		T318	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T13	9		T136	10		T213	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	323	1			T43	8		T175	5		T39	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	295	1			T13	8		T33	9		T43	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22439

1

T1

1

T2

176

T3

3

auto[1]

auto[0]

4163

1

T1

18

T5

23

T13

36