Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_3

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26602

1

T1

19

T2

176

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22750

1

T1

19

T2

176

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3852

1

T5

25

T9

1

T11

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20186

1

T2

176

T4

185

T6

14

auto[1]

6416

1

T1

19

T3

3

T5

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22211

1

T1

19

T2

176

T3

3

auto[1]

4391

1

T11

23

T13

85

T14

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	39	1			T301	21		T319	12		T300	6
values[0]	90	1			T13	8		T43	14		T216	11
values[1]	588	1			T144	8		T147	11		T16	13
values[2]	813	1			T30	9		T44	2		T77	13
values[3]	721	1			T13	1		T30	19		T141	15
values[4]	805	1			T5	12		T13	25		T14	1
values[5]	839	1			T11	11		T13	9		T14	8
values[6]	619	1			T5	13		T14	5		T33	17
values[7]	868	1			T9	1		T11	13		T13	39
values[8]	2827	1			T1	19		T3	3		T8	2
values[9]	1290	1			T12	1		T13	27		T32	31
minimum	17103	1			T2	176		T4	185		T6	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1014	1			T13	8		T30	9		T43	14
values[1]	654	1			T30	19		T44	2		T145	21
values[2]	673	1			T13	26		T158	10		T141	15
values[3]	867	1			T5	12		T11	11		T14	1
values[4]	764	1			T5	13		T13	9		T14	13
values[5]	672	1			T13	15		T33	17		T141	1
values[6]	3028	1			T1	19		T3	3		T8	2
values[7]	549	1			T12	1		T13	11		T43	6
values[8]	1074	1			T13	29		T32	31		T158	17
values[9]	179	1			T219	8		T222	2		T249	1
minimum	17128	1			T2	176		T4	185		T6	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22439

1

T1

1

T2

176

T3

3

auto[1]

4163

1

T1

18

T5

23

T13

36

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T13	1		T144	8		T147	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T30	3		T43	14		T77	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T30	10		T44	1		T145	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T147	1		T153	1		T139	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T13	1		T141	1		T216	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T13	11		T158	1		T159	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T11	1		T14	1		T216	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T5	12		T149	14		T159	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T14	4		T160	1		T39	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T5	13		T13	1		T14	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T13	9		T148	8		T41	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T33	10		T141	1		T149	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1502	1			T1	19		T3	3		T8	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	294	1			T9	1		T11	1		T134	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T12	1		T13	3		T43	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	116	1			T144	13		T217	11		T102	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T13	10		T44	11		T176	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T13	3		T32	17		T158	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	72	1			T222	1		T157	12		T297	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T219	8		T249	1		T254	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16969	1			T2	176		T4	185		T6	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T251	8		T252	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T13	7		T175	4		T214	16
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	311	1			T30	6		T77	12		T216	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T30	9		T44	1		T145	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T147	7		T153	13		T139	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	220	1			T141	14		T216	4		T175	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T13	14		T158	9		T159	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T11	10		T216	15		T17	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T159	8		T154	7		T215	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T14	4		T39	5		T148	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T13	8		T134	13		T243	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	106	1			T13	6		T148	6		T191	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T33	7		T161	13		T138	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1036	1			T13	14		T197	13		T145	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T11	12		T134	10		T145	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T13	8		T38	2		T136	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	92	1			T102	7		T230	15		T87	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T13	2		T44	12		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T13	14		T32	14		T158	16
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T222	1		T157	2		T298	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T254	9		T301	9		T303	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	1		T13	12		T33	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	16	1			T251	7		T252	9		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	5	1			T300	5		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T301	12		T319	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T13	1		T320	1		T296	20
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T43	14		T216	1		T214	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T144	8		T147	1		T243	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T16	9		T251	8		T229	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T44	1		T145	10		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T30	3		T77	1		T37	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T13	1		T30	10		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T149	14		T159	13		T153	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T14	1		T216	2		T17	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T5	12		T13	11		T158	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T11	1		T14	4		T160	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T13	1		T149	5		T154	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T148	8		T264	1		T105	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T5	13		T14	5		T33	10
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T13	19		T43	9		T145	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T9	1		T11	1		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1505	1			T1	19		T3	3		T8	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T13	2		T144	13		T178	7
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	352	1			T12	1		T13	10		T44	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	376	1			T13	1		T32	17		T158	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16969	1			T2	176		T4	185		T6	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	1	1			T300	1		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T301	9		T319	11		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T13	7		T296	9		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T216	10		T214	8		T321	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	99	1			T147	10		T214	16		T57	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T16	4		T251	7		T229	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T44	1		T145	11		T175	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	278	1			T30	6		T77	12		T37	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T30	9		T141	14		T175	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T159	13		T153	13		T139	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T216	19		T17	5		T155	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T13	14		T158	9		T159	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T11	10		T14	4		T39	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T13	8		T154	7		T236	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T148	6		T191	14		T19	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T33	7		T134	13		T161	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T13	20		T145	7		T39	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T11	12		T134	10		T145	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1040	1			T13	8		T197	13		T179	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	107	1			T178	7		T154	2		T222	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T13	2		T44	12		T40	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	334	1			T13	14		T32	14		T158	16
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	1		T13	12		T33	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T13	8		T144	1		T147	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	376	1			T30	7		T43	1		T77	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T30	10		T44	2		T145	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	217	1			T147	8		T153	14		T139	11
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T13	1		T141	15		T216	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T13	15		T158	10		T159	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	284	1			T11	11		T14	1		T216	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T5	1		T149	1		T159	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	243	1			T14	7		T160	1		T39	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T5	1		T13	9		T14	3
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T13	7		T148	7		T41	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T33	8		T141	1		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1367	1			T1	1		T3	3		T8	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T9	1		T11	13		T134	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T12	1		T13	11		T43	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T144	1		T217	1		T102	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T13	3		T44	13		T176	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	349	1			T13	17		T32	15		T158	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T222	2		T157	3		T297	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T219	1		T249	1		T254	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17103	1			T2	176		T4	185		T6	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	18	1			T251	8		T252	10		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T144	7		T175	5		T214	20
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T30	2		T43	13		T37	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T30	9		T145	9		T243	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T139	3		T170	9		T246	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T175	7		T136	15		T266	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T13	10		T159	12		T34	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T155	7		T241	10		T251	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	174	1			T5	11		T149	13		T154	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T14	1		T39	3		T221	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T5	12		T14	2		T134	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T13	8		T148	7		T105	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T33	9		T149	8		T156	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1171	1			T1	18		T13	9		T43	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T134	11		T145	2		T178	6
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T43	5		T144	7		T176	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T144	12		T217	10		T102	3
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T13	9		T44	10		T176	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T32	16		T45	11		T175	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	54	1			T157	11		T297	8		T166	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T219	7		T301	11		T183	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T251	7		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T300	4		-	-		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T301	10		T319	12		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T13	8		T320	1		T296	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T43	1		T216	11		T214	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	146	1			T144	1		T147	11		T243	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T16	11		T251	8		T229	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T44	2		T145	12		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T30	7		T77	13		T37	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T13	1		T30	10		T141	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T149	1		T159	14		T153	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T14	1		T216	21		T17	6
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T5	1		T13	15		T158	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	300	1			T11	11		T14	7		T160	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T13	9		T149	1		T154	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T148	7		T264	1		T105	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T5	1		T14	3		T33	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	185	1			T13	22		T43	1		T145	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T9	1		T11	13		T141	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1380	1			T1	1		T3	3		T8	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T13	2		T144	1		T178	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T12	1		T13	3		T44	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	393	1			T13	15		T32	15		T158	17
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17103	1			T2	176		T4	185		T6	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T300	2		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T301	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T296	19		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T43	13		T214	10		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T144	7		T243	2		T214	20
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T16	2		T251	7		T20	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T145	9		T175	5		T225	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T30	2		T37	1		T139	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	137	1			T30	9		T175	7		T136	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T149	13		T159	12		T139	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T155	7		T241	10		T171	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T5	11		T13	10		T103	3
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T14	1		T39	3		T221	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T149	4		T154	8		T236	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	101	1			T148	7		T105	16		T191	14
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T5	12		T14	2		T33	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	17		T43	8		T145	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T134	11		T149	8		T145	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	1165	1			T1	18		T43	5		T228	23
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T144	12		T178	6		T217	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T13	9		T44	10		T176	20
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	317	1			T32	16		T45	11		T175	6

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22439

1

T1

1

T2

176

T3

3

auto[1]

auto[0]

4163

1

T1

18

T5

23

T13

36