Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26602

1

T1

19

T2

176

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22993

1

T1

19

T2

176

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3609

1

T11

24

T12

1

T13

63

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20372

1

T2

176

T4

185

T5

25

auto[1]

6230

1

T1

19

T3

3

T8

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22211

1

T1

19

T2

176

T3

3

auto[1]

4391

1

T11

23

T13

85

T14

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	206	1			T13	8		T145	18		T216	11
values[0]	92	1			T136	26		T243	3		T139	4
values[1]	623	1			T5	12		T14	8		T43	15
values[2]	824	1			T13	36		T45	12		T147	8
values[3]	628	1			T158	17		T44	2		T144	8
values[4]	772	1			T11	13		T12	1		T44	23
values[5]	2796	1			T1	19		T3	3		T8	2
values[6]	926	1			T9	1		T14	6		T32	31
values[7]	653	1			T13	41		T33	17		T158	10
values[8]	937	1			T5	13		T144	8		T175	10
values[9]	1042	1			T11	11		T13	1		T141	16
minimum	17103	1			T2	176		T4	185		T6	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	739	1			T13	15		T14	8		T43	15
values[1]	847	1			T13	21		T44	2		T45	12
values[2]	673	1			T12	1		T158	17		T44	23
values[3]	2826	1			T1	19		T3	3		T8	2
values[4]	736	1			T13	12		T14	1		T30	19
values[5]	753	1			T9	1		T13	5		T14	5
values[6]	884	1			T13	36		T33	17		T158	10
values[7]	754	1			T5	13		T134	22		T176	13
values[8]	924	1			T11	11		T13	1		T141	16
values[9]	177	1			T13	8		T143	12		T156	7
minimum	17289	1			T2	176		T4	185		T5	12

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22439

1

T1

1

T2

176

T3

3

auto[1]

4163

1

T1

18

T5

23

T13

36

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T13	1		T159	13		T135	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T14	4		T43	15		T216	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T13	2		T44	1		T45	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T13	9		T149	5		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T76	1		T144	8		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	1		T158	1		T44	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1429	1			T1	19		T3	3		T8	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T11	1		T13	10		T30	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T37	2		T178	7		T217	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T13	10		T14	1		T30	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T9	1		T13	1		T32	17
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T14	5		T16	9		T236	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T13	11		T33	10		T77	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T13	3		T158	1		T144	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T5	13		T136	16		T171	19
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T134	12		T176	13		T217	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T141	2		T43	14		T145	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T11	1		T13	1		T144	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	29	1			T13	1		T156	7		T82	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T143	12		T103	12		T107	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17042	1			T2	176		T4	185		T5	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	25	1			T161	1		T136	11		T243	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T13	14		T159	13		T169	3
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	122	1			T14	4		T216	4		T139	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T13	4		T44	1		T38	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T13	6		T147	7		T39	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T76	7		T159	8		T39	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T158	16		T44	12		T148	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	953	1			T197	13		T179	17		T152	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T11	12		T13	14		T30	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T37	1		T178	7		T153	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T13	2		T30	9		T137	16
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T13	4		T32	14		T134	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T16	4		T236	12		T140	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T13	14		T33	7		T77	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T13	8		T158	9		T145	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T136	15		T242	13		T186	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T134	10		T140	2		T222	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T141	14		T145	7		T216	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T11	10		T175	6		T241	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T13	7		T82	12		T267	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T103	12		T271	13		T265	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T11	1		T13	12		T33	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T161	13		T136	15		T322	1

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T13	1		T145	11		T216	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	28	1			T42	2		T107	1		T84	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	26	1			T243	3		T139	2		T263	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T136	11		T273	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T5	12		T216	1		T159	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T14	4		T43	15		T216	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T13	3		T45	12		T38	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T13	9		T147	1		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T44	1		T144	8		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T158	1		T149	5		T39	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T76	1		T137	1		T213	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T11	1		T12	1		T44	11
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1492	1			T1	19		T3	3		T8	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T13	20		T30	13		T149	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T9	1		T32	17		T134	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T14	6		T236	9		T156	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T13	12		T33	10		T77	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T13	3		T158	1		T145	10
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T5	13		T136	16		T171	19
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T144	8		T175	6		T176	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T141	2		T43	14		T146	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	297	1			T11	1		T13	1		T144	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16969	1			T2	176		T4	185		T6	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T13	7		T145	7		T216	10
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	23	1			T42	1		T84	9		T271	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	32	1			T139	2		T263	15		T272	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T136	15		T273	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T216	15		T159	13		T169	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	111	1			T14	4		T216	4		T161	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T13	18		T38	2		T153	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T13	6		T147	7		T34	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T44	1		T159	8		T39	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	95	1			T158	16		T39	15		T148	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T76	7		T137	9		T213	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T11	12		T44	12		T161	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	996	1			T197	13		T37	1		T179	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T13	16		T30	15		T137	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T32	14		T134	13		T240	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T236	12		T242	17		T35	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T13	18		T33	7		T77	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T13	8		T158	9		T145	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T136	15		T242	13		T186	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T175	4		T140	4		T241	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T141	14		T148	6		T155	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T11	10		T134	10		T175	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	1		T13	12		T33	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T13	15		T159	14		T135	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T14	7		T43	2		T216	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T13	6		T44	2		T45	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T13	7		T149	1		T147	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T76	8		T144	1		T160	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T12	1		T158	17		T44	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1283	1			T1	1		T3	3		T8	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T11	13		T13	15		T30	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	247	1			T37	2		T178	8		T217	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T13	3		T14	1		T30	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	210	1			T9	1		T13	5		T32	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T14	3		T16	11		T236	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	231	1			T13	15		T33	8		T77	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T13	11		T158	10		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T5	1		T136	16		T171	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T134	11		T176	1		T217	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T141	16		T43	1		T145	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	246	1			T11	11		T13	1		T144	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T13	8		T156	1		T82	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T143	1		T103	13		T107	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17167	1			T2	176		T4	185		T5	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T161	14		T136	16		T243	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T159	12		T169	4		T217	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T14	1		T43	13		T139	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T45	11		T57	5		T192	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	139	1			T13	8		T149	4		T39	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T144	7		T39	3		T213	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T44	10		T149	8		T154	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1099	1			T1	18		T228	23		T150	39
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T13	9		T30	2		T175	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T37	1		T178	6		T217	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T13	9		T30	9		T149	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T32	16		T134	12		T225	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T14	2		T16	2		T236	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T13	10		T33	9		T145	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T144	7		T145	9		T175	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T5	12		T136	15		T171	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T134	11		T176	12		T217	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	260	1			T43	13		T145	10		T146	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T144	12		T175	6		T241	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T156	6		T82	11		T255	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T143	11		T103	11		T276	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	61	1			T5	11		T243	2		T139	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T136	10		T243	9		T322	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T13	8		T145	8		T216	11
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	29	1			T42	2		T107	1		T84	10
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T243	1		T139	3		T263	16
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T136	16		T273	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T5	1		T216	16		T159	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T14	7		T43	2		T216	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T13	21		T45	1		T38	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	226	1			T13	7		T147	8		T137	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	250	1			T44	2		T144	1		T160	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T158	17		T149	1		T39	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T76	8		T137	10		T213	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	269	1			T11	13		T12	1		T44	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1338	1			T1	1		T3	3		T8	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T13	18		T30	17		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T9	1		T32	15		T134	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T14	4		T236	13		T156	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T13	20		T33	8		T77	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T13	11		T158	10		T145	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T5	1		T136	16		T171	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T144	1		T175	5		T176	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T141	16		T43	1		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	318	1			T11	11		T13	1		T144	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17103	1			T2	176		T4	185		T6	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T145	10		T91	11		T182	8
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T42	1		T271	12		T238	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T243	2		T139	1		T263	9
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T136	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T5	11		T159	12		T169	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T14	1		T43	13		T243	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	187	1			T45	11		T139	9		T57	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T13	8		T34	11		T232	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T144	7		T39	3		T154	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	103	1			T149	4		T39	2		T221	8
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T213	13		T215	8		T103	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T44	10		T149	8		T175	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1150	1			T1	18		T228	23		T37	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T13	18		T30	11		T149	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T32	16		T134	12		T219	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T14	2		T236	8		T156	14
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T13	10		T33	9		T145	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T145	9		T16	2		T140	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	168	1			T5	12		T136	15		T171	18
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T144	7		T175	5		T176	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T43	13		T146	10		T148	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T144	12		T134	11		T143	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22439

1

T1

1

T2

176

T3

3

auto[1]

auto[0]

4163

1

T1

18

T5

23

T13

36