Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_7

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26602

1

T1

19

T2

176

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

20529

1

T2

176

T4

185

T6

14

auto[ADC_CTRL_FILTER_COND_OUT]

6073

1

T1

19

T3

3

T5

25

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20619

1

T2

176

T4

185

T5

25

auto[1]

5983

1

T1

19

T3

3

T8

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22211

1

T1

19

T2

176

T3

3

auto[1]

4391

1

T11

23

T13

85

T14

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	264	1			T148	14		T155	12		T217	8
values[0]	52	1			T16	13		T233	25		T238	14
values[1]	835	1			T12	1		T32	31		T43	9
values[2]	780	1			T14	8		T30	19		T43	6
values[3]	662	1			T13	24		T30	9		T45	12
values[4]	797	1			T13	29		T14	1		T141	1
values[5]	790	1			T13	6		T158	10		T43	14
values[6]	717	1			T9	1		T13	38		T141	15
values[7]	787	1			T11	13		T13	10		T33	17
values[8]	684	1			T13	15		T14	5		T158	17
values[9]	3131	1			T1	19		T3	3		T5	25
minimum	17103	1			T2	176		T4	185		T6	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	852	1			T30	19		T32	31		T43	6
values[1]	2882	1			T1	19		T3	3		T8	2
values[2]	764	1			T13	48		T30	9		T141	1
values[3]	798	1			T13	5		T14	1		T158	10
values[4]	714	1			T9	1		T13	6		T43	14
values[5]	778	1			T13	38		T141	15		T144	8
values[6]	809	1			T11	13		T13	10		T33	17
values[7]	664	1			T5	25		T13	15		T14	5
values[8]	861	1			T11	11		T12	1		T145	18
values[9]	181	1			T148	14		T139	19		T140	9
minimum	17299	1			T2	176		T4	185		T6	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22439

1

T1

1

T2

176

T3

3

auto[1]

4163

1

T1

18

T5

23

T13

36

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T32	17		T77	1		T38	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T30	10		T43	6		T44	11
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T149	9		T225	11		T157	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1539	1			T1	19		T3	3		T8	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T30	3		T141	1		T149	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T13	12		T45	12		T143	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T149	14		T147	1		T175	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T13	1		T14	1		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T13	2		T145	3		T161	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T9	1		T43	14		T159	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T13	21		T135	1		T40	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T13	1		T141	1		T144	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T13	2		T33	10		T144	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T11	1		T13	1		T44	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T14	5		T160	1		T216	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T5	25		T13	9		T158	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T11	1		T12	1		T175	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T145	11		T137	1		T169	5
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	42	1			T148	8		T139	10		T272	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	50	1			T140	5		T164	1		T187	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17033	1			T2	176		T4	185		T6	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T12	1		T16	9		T171	19
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T32	14		T77	12		T38	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T30	9		T44	12		T134	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T225	7		T157	2		T230	15
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1035	1			T14	4		T197	13		T134	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T30	6		T216	15		T236	11
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T13	36		T199	11		T57	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T147	7		T175	6		T136	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T13	4		T158	9		T76	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T13	4		T145	5		T161	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T159	8		T161	13		T139	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T13	16		T40	1		T136	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T141	14		T170	9		T237	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T33	7		T148	8		T138	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T11	12		T13	7		T44	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T216	4		T147	10		T175	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T13	6		T158	16		T236	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T11	10		T175	2		T39	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T145	7		T137	16		T169	3
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T148	6		T139	9		T194	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T140	4		T164	13		T187	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T11	1		T13	12		T33	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	44	1			T16	4		T35	12		T234	14

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	52	1			T148	8		T139	10		T222	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	98	1			T155	8		T217	8		T164	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T233	14		T238	8		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T16	9		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T32	17		T43	9		T77	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T12	1		T44	11		T134	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T149	9		T38	3		T176	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T14	4		T30	10		T43	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T30	3		T149	5		T236	10
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T13	10		T45	12		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T141	1		T149	14		T216	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T13	3		T14	1		T76	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T13	2		T145	3		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T158	1		T43	14		T161	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T13	21		T17	1		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T9	1		T13	1		T141	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T13	2		T33	10		T144	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T11	1		T13	1		T44	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T14	5		T216	1		T148	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T13	9		T158	1		T236	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T11	1		T12	1		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1647	1			T1	19		T3	3		T5	25
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16969	1			T2	176		T4	185		T6	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	36	1			T148	6		T139	9		T222	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	78	1			T155	4		T164	13		T297	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	17	1			T233	11		T238	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T16	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	153	1			T32	14		T77	12		T221	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T44	12		T134	13		T178	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T38	2		T225	7		T157	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T14	4		T30	9		T134	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	124	1			T30	6		T236	11		T103	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T13	14		T213	12		T57	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	209	1			T216	15		T147	7		T175	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	26		T76	7		T148	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	139	1			T13	4		T145	5		T161	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T158	9		T161	13		T39	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T13	16		T17	5		T40	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T141	14		T159	8		T170	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T33	7		T138	10		T154	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T11	12		T13	7		T44	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	121	1			T216	4		T148	8		T140	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T13	6		T158	16		T236	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T11	10		T147	10		T175	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1103	1			T197	13		T145	7		T179	17
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	1		T13	12		T33	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T32	15		T77	13		T38	5
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T30	10		T43	1		T44	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T149	1		T225	8		T157	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1370	1			T1	1		T3	3		T8	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T30	7		T141	1		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T13	39		T45	1		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T149	1		T147	8		T175	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T13	5		T14	1		T158	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	6		T145	6		T161	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T9	1		T43	1		T159	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T13	18		T135	1		T40	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	242	1			T13	1		T141	15		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T13	2		T33	8		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T11	13		T13	8		T44	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T14	3		T160	1		T216	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T5	2		T13	7		T158	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T11	11		T12	1		T175	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	280	1			T145	8		T137	17		T169	4
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T148	7		T139	10		T272	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	56	1			T140	5		T164	14		T187	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17144	1			T2	176		T4	185		T6	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	57	1			T12	1		T16	11		T171	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T32	16		T176	8		T221	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T30	9		T43	5		T44	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T149	8		T225	10		T157	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1204	1			T1	18		T14	1		T228	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T30	2		T149	4		T236	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T13	9		T45	11		T143	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T149	13		T175	6		T136	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	113	1			T39	2		T251	7		T103	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T145	2		T154	11		T245	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T43	13		T139	1		T241	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T13	19		T40	1		T136	15
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T144	7		T170	9		T242	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T33	9		T144	7		T154	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T37	1		T146	10		T243	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T14	2		T175	5		T217	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T5	23		T13	8		T144	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T175	7		T39	3		T214	20
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T145	10		T169	4		T155	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	33	1			T148	7		T139	9		T194	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T140	4		T187	9		T183	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T43	8		T192	2		T272	1
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	48	1			T16	2		T171	18		T35	14

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	47	1			T148	7		T139	10		T222	2
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	90	1			T155	5		T217	1		T164	14
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T233	12		T238	7		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T16	11		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T32	15		T43	1		T77	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T12	1		T44	13		T134	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T149	1		T38	5		T176	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T14	7		T30	10		T43	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T30	7		T149	1		T236	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T13	15		T45	1		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T141	1		T149	1		T216	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T13	29		T14	1		T76	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	6		T145	6		T161	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	320	1			T158	10		T43	1		T161	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T13	18		T17	6		T135	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T9	1		T13	1		T141	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	258	1			T13	2		T33	8		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T11	13		T13	8		T44	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T14	3		T216	5		T148	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T13	7		T158	17		T236	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	251	1			T11	11		T12	1		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1460	1			T1	1		T3	3		T5	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17103	1			T2	176		T4	185		T6	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	41	1			T148	7		T139	9		T18	1
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T155	7		T217	7		T182	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T233	13		T238	7		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T16	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T32	16		T43	8		T221	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T44	10		T134	12		T178	6
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T149	8		T176	8		T232	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T14	1		T30	9		T43	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T30	2		T149	4		T236	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T13	9		T45	11		T213	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T149	13		T175	6		T136	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T143	11		T251	7		T199	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T145	2		T154	11		T245	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T43	13		T39	2		T139	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T13	19		T40	1		T136	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T144	7		T170	9		T242	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T33	9		T144	7		T243	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T37	1		T146	10		T243	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T14	2		T217	11		T156	16
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	150	1			T13	8		T236	8		T221	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	130	1			T175	12		T39	3		T156	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1290	1			T1	18		T5	23		T228	23

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22439

1

T1

1

T2

176

T3

3

auto[1]

auto[0]

4163

1

T1

18

T5

23

T13

36