Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_7

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	263	1			T32	15		T43	1		T77	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T12	1		T30	10		T43	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T149	1		T232	1		T157	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1375	1			T1	1		T3	3		T8	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	175	1			T30	7		T141	1		T149	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T13	39		T45	1		T143	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	194	1			T149	1		T147	8		T175	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T13	5		T14	1		T158	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T13	6		T145	6		T161	18
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T9	1		T43	1		T159	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T13	18		T135	1		T40	5
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	256	1			T13	1		T141	15		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T13	2		T33	8		T144	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T11	13		T13	8		T44	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T14	3		T160	1		T216	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T5	2		T13	7		T158	17
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T11	11		T12	1		T39	9
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T144	1		T145	8		T137	17
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T175	3		T148	7		T139	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	66	1			T140	5		T164	14		T183	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17103	1			T2	176		T4	185		T6	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T234	15		T235	12		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	266	1			T32	16		T43	8		T176	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T30	9		T43	5		T44	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T149	8		T232	12		T157	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	1212	1			T1	18		T14	1		T228	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T30	2		T149	4		T236	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T13	9		T45	11		T143	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T149	13		T175	6		T136	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T39	2		T103	11		T109	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T145	2		T136	15		T154	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T43	13		T139	1		T241	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T13	19		T40	1		T154	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T144	7		T170	9		T242	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T33	9		T144	7		T243	9
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T37	1		T146	10		T243	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	98	1			T14	2		T175	5		T217	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T5	23		T13	8		T236	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T39	3		T214	20		T191	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	260	1			T144	12		T145	10		T169	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	40	1			T175	7		T148	7		T139	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T140	4		T183	4		T244	16

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	7	41	85.42	7

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	27	1			T192	8		T233	12		T238	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	20	1			T16	11		T233	8		T239	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T32	15		T43	1		T77	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T12	1		T14	7		T43	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T149	1		T38	5		T176	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T13	15		T30	10		T134	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T30	7		T149	1		T147	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T45	1		T160	1		T155	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	268	1			T141	1		T149	1		T216	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T13	29		T14	1		T43	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T13	6		T145	6		T161	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T158	10		T144	1		T161	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T13	18		T135	1		T40	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T9	1		T13	1		T141	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T13	2		T33	8		T147	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T11	13		T13	8		T44	2
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T14	3		T144	1		T216	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	265	1			T13	7		T158	17		T144	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T11	11		T12	1		T160	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1568	1			T1	1		T3	3		T5	2
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17103	1			T2	176		T4	185		T6	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T192	2		T233	13		T238	7
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	21	1			T16	2		T233	6		T239	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T32	16		T43	8		T221	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T14	1		T43	5		T44	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T149	8		T176	8		T232	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T13	9		T30	9		T134	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T30	2		T149	4		T236	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T45	11		T213	13		T57	5
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T149	13		T175	6		T136	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T43	13		T143	11		T39	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T145	2		T154	11		T245	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T144	7		T139	1		T34	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	145	1			T13	19		T40	1		T136	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T241	10		T170	9		T242	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T33	9		T243	9		T154	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T37	1		T146	10		T243	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T14	2		T144	7		T217	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T13	8		T144	12		T169	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T175	12		T39	3		T148	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	1370	1			T1	18		T5	23		T228	23

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22439

1

T1

1

T2

176

T3

3

auto[1]

auto[0]

4163

1

T1

18

T5

23

T13

36