Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_0_0

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26602

1

T1

19

T2

176

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22890

1

T1

19

T2

176

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3712

1

T5

25

T11

24

T12

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19974

1

T2

172

T4

179

T5

12

auto[1]

6628

1

T1

19

T2

4

T3

3

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22211

1

T1

19

T2

176

T3

3

auto[1]

4391

1

T11

23

T13

85

T14

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	735	1			T2	4		T4	6		T9	9
values[0]	8	1			T187	7		T258	1		-	-
values[1]	665	1			T5	12		T14	9		T45	12
values[2]	3071	1			T1	19		T3	3		T5	13
values[3]	825	1			T30	9		T158	17		T149	9
values[4]	591	1			T11	13		T13	39		T30	19
values[5]	782	1			T158	10		T134	22		T145	8
values[6]	514	1			T13	1		T32	31		T144	8
values[7]	952	1			T9	1		T12	1		T13	39
values[8]	598	1			T13	12		T145	18		T160	1
values[9]	1142	1			T11	11		T12	1		T13	29
minimum	16719	1			T2	172		T4	179		T6	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	728	1			T5	25		T14	13		T149	14
values[1]	3120	1			T1	19		T3	3		T8	2
values[2]	579	1			T11	13		T149	9		T176	22
values[3]	729	1			T13	39		T30	19		T141	1
values[4]	716	1			T32	31		T158	10		T134	22
values[5]	662	1			T9	1		T13	1		T144	8
values[6]	836	1			T12	1		T13	39		T43	6
values[7]	606	1			T13	27		T33	17		T43	14
values[8]	1025	1			T11	11		T12	1		T13	10
values[9]	294	1			T13	6		T216	11		T175	20
minimum	17307	1			T2	176		T4	185		T6	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22439

1

T1

1

T2

176

T3

3

auto[1]

4163

1

T1

18

T5

23

T13

36

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T14	9		T149	14		T147	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T5	25		T148	8		T243	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1582	1			T1	19		T3	3		T8	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	215	1			T30	3		T158	1		T44	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T176	22		T17	1		T243	12
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T11	1		T149	9		T241	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T13	1		T30	10		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T13	12		T161	1		T38	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T32	17		T154	12		T253	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T158	1		T134	12		T217	20
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T9	1		T160	1		T175	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	1		T144	8		T137	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T13	1		T44	11		T77	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T12	1		T13	10		T43	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	92	1			T161	1		T147	1		T136	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T13	19		T33	10		T43	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T13	2		T16	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	335	1			T11	1		T12	1		T13	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T13	2		T175	8		T253	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	43	1			T216	1		T175	6		T221	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17043	1			T2	176		T4	185		T6	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T14	1		T144	8		T134	13
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T14	4		T147	10		T236	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T148	6		T154	7		T140	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1068	1			T197	13		T179	17		T40	1
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	255	1			T30	6		T158	16		T44	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T17	5		T243	13		T153	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	130	1			T11	12		T241	8		T222	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T13	4		T30	9		T145	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T13	22		T161	17		T38	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T32	14		T154	2		T251	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T158	9		T134	10		T259	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T175	6		T222	1		T250	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T137	16		T236	11		T260	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T13	14		T44	12		T77	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T13	14		T76	7		T213	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T161	13		T147	7		T136	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T13	8		T33	7		T139	9
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T240	11		T139	7		T221	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T11	10		T13	7		T141	14
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	86	1			T13	4		T175	2		T34	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	38	1			T216	10		T175	4		T221	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T11	1		T13	12		T33	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T134	13		T42	1		T261	12

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	507	1			T2	4		T4	6		T9	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T175	6		T39	3		T243	3
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	6	1			T187	5		T258	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	149	1			T14	4		T45	12		T145	10
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T5	12		T14	1		T144	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1570	1			T1	19		T3	3		T8	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	257	1			T5	13		T44	1		T144	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	293	1			T176	22		T17	1		T243	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T30	3		T158	1		T149	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T13	1		T30	10		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	159	1			T11	1		T13	12		T161	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T145	3		T251	15		T171	19
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T158	1		T134	12		T155	8
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T32	17		T160	1		T175	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T13	1		T144	8		T137	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T9	1		T13	1		T44	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T12	1		T13	10		T43	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T145	11		T159	1		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T13	10		T160	1		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	252	1			T13	2		T147	1		T175	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	411	1			T11	1		T12	1		T13	10
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16585	1			T2	172		T4	179		T6	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T139	7		T34	10		T225	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T175	4		T39	15		T139	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	2	1			T187	2		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	136	1			T14	4		T145	11		T159	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T134	13		T148	6		T154	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1023	1			T197	13		T179	17		T147	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	221	1			T44	1		T216	4		T222	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T17	5		T243	13		T153	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T30	6		T158	16		T153	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	127	1			T13	4		T30	9		T178	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T11	12		T13	22		T161	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T145	5		T251	13		T191	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T158	9		T134	10		T155	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	100	1			T32	14		T175	6		T154	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T137	16		T260	10		T103	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	334	1			T13	14		T44	12		T77	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T13	14		T76	7		T236	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T145	7		T159	8		T161	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	115	1			T13	2		T213	12		T139	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T13	4		T147	7		T175	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T11	10		T13	13		T33	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	1		T13	12		T33	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T14	10		T149	1		T147	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T5	2		T148	7		T243	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1408	1			T1	1		T3	3		T8	2
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T30	7		T158	17		T44	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T176	2		T17	6		T243	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T11	13		T149	1		T241	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T13	5		T30	10		T141	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T13	24		T161	18		T38	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	197	1			T32	15		T154	3		T253	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T158	10		T134	11		T217	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T9	1		T160	1		T175	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	264	1			T13	1		T144	1		T137	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	359	1			T13	15		T44	13		T77	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T12	1		T13	15		T43	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T161	14		T147	8		T136	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T13	10		T33	8		T43	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T13	2		T16	1		T135	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	338	1			T11	11		T12	1		T13	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T13	6		T175	3		T253	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	49	1			T216	11		T175	5		T221	8
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17171	1			T2	176		T4	185		T6	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T14	1		T144	1		T134	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	132	1			T14	3		T149	13		T236	8
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T5	23		T148	7		T243	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	1242	1			T1	18		T228	23		T143	11
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T30	2		T144	12		T146	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T176	20		T243	11		T219	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T149	8		T241	10		T222	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T30	9		T145	2		T178	6
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T13	10		T155	7		T221	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T32	16		T154	11		T251	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T134	11		T217	18		T259	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	95	1			T175	6		T250	12		T262	14
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T144	7		T236	9		T232	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T44	10		T145	10		T136	15
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T13	9		T43	5		T149	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	63	1			T136	10		T229	8		T263	9
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T13	17		T33	9		T43	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T139	2		T221	8		T34	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	261	1			T43	8		T37	1		T16	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	109	1			T175	7		T34	11		T225	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T175	5		T221	8		T103	4
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	64	1			T45	11		T145	9		T159	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	30	1			T144	7		T134	12		T42	1

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[values[0]]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	539	1			T2	4		T4	6		T9	9
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	65	1			T175	5		T39	16		T243	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T187	3		T258	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T14	7		T45	1		T145	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T5	1		T14	1		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1365	1			T1	1		T3	3		T8	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T5	1		T44	2		T144	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T176	2		T17	6		T243	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T30	7		T158	17		T149	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T13	5		T30	10		T141	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T11	13		T13	24		T161	18
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T145	6		T251	14		T171	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T158	10		T134	11		T155	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T32	15		T160	1		T175	7
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	185	1			T13	1		T144	1		T137	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	382	1			T9	1		T13	15		T44	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T12	1		T13	15		T43	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T145	8		T159	9		T161	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T13	3		T160	1		T155	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T13	6		T147	8		T175	3
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	388	1			T11	11		T12	1		T13	15
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16719	1			T2	172		T4	179		T6	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T139	2		T34	11		T225	4
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	35	1			T175	5		T39	2		T243	2
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T187	4		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T14	1		T45	11		T145	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T5	11		T144	7		T134	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	1228	1			T1	18		T14	2		T228	23
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	212	1			T5	12		T144	12		T146	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T176	20		T243	11		T219	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	104	1			T30	2		T149	8		T221	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T30	9		T178	6		T169	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T13	10		T140	14		T241	10
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	164	1			T145	2		T251	14		T171	18
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T134	11		T155	7		T217	18
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T32	16		T175	6		T154	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T144	7		T232	12		T103	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T44	10		T136	15		T251	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T13	9		T43	5		T149	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	103	1			T145	10		T136	10		T229	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	9		T213	13		T139	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T175	7		T221	8		T34	5
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	328	1			T13	8		T33	9		T43	21

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22439

1

T1

1

T2

176

T3

3

auto[1]

auto[0]

4163

1

T1

18

T5

23

T13

36