Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_5

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26602

1

T1

19

T2

176

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

22532

1

T1

19

T2

176

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

4070

1

T5

13

T9

1

T11

11

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20392

1

T2

176

T4

185

T6

14

auto[1]

6210

1

T1

19

T3

3

T5

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22211

1

T1

19

T2

176

T3

3

auto[1]

4391

1

T11

23

T13

85

T14

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	43	1			T13	8		T264	1		T230	20
values[0]	93	1			T43	14		T199	24		T157	2
values[1]	804	1			T5	13		T12	1		T13	30
values[2]	758	1			T13	24		T44	23		T144	8
values[3]	772	1			T12	1		T13	9		T44	2
values[4]	2903	1			T1	19		T3	3		T8	2
values[5]	811	1			T11	24		T141	15		T149	9
values[6]	664	1			T30	9		T134	26		T160	1
values[7]	775	1			T5	12		T9	1		T13	15
values[8]	738	1			T13	30		T14	8		T141	1
values[9]	1138	1			T158	27		T43	9		T45	12
minimum	17103	1			T2	176		T4	185		T6	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	1186	1			T5	13		T12	1		T13	54
values[1]	586	1			T44	23		T160	1		T147	8
values[2]	830	1			T12	1		T13	15		T44	2
values[3]	2985	1			T1	19		T3	3		T8	2
values[4]	794	1			T11	11		T30	9		T149	9
values[5]	584	1			T9	1		T32	31		T134	26
values[6]	736	1			T5	12		T13	17		T141	1
values[7]	746	1			T13	28		T14	8		T134	22
values[8]	745	1			T158	10		T43	9		T45	12
values[9]	305	1			T13	8		T158	17		T216	11
minimum	17105	1			T2	176		T4	185		T6	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22439

1

T1

1

T2

176

T3

3

auto[1]

4163

1

T1

18

T5

23

T13

36

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T12	1		T13	21		T14	6
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	415	1			T5	13		T13	1		T43	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	143	1			T44	11		T175	8		T243	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	206	1			T160	1		T147	1		T222	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T12	1		T13	1		T44	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T13	2		T145	11		T39	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1507	1			T1	19		T3	3		T8	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T30	10		T144	8		T145	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T39	7		T155	1		T154	9
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T11	1		T30	3		T149	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T32	17		T149	19		T160	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T9	1		T134	13		T145	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T5	12		T13	11		T176	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T141	1		T159	1		T178	7
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T13	12		T14	4		T219	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T134	12		T143	12		T216	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T158	1		T45	12		T136	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	254	1			T43	9		T144	13		T176	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	96	1			T158	1		T146	11		T16	9
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	47	1			T13	1		T216	1		T175	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16970	1			T2	176		T4	185		T6	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T254	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T13	28		T77	12		T161	17
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	352	1			T13	4		T76	7		T161	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	125	1			T44	12		T175	2		T140	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	112	1			T147	7		T222	1		T191	14
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T13	8		T44	1		T147	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	245	1			T13	4		T145	7		T39	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1018	1			T11	12		T33	7		T141	14
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T30	9		T145	11		T153	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	117	1			T39	5		T154	7		T222	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T11	10		T30	6		T148	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	115	1			T32	14		T216	15		T38	2
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T134	13		T145	5		T40	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T13	6		T169	3		T236	23
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T159	8		T178	7		T155	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T13	16		T14	4		T221	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T134	10		T216	4		T159	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	155	1			T158	9		T136	15		T221	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T17	5		T139	2		T254	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T158	16		T16	4		T154	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T13	7		T216	10		T175	6
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	1		T13	12		T33	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T230	10		T265	1		T226	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	2	1			T13	1		T264	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T199	13		T165	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	41	1			T43	14		T157	1		T263	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T12	1		T13	11		T14	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	244	1			T5	13		T13	1		T76	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T13	10		T44	11		T144	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	315	1			T160	1		T147	1		T251	15
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T12	1		T13	1		T44	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T145	11		T137	1		T222	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1496	1			T1	19		T3	3		T8	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T13	2		T30	10		T144	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T11	1		T141	1		T39	7
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T11	1		T149	9		T213	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	144	1			T160	1		T243	10		T140	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T30	3		T134	13		T136	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T5	12		T13	9		T32	17
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T9	1		T134	12		T145	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T13	14		T14	4		T219	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T141	1		T159	13		T37	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T158	2		T45	12		T146	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T43	9		T144	13		T143	12
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16969	1			T2	176		T4	185		T6	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	22	1			T230	10		T265	3		T226	9
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T13	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T199	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	27	1			T157	1		T263	11		T252	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	141	1			T13	14		T77	12		T161	17
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	224	1			T13	4		T76	7		T161	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	126	1			T13	14		T44	12		T175	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T147	7		T251	13		T229	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T13	8		T44	1		T147	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T145	7		T137	16		T222	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	940	1			T33	7		T197	13		T179	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T13	4		T30	9		T145	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T11	12		T141	14		T39	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T11	10		T213	12		T221	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	105	1			T140	2		T222	12		T227	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T30	6		T134	13		T136	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T13	6		T32	14		T216	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	143	1			T134	10		T145	5		T216	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T13	16		T14	4		T236	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	162	1			T159	13		T37	1		T178	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	257	1			T158	25		T16	4		T136	15
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T216	10		T175	10		T17	5
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	1		T13	12		T33	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T12	1		T13	30		T14	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	423	1			T5	1		T13	5		T43	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T44	13		T175	3		T243	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T160	1		T147	8		T222	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T12	1		T13	9		T44	2
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	296	1			T13	6		T145	8		T39	16
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1350	1			T1	1		T3	3		T8	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T30	10		T144	1		T145	12
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	150	1			T39	9		T155	1		T154	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	323	1			T11	11		T30	7		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T32	15		T149	2		T160	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T9	1		T134	14		T145	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T5	1		T13	9		T176	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T141	1		T159	9		T178	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T13	19		T14	7		T219	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T134	11		T143	1		T216	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T158	10		T45	1		T136	16
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T43	1		T144	1		T176	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	114	1			T158	17		T146	1		T16	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	82	1			T13	8		T216	11		T175	7
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17104	1			T2	176		T4	185		T6	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T254	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T13	19		T14	2		T43	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	344	1			T5	12		T43	13		T251	14
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	111	1			T44	10		T175	7		T243	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	173	1			T191	14		T262	14		T257	12
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T156	22		T245	19		T192	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T145	10		T39	2		T170	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1175	1			T1	18		T33	9		T228	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T30	9		T144	7		T145	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	81	1			T39	3		T154	8		T222	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	240	1			T30	2		T149	8		T148	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T32	16		T149	17		T243	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	146	1			T134	12		T145	2		T40	1
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	188	1			T5	11		T13	8		T176	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T178	6		T155	7		T266	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T13	9		T14	1		T219	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T134	11		T143	11		T159	12
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T45	11		T136	10		T221	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T43	8		T144	12		T176	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	73	1			T146	10		T16	2		T154	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	36	1			T175	6		T217	10		T103	11

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T230	11		T265	4		T226	10
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T13	8		T264	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T199	14		T165	1		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	37	1			T43	1		T157	2		T263	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T12	1		T13	15		T14	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T5	1		T13	5		T76	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	161	1			T13	15		T44	13		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	241	1			T160	1		T147	8		T251	14
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T12	1		T13	9		T44	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	231	1			T145	8		T137	17		T222	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1265	1			T1	1		T3	3		T8	2
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	279	1			T13	6		T30	10		T144	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	174	1			T11	13		T141	15		T39	9
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	303	1			T11	11		T149	1		T213	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	133	1			T160	1		T243	1		T140	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T30	7		T134	14		T136	16
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T5	1		T13	7		T32	15
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	175	1			T9	1		T134	11		T145	6
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	232	1			T13	21		T14	7		T219	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T141	1		T159	14		T37	2
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	316	1			T158	27		T45	1		T146	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	333	1			T43	1		T144	1		T143	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17103	1			T2	176		T4	185		T6	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T230	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T199	10		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	31	1			T43	13		T252	15		T58	3
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T13	10		T14	2		T43	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T5	12		T34	5		T171	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	88	1			T13	9		T44	10		T144	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	268	1			T251	14		T229	8		T225	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	158	1			T156	22		T192	2		T162	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T145	10		T214	20		T232	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	1171	1			T1	18		T33	9		T228	23
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T30	9		T144	7		T145	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	107	1			T39	3		T154	8		T139	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	227	1			T149	8		T213	13		T221	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	116	1			T243	9		T140	14		T222	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T30	2		T134	12		T136	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T5	11		T13	8		T32	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T134	11		T145	2		T40	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T13	9		T14	1		T219	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	124	1			T159	12		T37	1		T178	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	217	1			T45	11		T146	10		T16	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	272	1			T43	8		T144	12		T143	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22439

1

T1

1

T2

176

T3

3

auto[1]

auto[0]

4163

1

T1

18

T5

23

T13

36