Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_1

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26602

1

T1

19

T2

176

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23056

1

T1

19

T2

176

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3546

1

T11

24

T12

2

T13

63

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20291

1

T2

176

T4

185

T5

25

auto[1]

6311

1

T1

19

T3

3

T8

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22211

1

T1

19

T2

176

T3

3

auto[1]

4391

1

T11

23

T13

85

T14

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	44	1			T259	28		T267	13		T268	3
values[0]	88	1			T136	26		T243	3		T263	25
values[1]	652	1			T5	12		T14	8		T43	15
values[2]	824	1			T13	36		T158	17		T45	12
values[3]	567	1			T44	2		T144	8		T149	5
values[4]	850	1			T11	13		T12	1		T13	24
values[5]	2805	1			T1	19		T3	3		T8	2
values[6]	847	1			T9	1		T14	6		T32	31
values[7]	673	1			T13	41		T33	17		T77	13
values[8]	961	1			T5	13		T144	8		T175	10
values[9]	1188	1			T11	11		T13	9		T141	16
minimum	17103	1			T2	176		T4	185		T6	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	907	1			T5	12		T13	15		T14	8
values[1]	865	1			T13	21		T44	2		T45	12
values[2]	693	1			T12	1		T158	17		T44	23
values[3]	2766	1			T1	19		T3	3		T8	2
values[4]	801	1			T13	36		T14	1		T30	19
values[5]	718	1			T9	1		T13	5		T14	5
values[6]	853	1			T13	36		T158	10		T77	13
values[7]	768	1			T5	13		T33	17		T134	22
values[8]	963	1			T11	11		T13	9		T141	16
values[9]	151	1			T143	12		T156	7		T103	24
minimum	17117	1			T2	176		T4	185		T6	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22439

1

T1

1

T2

176

T3

3

auto[1]

4163

1

T1

18

T5

23

T13

36

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	343	1			T5	12		T13	1		T14	4
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	183	1			T43	9		T216	1		T16	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T13	2		T44	1		T45	12
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T13	9		T149	5		T147	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T76	1		T160	1		T159	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T12	1		T158	1		T44	11
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1432	1			T1	19		T3	3		T8	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	189	1			T11	1		T12	1		T30	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T32	17		T37	2		T178	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T13	20		T14	1		T30	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	157	1			T9	1		T13	1		T134	13
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T14	5		T16	9		T236	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T13	11		T77	1		T145	3
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T13	3		T158	1		T144	8
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T5	13		T33	10		T146	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T134	12		T217	12		T140	15
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	265	1			T13	1		T141	2		T43	14
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	235	1			T11	1		T13	1		T144	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T156	7		T267	1		T269	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	74	1			T143	12		T103	12		T107	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16969	1			T2	176		T4	185		T6	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T161	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T13	14		T14	4		T216	15
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	128	1			T216	4		T136	15		T139	7
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	223	1			T13	4		T44	1		T38	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	208	1			T13	6		T147	7		T39	15
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T76	7		T159	8		T39	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	117	1			T158	16		T44	12		T138	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	949	1			T197	13		T179	17		T152	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T11	12		T30	6		T161	17
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T32	14		T37	1		T178	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T13	16		T30	9		T153	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	135	1			T13	4		T134	13		T240	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T16	4		T236	12		T140	10
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T13	14		T77	12		T145	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T13	8		T158	9		T145	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T33	7		T40	1		T136	15
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T134	10		T140	2		T222	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	234	1			T13	7		T141	14		T148	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	229	1			T11	10		T145	7		T216	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	25	1			T267	12		T270	2		T255	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	32	1			T103	12		T271	13		T265	3
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	1		T13	12		T33	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T161	13		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	4	1			T267	1		T268	3		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T259	15		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T243	3		T263	10		T272	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T136	11		T273	1		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T5	12		T14	4		T43	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	120	1			T43	9		T216	1		T161	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	233	1			T13	3		T45	12		T153	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	192	1			T13	9		T158	1		T147	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T44	1		T160	1		T159	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T144	8		T149	5		T39	3
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	162	1			T76	1		T137	1		T213	14
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	252	1			T11	1		T12	1		T13	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1526	1			T1	19		T3	3		T8	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T12	1		T13	10		T30	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	207	1			T9	1		T32	17		T134	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T14	6		T158	1		T236	9
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T13	12		T33	10		T77	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T13	3		T145	10		T147	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T5	13		T136	16		T148	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T144	8		T175	6		T176	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	319	1			T13	1		T141	2		T43	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	337	1			T11	1		T13	1		T144	13
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16969	1			T2	176		T4	185		T6	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	12	1			T267	12		-	-		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	13	1			T259	13		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	30	1			T263	15		T272	1		T274	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	22	1			T136	15		T273	7		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	159	1			T14	4		T216	15		T159	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	102	1			T216	4		T161	13		T139	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T13	18		T153	4		T139	9
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T13	6		T158	16		T147	7
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	170	1			T44	1		T159	8		T39	5
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T39	15		T148	2		T138	10
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T76	7		T137	9		T213	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	236	1			T11	12		T13	14		T44	12
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1000	1			T197	13		T37	1		T179	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	126	1			T13	2		T30	15		T137	16
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T32	14		T134	13		T240	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	251	1			T158	9		T236	12		T242	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T13	18		T33	7		T77	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T13	8		T145	11		T147	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	214	1			T136	15		T148	6		T221	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	230	1			T175	4		T140	4		T241	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T13	7		T141	14		T148	8
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T11	10		T134	10		T145	7
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	1		T13	12		T33	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	6	42	87.50	6

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2
[auto[1]]	[minimum]	*	--	--	2

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	313	1			T5	1		T13	15		T14	7
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T43	1		T216	5		T16	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	273	1			T13	6		T44	2		T45	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T13	7		T149	1		T147	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	262	1			T76	8		T160	1		T159	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T12	1		T158	17		T44	13
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1268	1			T1	1		T3	3		T8	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T11	13		T12	1		T30	7
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T32	15		T37	2		T178	8
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	181	1			T13	18		T14	1		T30	10
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	163	1			T9	1		T13	5		T134	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T14	3		T16	11		T236	13
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T13	15		T77	13		T145	6
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	11		T158	10		T144	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	189	1			T5	1		T33	8		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	223	1			T134	11		T217	1		T140	3
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T13	8		T141	16		T43	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T11	11		T13	1		T144	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	31	1			T156	1		T267	13		T269	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	46	1			T143	1		T103	13		T107	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17103	1			T2	176		T4	185		T6	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T161	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	283	1			T5	11		T14	1		T43	5
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T43	8		T136	10		T243	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	191	1			T45	11		T57	5		T230	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T13	8		T149	4		T39	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	122	1			T39	3		T213	13		T154	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T44	10		T144	7		T149	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1113	1			T1	18		T228	23		T150	39
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T30	2		T175	7		T250	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T32	16		T37	1		T178	6
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T13	18		T30	9		T149	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	129	1			T134	12		T225	14		T275	13
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T14	2		T16	2		T236	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T13	10		T145	2		T251	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T144	7		T145	9		T175	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T5	12		T33	9		T146	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T134	11		T217	11		T140	14
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	212	1			T43	13		T148	7		T155	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T144	12		T145	10		T175	6
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T156	6		T270	4		T255	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	60	1			T143	11		T103	11		T276	12

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T267	13		T268	3		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T259	14		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	35	1			T243	1		T263	16		T272	2
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	24	1			T136	16		T273	8		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	211	1			T5	1		T14	7		T43	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	129	1			T43	1		T216	5		T161	14
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T13	21		T45	1		T153	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	225	1			T13	7		T158	17		T147	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	205	1			T44	2		T160	1		T159	9
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	131	1			T144	1		T149	1		T39	16
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T76	8		T137	10		T213	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	281	1			T11	13		T12	1		T13	15
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1342	1			T1	1		T3	3		T8	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T12	1		T13	3		T30	17
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T9	1		T32	15		T134	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	301	1			T14	4		T158	10		T236	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T13	20		T33	8		T77	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T13	11		T145	12		T147	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	259	1			T5	1		T136	16		T148	7
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T144	1		T175	5		T176	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	322	1			T13	8		T141	16		T43	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	339	1			T11	11		T13	1		T144	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17103	1			T2	176		T4	185		T6	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T259	14		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	19	1			T243	2		T263	9		T272	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T136	10		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	219	1			T5	11		T14	1		T43	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	93	1			T43	8		T243	9		T139	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	190	1			T45	11		T139	9		T57	5
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	148	1			T13	8		T34	11		T232	2
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	112	1			T39	3		T154	8		T156	16
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	119	1			T144	7		T149	4		T39	2
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	120	1			T213	13		T215	8		T103	4
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T13	9		T44	10		T149	8
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1184	1			T1	18		T228	23		T37	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T13	9		T30	11		T149	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T32	16		T134	12		T219	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T14	2		T236	8		T245	17
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	167	1			T13	10		T33	9		T145	2
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T145	9		T16	2		T140	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T5	12		T136	15		T148	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	237	1			T144	7		T175	5		T176	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	256	1			T43	13		T146	10		T155	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	271	1			T144	12		T134	11		T145	10

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22439

1

T1

1

T2

176

T3

3

auto[1]

auto[0]

4163

1

T1

18

T5

23

T13

36