Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_4

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26602

1

T1

19

T2

176

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23041

1

T1

19

T2

176

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3561

1

T5

12

T9

1

T11

13

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20471

1

T2

176

T4

185

T5

25

auto[1]

6131

1

T1

19

T3

3

T8

2

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22211

1

T1

19

T2

176

T3

3

auto[1]

4391

1

T11

23

T13

85

T14

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	26	1			T176	9		T191	16		T277	1
values[0]	50	1			T33	17		T278	3		T183	19
values[1]	684	1			T9	1		T11	11		T141	1
values[2]	657	1			T158	17		T44	2		T144	13
values[3]	776	1			T5	25		T13	14		T14	5
values[4]	554	1			T12	1		T144	8		T216	16
values[5]	3039	1			T1	19		T3	3		T8	2
values[6]	788	1			T13	35		T30	19		T141	15
values[7]	663	1			T13	17		T158	10		T44	23
values[8]	764	1			T30	9		T32	31		T43	9
values[9]	1498	1			T13	56		T43	6		T77	13
minimum	17103	1			T2	176		T4	185		T6	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	956	1			T9	1		T11	11		T33	17
values[1]	709	1			T5	12		T158	17		T44	2
values[2]	559	1			T5	13		T12	1		T13	14
values[3]	2969	1			T1	19		T3	3		T8	2
values[4]	800	1			T11	13		T12	1		T13	26
values[5]	743	1			T13	9		T14	1		T141	15
values[6]	741	1			T13	17		T158	10		T145	21
values[7]	618	1			T30	9		T32	31		T43	9
values[8]	1039	1			T13	56		T43	6		T77	13
values[9]	351	1			T221	35		T241	19		T246	29
minimum	17117	1			T2	176		T4	185		T6	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22439

1

T1

1

T2

176

T3

3

auto[1]

4163

1

T1

18

T5

23

T13

36

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[maximum]	*	--	--	4

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	287	1			T11	1		T33	10		T144	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T9	1		T141	1		T136	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T158	1		T44	1		T134	13
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	199	1			T5	12		T143	12		T40	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T5	13		T13	2		T14	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	99	1			T12	1		T13	1		T216	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1497	1			T1	19		T3	3		T8	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	259	1			T144	8		T161	1		T245	20
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T13	12		T30	10		T176	13
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	196	1			T11	1		T12	1		T149	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T43	14		T44	11		T76	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T13	1		T14	1		T141	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T145	10		T159	13		T153	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T13	11		T158	1		T146	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T32	17		T43	9		T134	12
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	145	1			T30	3		T175	8		T16	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	304	1			T13	20		T43	6		T77	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	298	1			T13	2		T160	1		T147	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	91	1			T241	11		T82	1		T84	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	80	1			T221	20		T246	16		T247	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16969	1			T2	176		T4	185		T6	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T229	9		T279	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	224	1			T11	10		T33	7		T37	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	263	1			T136	15		T154	7		T140	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	138	1			T158	16		T44	1		T134	13
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T40	1		T250	13		T157	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T13	4		T136	15		T153	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	105	1			T13	7		T216	19		T159	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1012	1			T14	4		T197	13		T179	17
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T161	17		T170	9		T251	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	199	1			T13	14		T30	9		T137	16
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T11	12		T216	10		T148	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T44	12		T76	7		T145	5
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T13	8		T141	14		T161	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	180	1			T145	11		T159	13		T153	4
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T13	6		T158	9		T169	3
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T32	14		T134	10		T145	7
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	121	1			T30	6		T175	2		T39	15
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	230	1			T13	20		T77	12		T16	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	207	1			T13	14		T147	10		T175	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	97	1			T241	8		T84	9		T280	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	83	1			T221	15		T246	13		T247	8
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	1		T13	12		T33	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	4	1			T229	4		-	-		-	-

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for intr_max_v_cond_xp

Uncovered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T176	9		T191	7		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T277	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T33	10		T278	3		T281	11
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T183	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T11	1		T37	2		T148	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T9	1		T141	1		T154	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T158	1		T44	1		T144	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T143	12		T136	16		T240	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	245	1			T5	13		T13	2		T14	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	177	1			T5	12		T13	1		T216	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	104	1			T153	1		T156	17		T253	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	187	1			T12	1		T144	8		T216	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1494	1			T1	19		T3	3		T8	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T11	1		T12	1		T14	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	270	1			T13	12		T30	10		T43	14
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	166	1			T13	1		T141	1		T149	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	184	1			T44	11		T76	1		T145	13
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	172	1			T13	11		T158	1		T146	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	241	1			T32	17		T43	9		T134	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	134	1			T30	3		T39	3		T251	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	403	1			T13	20		T43	6		T77	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	448	1			T13	2		T160	1		T147	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16969	1			T2	176		T4	185		T6	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	9	1			T191	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	7	1			T33	7		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T183	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T11	10		T37	1		T148	8
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	197	1			T154	7		T140	10		T229	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T158	16		T44	1		T134	13
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T136	15		T240	11		T250	13
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T13	4		T136	15		T170	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	125	1			T13	7		T216	4		T40	1
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	93	1			T153	13		T257	12		T187	7
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T216	15		T159	8		T148	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1022	1			T14	4		T197	13		T179	17
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	249	1			T11	12		T216	10		T161	17
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T13	14		T30	9		T147	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T13	8		T141	14		T236	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	156	1			T44	12		T76	7		T145	16
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	151	1			T13	6		T158	9		T161	13
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	222	1			T32	14		T134	10		T145	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T30	6		T39	15		T251	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	328	1			T13	20		T77	12		T16	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	319	1			T13	14		T147	10		T175	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	1		T13	12		T33	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_IN]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	290	1			T11	11		T33	8		T144	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	305	1			T9	1		T141	1		T136	16
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	181	1			T158	17		T44	2		T134	14
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	198	1			T5	1		T143	1		T40	5
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T5	1		T13	6		T14	3
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T12	1		T13	8		T216	21
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1348	1			T1	1		T3	3		T8	2
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	238	1			T144	1		T161	18		T245	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T13	17		T30	10		T176	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	219	1			T11	13		T12	1		T149	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T43	1		T44	13		T76	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T13	9		T14	1		T141	15
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T145	12		T159	14		T153	5
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	218	1			T13	8		T158	10		T146	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	200	1			T32	15		T43	1		T134	11
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	156	1			T30	7		T175	3		T16	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	292	1			T13	22		T43	1		T77	13
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	266	1			T13	16		T160	1		T147	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T241	9		T82	1		T84	10
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	94	1			T221	17		T246	14		T247	9
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17103	1			T2	176		T4	185		T6	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	6	1			T229	5		T279	1		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T33	9		T144	12		T37	1
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	140	1			T136	15		T154	8		T140	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T134	12		T149	4		T243	9
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T5	11		T143	11		T40	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T5	12		T14	2		T136	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	71	1			T140	14		T225	4		T182	8
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	1161	1			T1	18		T14	1		T228	23
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	222	1			T144	7		T245	19		T170	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	183	1			T13	9		T30	9		T176	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T149	13		T148	7		T217	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	177	1			T43	13		T44	10		T45	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T139	9		T236	9		T232	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	147	1			T145	9		T159	12		T139	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	160	1			T13	9		T146	10		T169	4
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T32	16		T43	8		T134	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T30	2		T175	7		T39	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T13	18		T43	5		T176	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T175	11		T39	3		T219	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	75	1			T241	10		T282	11		T283	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	69	1			T221	18		T246	15		T166	9
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	8	1			T229	8		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	4	44	91.67	4

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1
[auto[1]]	[maximum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	11	1			T176	1		T191	10		-	-
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T277	1		-	-		-	-
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	10	1			T33	8		T278	1		T281	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	10	1			T183	10		-	-		-	-
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T11	11		T37	2		T148	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	228	1			T9	1		T141	1		T154	8
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T158	17		T44	2		T144	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	193	1			T143	1		T136	16		T240	12
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	279	1			T5	1		T13	6		T14	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T5	1		T13	8		T216	5
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	123	1			T153	14		T156	1		T253	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T12	1		T144	1		T216	16
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1359	1			T1	1		T3	3		T8	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	289	1			T11	13		T12	1		T14	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T13	17		T30	10		T43	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	188	1			T13	9		T141	15		T149	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T44	13		T76	8		T145	18
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	186	1			T13	8		T158	10		T146	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	267	1			T32	15		T43	1		T134	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T30	7		T39	16		T251	8
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	413	1			T13	22		T43	1		T77	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	398	1			T13	16		T160	1		T147	11
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17103	1			T2	176		T4	185		T6	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	14	1			T176	8		T191	6		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	21	1			T33	9		T278	2		T281	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T183	9		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	140	1			T37	1		T243	2		T217	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T154	8		T140	10		T229	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	172	1			T144	12		T134	12		T149	4
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	123	1			T143	11		T136	15		T250	12
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T5	12		T14	2		T136	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	144	1			T5	11		T40	1		T140	14
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	74	1			T156	16		T171	13		T257	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	153	1			T144	7		T148	7		T170	9
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	1157	1			T1	18		T14	1		T228	23
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	234	1			T217	11		T245	19		T242	12
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T13	9		T30	9		T43	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	135	1			T149	13		T236	9		T232	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	142	1			T44	10		T145	11		T159	12
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	137	1			T13	9		T146	10		T169	4
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	196	1			T32	16		T43	8		T134	11
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	101	1			T30	2		T39	2		T251	7
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	318	1			T13	18		T43	5		T16	2
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	369	1			T175	18		T39	3		T213	13

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22439

1

T1

1

T2

176

T3

3

auto[1]

auto[0]

4163

1

T1

18

T5

23

T13

36