Unified Coverage Report :: Group Instance : adc_ctrl_filter_cg_1_2

Summary for Variable clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for clk_gate_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26602

1

T1

19

T2

176

T3

3

---

Summary for Variable cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cond_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[ADC_CTRL_FILTER_COND_IN]

23224

1

T1

19

T2

176

T3

3

auto[ADC_CTRL_FILTER_COND_OUT]

3378

1

T9

1

T11

11

T12

2

---

Summary for Variable en_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for en_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

20613

1

T2

176

T4

185

T6

14

auto[1]

5989

1

T1

19

T3

3

T5

25

---

Summary for Variable interrupt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for interrupt_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22211

1

T1

19

T2

176

T3

3

auto[1]

4391

1

T11

23

T13

85

T14

4

---

Summary for Variable max_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	0	12	100.00

User Defined Bins for max_v_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
maximum	63	1			T145	39		T284	1		T285	1
values[0]	117	1			T13	24		T185	1		T263	12
values[1]	614	1			T5	12		T11	11		T14	5
values[2]	801	1			T12	1		T141	15		T216	11
values[3]	769	1			T11	13		T12	1		T149	5
values[4]	803	1			T13	11		T158	10		T43	6
values[5]	946	1			T9	1		T13	48		T14	1
values[6]	720	1			T13	12		T30	28		T159	9
values[7]	706	1			T13	21		T158	17		T45	12
values[8]	598	1			T33	17		T144	13		T134	48
values[9]	3362	1			T1	19		T3	3		T5	13
minimum	17103	1			T2	176		T4	185		T6	14

---

Summary for Variable min_v_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	12	1	11	91.67

User Defined Bins for min_v_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
maximum	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	929	1			T5	12		T11	11		T12	1
values[1]	742	1			T149	5		T148	3		T138	11
values[2]	798	1			T11	13		T12	1		T216	11
values[3]	937	1			T13	34		T32	31		T158	10
values[4]	743	1			T9	1		T13	25		T14	1
values[5]	839	1			T13	33		T30	28		T149	9
values[6]	2821	1			T1	19		T3	3		T8	2
values[7]	646	1			T13	5		T14	8		T144	21
values[8]	825	1			T13	1		T44	2		T77	13
values[9]	202	1			T5	13		T143	12		T216	16
minimum	17120	1			T2	176		T4	185		T6	14

---

Summary for Variable wakeup_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wakeup_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

22439

1

T1

1

T2

176

T3

3

auto[1]

4163

1

T1

18

T5

23

T13

36

---

Summary for Cross intr_min_v_cond_xp

Samples crossed: interrupt_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for intr_min_v_cond_xp

Element holes

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

interrupt_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	229	1			T5	12		T13	10		T76	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	273	1			T11	1		T12	1		T14	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T149	5		T236	9		T34	6
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	165	1			T148	1		T138	1		T156	17
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	244	1			T11	1		T216	1		T156	7
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	203	1			T12	1		T136	11		T155	8
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	271	1			T13	12		T141	1		T43	6
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T13	1		T32	17		T158	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T43	14		T148	8		T249	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T9	1		T13	11		T14	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	215	1			T30	3		T159	1		T37	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T13	13		T30	10		T149	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1526	1			T1	19		T3	3		T8	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	133	1			T134	12		T169	5		T41	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	169	1			T14	4		T144	8		T175	6
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	209	1			T13	1		T144	13		T34	12
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	261	1			T44	1		T77	1		T145	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	191	1			T13	1		T144	8		T149	14
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	51	1			T5	13		T137	1		T217	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	42	1			T143	12		T216	1		T140	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16985	1			T2	176		T4	185		T6	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T185	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	226	1			T13	14		T76	7		T216	4
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T11	10		T141	14		T44	12
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T236	12		T34	8		T229	4
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	169	1			T148	2		T138	10		T186	17
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T11	12		T216	10		T225	7
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	138	1			T136	15		T155	4		T236	11
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	227	1			T13	13		T136	15		T153	4
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	239	1			T13	8		T32	14		T158	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T148	6		T260	10		T242	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	154	1			T13	14		T145	5		T175	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	192	1			T30	6		T159	8		T37	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	216	1			T13	20		T30	9		T161	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1076	1			T33	7		T158	16		T197	13
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	86	1			T134	10		T169	3		T214	8
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	160	1			T14	4		T175	4		T240	11
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	108	1			T13	4		T34	10		T229	1
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T44	1		T77	12		T145	7
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T145	11		T175	2		T153	13
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T137	16		T241	8		T266	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	53	1			T216	15		T140	4		T198	12
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	1		T13	12		T33	2

---

Summary for Cross intr_max_v_cond_xp

Samples crossed: interrupt_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	2	46	95.83	2

Automatically Generated Cross Bins for intr_max_v_cond_xp

Element holes

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	--	--	2

Covered bins

interrupt_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	24	1			T145	11		T285	1		T280	5
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	12	1			T145	10		T284	1		T91	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	50	1			T13	10		T263	1		T87	9
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	15	1			T185	1		T286	1		T265	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T5	12		T76	1		T216	1
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T11	1		T14	5		T43	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	213	1			T216	1		T155	1		T236	9
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T12	1		T141	1		T148	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T11	1		T149	5		T156	7
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T12	1		T136	11		T156	15
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	238	1			T13	2		T43	6		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	178	1			T13	1		T158	1		T147	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	248	1			T13	10		T141	1		T43	14
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	233	1			T9	1		T13	11		T14	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T30	3		T159	1		T176	9
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T13	10		T30	10		T161	1
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	166	1			T158	1		T45	12		T37	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	190	1			T13	3		T149	9		T169	5
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T33	10		T134	13		T161	1
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	182	1			T144	13		T134	12		T34	12
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1702	1			T1	19		T3	3		T5	13
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	258	1			T13	2		T144	8		T149	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	16969	1			T2	176		T4	185		T6	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	16	1			T145	7		T287	9		-	-
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T145	11		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	49	1			T13	14		T263	11		T87	12
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	3	1			T265	3		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	113	1			T76	7		T216	4		T17	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T11	10		T44	12		T38	2
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	239	1			T216	10		T236	12		T34	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	167	1			T141	14		T148	2		T138	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	198	1			T11	12		T225	7		T42	1
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	149	1			T136	15		T288	12		T91	3
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	203	1			T136	15		T153	4		T213	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	184	1			T13	8		T158	9		T147	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	218	1			T13	13		T148	6		T222	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	247	1			T13	14		T32	14		T145	5
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	152	1			T30	6		T159	8		T221	7
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	161	1			T13	2		T30	9		T161	13
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	193	1			T158	16		T37	1		T40	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	157	1			T13	18		T169	3		T214	8
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	182	1			T33	7		T134	13		T161	17
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T134	10		T34	10		T106	4
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1159	1			T14	4		T44	1		T77	12
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	243	1			T13	4		T216	15		T175	2
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T11	1		T13	12		T33	2

---

Summary for Cross wakeup_min_v_cond_xp

Samples crossed: wakeup_cp min_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	5	43	89.58	5

Automatically Generated Cross Bins for wakeup_min_v_cond_xp

Element holes

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[maximum]	*	--	--	2
[auto[1]]	[maximum]	*	--	--	2

Uncovered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	min_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	276	1			T5	1		T13	15		T76	8
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	274	1			T11	11		T12	1		T14	3
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	237	1			T149	1		T236	13		T34	9
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	202	1			T148	3		T138	11		T156	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	253	1			T11	13		T216	11		T156	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T12	1		T136	16		T155	5
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	282	1			T13	17		T141	1		T43	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	275	1			T13	9		T32	15		T158	10
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	206	1			T43	1		T148	7		T249	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	201	1			T9	1		T13	15		T14	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	242	1			T30	7		T159	9		T37	2
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	262	1			T13	24		T30	10		T149	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1413	1			T1	1		T3	3		T8	2
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	110	1			T134	11		T169	4		T41	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T14	7		T144	1		T175	5
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	141	1			T13	5		T144	1		T34	11
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	255	1			T44	2		T77	13		T145	8
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	204	1			T13	1		T144	1		T149	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	69	1			T5	1		T137	17		T217	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	61	1			T143	1		T216	16		T140	5
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17104	1			T2	176		T4	185		T6	14
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_OUT]	1	1			T185	1		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	179	1			T5	11		T13	9		T146	10
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T14	2		T43	8		T44	10
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	171	1			T149	4		T236	8		T34	5
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	132	1			T156	16		T186	18		T90	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	204	1			T156	6		T225	10		T42	1
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T136	10		T155	7		T236	9
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	216	1			T13	8		T43	5		T136	15
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T32	16		T159	12		T243	9
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	173	1			T43	13		T148	7		T242	12
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	163	1			T13	10		T145	2		T175	6
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	165	1			T30	2		T37	1		T243	11
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	170	1			T13	9		T30	9		T149	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	1189	1			T1	18		T33	9		T45	11
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	109	1			T134	11		T169	4		T214	10
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	128	1			T14	1		T144	7		T175	5
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	176	1			T144	12		T34	11		T106	2
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	208	1			T145	10		T176	12		T39	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	158	1			T144	7		T149	13		T145	9
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	38	1			T5	12		T217	10		T241	10
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	34	1			T143	11		T140	4		T245	19
auto[1]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	15	1			T189	15		-	-		-	-

---

Summary for Cross wakeup_max_v_cond_xp

Samples crossed: wakeup_cp max_v_cp cond_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	48	3	45	93.75	3

Automatically Generated Cross Bins for wakeup_max_v_cond_xp

Element holes

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[minimum]	*	--	--	2

Uncovered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[minimum]	[auto[ADC_CTRL_FILTER_COND_OUT]]	0	1	1

Covered bins

wakeup_cp	max_v_cp	cond_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T145	8		T285	1		T280	1
auto[0]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	14	1			T145	12		T284	1		T91	1
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	56	1			T13	15		T263	12		T87	13
auto[0]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	7	1			T185	1		T286	1		T265	4
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	148	1			T5	1		T76	8		T216	5
auto[0]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	200	1			T11	11		T14	3		T43	1
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	274	1			T216	11		T155	1		T236	13
auto[0]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	213	1			T12	1		T141	15		T148	3
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	240	1			T11	13		T149	1		T156	1
auto[0]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	179	1			T12	1		T136	16		T156	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	246	1			T13	2		T43	1		T160	1
auto[0]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	220	1			T13	9		T158	10		T147	8
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	264	1			T13	15		T141	1		T43	1
auto[0]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	300	1			T9	1		T13	15		T14	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	201	1			T30	7		T159	9		T176	1
auto[0]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	194	1			T13	3		T30	10		T161	14
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	228	1			T158	17		T45	1		T37	2
auto[0]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	195	1			T13	21		T149	1		T169	4
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	221	1			T33	8		T134	14		T161	18
auto[0]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	88	1			T144	1		T134	11		T34	11
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1537	1			T1	1		T3	3		T5	1
auto[0]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	291	1			T13	6		T144	1		T149	1
auto[0]	minimum	auto[ADC_CTRL_FILTER_COND_IN]	17103	1			T2	176		T4	185		T6	14
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_IN]	20	1			T145	10		T280	4		T287	6
auto[1]	maximum	auto[ADC_CTRL_FILTER_COND_OUT]	9	1			T145	9		-	-		-	-
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_IN]	43	1			T13	9		T87	8		T262	14
auto[1]	values[0]	auto[ADC_CTRL_FILTER_COND_OUT]	11	1			T188	11		-	-		-	-
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_IN]	119	1			T5	11		T146	10		T139	2
auto[1]	values[1]	auto[ADC_CTRL_FILTER_COND_OUT]	147	1			T14	2		T43	8		T44	10
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_IN]	178	1			T236	8		T34	5		T229	8
auto[1]	values[2]	auto[ADC_CTRL_FILTER_COND_OUT]	136	1			T236	9		T156	16		T171	18
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_IN]	186	1			T149	4		T156	6		T225	10
auto[1]	values[3]	auto[ADC_CTRL_FILTER_COND_OUT]	164	1			T136	10		T156	14		T229	11
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_IN]	195	1			T43	5		T136	15		T213	13
auto[1]	values[4]	auto[ADC_CTRL_FILTER_COND_OUT]	142	1			T155	7		T243	9		T18	1
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_IN]	202	1			T13	8		T43	13		T148	7
auto[1]	values[5]	auto[ADC_CTRL_FILTER_COND_OUT]	180	1			T13	10		T32	16		T145	2
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_IN]	154	1			T30	2		T176	8		T221	8
auto[1]	values[6]	auto[ADC_CTRL_FILTER_COND_OUT]	171	1			T13	9		T30	9		T217	18
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_IN]	131	1			T45	11		T37	1		T40	1
auto[1]	values[7]	auto[ADC_CTRL_FILTER_COND_OUT]	152	1			T149	8		T169	4		T214	10
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_IN]	134	1			T33	9		T134	12		T175	5
auto[1]	values[8]	auto[ADC_CTRL_FILTER_COND_OUT]	155	1			T144	12		T134	11		T34	11
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_IN]	1324	1			T1	18		T5	12		T14	1
auto[1]	values[9]	auto[ADC_CTRL_FILTER_COND_OUT]	210	1			T144	7		T149	13		T143	11

---

Summary for Cross wakeup_gated_xp

Samples crossed: wakeup_cp clk_gate_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	2	2	50.00	2

Automatically Generated Cross Bins for wakeup_gated_xp

Element holes

wakeup_cp	clk_gate_cp	COUNT	AT LEAST	NUMBER	STATUS
*	[auto[1]]	--	--	2

Covered bins

wakeup_cp

clk_gate_cp

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

22439

1

T1

1

T2

176

T3

3

auto[1]

auto[0]

4163

1

T1

18

T5

23

T13

36